TWI341566B - Bump structure, method of forming bump structure, and semiconductor apparatus using the same - Google Patents

Bump structure, method of forming bump structure, and semiconductor apparatus using the same

Info

Publication number
TWI341566B
TWI341566B TW096115056A TW96115056A TWI341566B TW I341566 B TWI341566 B TW I341566B TW 096115056 A TW096115056 A TW 096115056A TW 96115056 A TW96115056 A TW 96115056A TW I341566 B TWI341566 B TW I341566B
Authority
TW
Taiwan
Prior art keywords
bump structure
same
semiconductor apparatus
forming
forming bump
Prior art date
Application number
TW096115056A
Other languages
English (en)
Other versions
TW200809993A (en
Inventor
Yuji Yano
Kazuo Tamaki
Original Assignee
Sharp Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Kk filed Critical Sharp Kk
Publication of TW200809993A publication Critical patent/TW200809993A/zh
Application granted granted Critical
Publication of TWI341566B publication Critical patent/TWI341566B/zh

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/06Measuring leads; Measuring probes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05568Disposition the whole external layer protruding from the surface
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
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    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13012Shape in top view
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    • H01L2224/13001Core members of the bump connector
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    • H01L2224/13016Shape in side view
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    • H01L2224/1301Shape
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    • H01L2224/13017Shape in side view being non uniform along the bump connector
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16104Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/16106Disposition relative to the bonding area, e.g. bond pad the bump connector connecting one bonding area to at least two respective bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
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    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/7825Means for applying energy, e.g. heating means
    • H01L2224/783Means for applying energy, e.g. heating means by means of pressure
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    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
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    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/013Alloys
    • H01L2924/014Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Wire Bonding (AREA)
TW096115056A 2006-05-01 2007-04-27 Bump structure, method of forming bump structure, and semiconductor apparatus using the same TWI341566B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006127813A JP4216295B2 (ja) 2006-05-01 2006-05-01 バンプ構造およびその形成方法、ならびにそれを用いた半導体装置

Publications (2)

Publication Number Publication Date
TW200809993A TW200809993A (en) 2008-02-16
TWI341566B true TWI341566B (en) 2011-05-01

Family

ID=38647582

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096115056A TWI341566B (en) 2006-05-01 2007-04-27 Bump structure, method of forming bump structure, and semiconductor apparatus using the same

Country Status (5)

Country Link
US (1) US7683484B2 (zh)
JP (1) JP4216295B2 (zh)
KR (1) KR100884520B1 (zh)
CN (1) CN101068012A (zh)
TW (1) TWI341566B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI384603B (zh) 2009-02-17 2013-02-01 Advanced Semiconductor Eng 基板結構及應用其之封裝結構
US8008785B2 (en) 2009-12-22 2011-08-30 Tessera Research Llc Microelectronic assembly with joined bond elements having lowered inductance
US9082763B2 (en) * 2012-03-15 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Joint structure for substrates and methods of forming
KR101977391B1 (ko) 2018-05-31 2019-08-28 주식회사 동부아이씨티 열영상 기반의 교통 신호 제어 방법 및 장치

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0429389A (ja) 1990-05-24 1992-01-31 Hitachi Chem Co Ltd フレキシブルプリント配線板
JPH0529389A (ja) 1991-07-22 1993-02-05 Sharp Corp 半導体素子の接続構造
JP3259377B2 (ja) 1992-11-06 2002-02-25 ソニー株式会社 半導体装置
JP2735022B2 (ja) 1995-03-22 1998-04-02 日本電気株式会社 バンプ製造方法
US5842628A (en) 1995-04-10 1998-12-01 Fujitsu Limited Wire bonding method, semiconductor device, capillary for wire bonding and ball bump forming method
US6225143B1 (en) * 1998-06-03 2001-05-01 Lsi Logic Corporation Flip-chip integrated circuit routing to I/O devices
JP2000311915A (ja) 1998-10-14 2000-11-07 Texas Instr Inc <Ti> 半導体デバイス及びボンディング方法
JP2001176908A (ja) 1999-12-17 2001-06-29 Matsushita Electronics Industry Corp 半導体装置の製造方法
JP2001189338A (ja) 1999-12-28 2001-07-10 Fujitsu Ltd 半導体装置、半導体装置の製造方法及び試験方法
JP2002076048A (ja) 2000-09-05 2002-03-15 Sony Corp フリップチップ接続によるバンプの配置方法
JP3913134B2 (ja) 2002-08-08 2007-05-09 株式会社カイジョー バンプの形成方法及びバンプ
JP2002329742A (ja) 2001-05-07 2002-11-15 Mitsubishi Electric Corp 半導体装置
US7229906B2 (en) * 2002-09-19 2007-06-12 Kulicke And Soffa Industries, Inc. Method and apparatus for forming bumps for semiconductor interconnections using a wire bonding machine
TWI221664B (en) * 2002-11-07 2004-10-01 Via Tech Inc Structure of chip package and process thereof
JP2004172477A (ja) * 2002-11-21 2004-06-17 Kaijo Corp ワイヤループ形状、そのワイヤループ形状を備えた半導体装置、ワイヤボンディング方法及び半導体製造装置
JP3854232B2 (ja) 2003-02-17 2006-12-06 株式会社新川 バンプ形成方法及びワイヤボンディング方法
US6815836B2 (en) * 2003-03-24 2004-11-09 Texas Instruments Incorporated Wire bonding for thin semiconductor package
US20050133928A1 (en) * 2003-12-19 2005-06-23 Howard Gregory E. Wire loop grid array package

Also Published As

Publication number Publication date
US20070252272A1 (en) 2007-11-01
KR100884520B1 (ko) 2009-02-18
JP2007300000A (ja) 2007-11-15
CN101068012A (zh) 2007-11-07
KR20070106935A (ko) 2007-11-06
JP4216295B2 (ja) 2009-01-28
TW200809993A (en) 2008-02-16
US7683484B2 (en) 2010-03-23

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