TWI336519B - Semiconductor device and electronic apparatus capable of detecting open wire using weak current - Google Patents

Semiconductor device and electronic apparatus capable of detecting open wire using weak current Download PDF

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Publication number
TWI336519B
TWI336519B TW093124781A TW93124781A TWI336519B TW I336519 B TWI336519 B TW I336519B TW 093124781 A TW093124781 A TW 093124781A TW 93124781 A TW93124781 A TW 93124781A TW I336519 B TWI336519 B TW I336519B
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Taiwan
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semiconductor device
voltage
output
terminal
pad
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TW093124781A
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English (en)
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TW200511558A (en
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Isao Yamamoto
Koichi Miyanaga
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Rohm Co Ltd
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Publication of TW200511558A publication Critical patent/TW200511558A/zh
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Publication of TWI336519B publication Critical patent/TWI336519B/zh

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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
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    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Automation & Control Theory (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Description

1336519 九、發明說明： 【發明所屬之技術領域】 本發明係關於半導體裝置及電子褒置，特別係關於内· 建ic晶片，利用接合引線（以下簡稱為「引線」）連接ic 晶片側的銲墊與IC的外部端子（以下簡稱為「端子」）之 半導體裝置以及搭載該半導體裝置之電子裝置。 【先前技術】 古根據不同的半導體裝置的規格，而有要求流通較大電 =之訊號。此種情形，以使該訊號連接於lc晶片❸複數個# 銲墊:再利用複數個料分担電流之構成已為眾所周知。 由於係形成利用各個引線由該等複數個銲墊連接至外部端 子’因此在外觀上可看出1個端子顯現出1條訊號線。然·： 而’其内部中’係2條引線由2個銲墊連接於工個端子上。：· 在上述構成中，只要2條引線令的其中一條發生開線 (open)故障’即無法產生所需之電流值’同時因過電流會 L於幻餘的一條引線，而導致該條引線的長期可靠性降 低等缺失。但’即使在其中一條引線斷裂的狀態下，由於 該訊號本身依然會顯現於端子’因此在—般的實驗中亦不 易進行故障的判斷。為解決上述之問題，—種利用電阻連 接鋒塾間’以檢測因開線故障而導致之電阻值變化之技術 已為眾所周知（專利申請文獻1 )。 [專利文獻1] 曰本專利特開平11-111785號公報 【發明内容] 316179 5 1336519 (發明所欲解決之課題） 然而’以專利文獻1的技術為例，不流通相當程度的 測試電流使電壓下降即無法進行故障的判斷。然而，除了 有時無法由測試器流通大的電流之外，為了不因測試電流.. 使引線產生負載，亦期望能以微弱的電流進行檢測。 本發明係有鑑於上述課題而研創者，其目的在於提供 一種能以微弱的測試電流進行故障判斷之半導體裝置以及 搭載該半導體裝置之電子裝置。 (解決課題之手段） 籲 本發明之半導體裝置係具有：具有第丨銲墊以及第2 得塾之1C晶片；以及連接於前述第！銲墊以及第2鲜塾兩 方之端子，而將連接於第1銲墊之第1訊號與連接於第2 鋒整之第2訊號利用二極體予以麵合。二極體可以僅放置 1個在電流由第1訊號流入第2訊號的流通方向，或僅放 置1個在其相反方向，或放置於兩方亦可。
不：採取任何方式’發生開線時，連接於第㈤ 第2訊號之電路在IC晶片内部即無法產生作動，或者和 二極體的順方向降下電壓，於诘 ㈣原夕电i於減電測试，亦即在由較低 原電I之K中’因錯誤訊息會*平常 得以檢測出故障。藉由使用-榀μ 职兄猎此 行該測試。θ由❹’即可以微弱的電流 在該半導體裝置t，鲁針、+、ia_ 導體裝置尚具有：將電源；二、子為輪入端子時，該半 源電壓產生標帽之"二：加於輸入端子時，由該電 控制電路；以及輸出產生之標的電 316179 6 1336519 壓：輸出端子’而控制電路亦可形成以第i訊號以及第2 :唬之兩個系統接收電源電壓以產生前述標的電壓之構 造。 #他實施態樣上’在該半導體裝置中，前述端子為 :出端子時’該半導體農置尚具有：施加有預定的電源電 姿之輸入端子；以及由該電源電壓產生標的電壓之控制電 路’使前述標的電壓傳輸至前述第丨訊號或第2訊號的盆 中之一。 八 本發明之另-實施態樣中，半導體裝置係包含：施加# 有電源電壓之輸入端子；由電源電壓產生標的電壓之控制 電路；以及輸出所產生之標的電壓之輸出端子，而在輪入 1子或輪出端子的至少其中—方，配置複數個冗晶片侧的 銲墊以將讯唬傳輸路徑予以多重化的同時，利用二極體將： 經多重化之訊號傳輸路徑間予耦合。 本發明之又另一實施例，係關於電子裝置。該電子裝 置係搭载半導體裝置與負載裝置。半導體裝置包含：施加 有電源電壓之輸入端子；由前述電源電壓產生標的電壓之參 控制電路，以及輸出所產生之標的電壓之輸出端子，而在 輸入端子或輸出端子的至少其中一方，配置複數個Ic晶片 侧的銲墊’以將訊號傳輸路徑予以多重化的同時，利用二 極體在前述半導體裝置内部或半導體裝置與前述負裁裝^ 之間的位置’將經多重化之訊號傳輸路徑間予以麵合。 【實施方式】 名1貫施例 316179 7 第i圖係顯示本實施例之半導體裝置的電路。Ic晶片 11構成串聯調痛器（series regulat〇r)。IC晶片^ i係具備： 輪入來自電源之輪入電壓Vi之輸入用銲墊Pil;輪出 控制標的之輸出電摩vo之輸出用鲜塾pol;以及將輸出於 外部的輸出電壓ν〇做為復位電壓Vfb進行反饋之復位用、 銲墊ΡΠ。 攻姐用 在輸入用銲墊Pil與輸出用銲墊p〇1之間連接 PMOS型的電晶體Q卜此外，在輸出 銲墊Pfl之間，則遠桩古，v ; a心 /、仅位用 1财接有以由則者朝後者之方向為 ，第L二極體D1以及其逆方向之第2二極體D2。另^ 進灯後述之開線故障檢測時並不需要使用第2二極 可將其省略。以下將第！、第2二極體D 間早地統稱為「二極體」。 在運算放大器0P1的反轉輸入端子（一）中 電昼广，並在非反轉輸入端子（+ )中輸，準 = 使復位電壓州分壓後之比較對象電^ 十 土；電^ Verf與比較對象電壓Vfb，的差份則由 养放大器0P1輸出，並描供早+s 產伤則由運 *並扼供予電晶體Q1的閘極。 半導體裝置2i具有料導線端子之輸人端子阳 出^子〜2。輸人端子Pi2_用輪人 ^ 入用銲墊Pil，而耠φ 逆接於輸 :登1而輸出知子？〇2則利用輸 於輸出用銲墊Ρο1。此外，輸出端子ρ〇 1連接
Wfl連接於復位用銲墊pfl。 口 〈位引線 如圖中的虛線所示，做為泰、、后4 β 為1"/原之電池ΒΑΤ係連接於輸 8 316179 1336519 入端子Pl2 ’並可供應例如（5V的輸入電壓v P〇2則可輸出例如3 ()v的輸出㈣％ :出端子 半導體裝置21中進行控制成使基準電：' 31 °在 電壓Vfb，相等。 ref與比較對象 本實施例中，在IC晶片u的内部，將 輪出用鋅墊Pol與復位用銲墊pfl之間。未—接於 m復靖wfl開線，即無法形成復位， 會上昇至大致與輸人電壓Vi同等的電壓輸出電壓 負載裝置31產座4口/复-丄 ft將導致 的發生。㈣。稭由配置二極體，即可迴避該問題 第2圖係顯示開線故障的檢測原理。测試 :子Γ二中施加由0緩緩上昇的電壓（以下稱之為「二式 二電塗」，並以Vti標示該電壓），此時即對 出 …心電壓（以下稱之為「測試輸出 以輸: 標=該電壓）進行觀察。在該圖中，粗的實線 正吊的狀‘4，虛線（b )顯示輸出引線Wq1斷裂 业:、丁 而'點鏈線“）則顯示復位引線Wfl斷裂時二各二’ 況下之Vt〇對Vti的作動。但，為清楚明示，二條線2 的重覆部份則將線錯開顯示。 ’、，，%上 (1 )正常時 #。Vo相當 。繼之，一 維持Vto = 一直到Vti= Vo為止，Vt〇無法有效地顯 於電晶體Q1開始進行作動時之源極/汲極電壓 直到Vto = Vfb為止，vto以線性增加。之德， Vfb。 316179 9 (2 )輸出引線Wo 1斷裂時 —直到 Vti = Vo + Vf 為 1卜，. 為雷曰舻m认 t0無法有效地顯現。Vf 為電-體Q1的順方向下降電壓 Vf 體Q1的汲極㈣第i電晶體D1 :二為.VtQ係由電晶 輪屮她工D， 电曰曰體01、设位引線Wfi而出現於 ⑶1 X之故°因此’可藉由減電測試發現故障。 (3 )復位引線Wfl斷裂時 在VU= Vo的條件下，Vt〇有 性增加之點係與⑴相同。秋而丈;：=’之後，。呈線 即無法停止，而會-直㈤加到在VtG=Vfb的條件下 持节數佶甘田 直θ加到Vt〇=Vfb+Vf。之後，則維 d/後Vfb，係為輸出電壓通過第1二極體 障現的㈣之故。因此’同樣可藉由減電測試發現故 H ’除上述的情況外，還有可能有輸入引線則的 :線朴。此時，即使VtiJ[生變化，vt〇也不會顯現， 故可以輕易地檢測出。 、上根據本具％例，藉由使用二極體，即能以微弱 =之測試檢測出開線故障。此外，即使其中-條引線斷 用—極體使輸出電壓與復位電壓維持在比較 I的數i目此得以減輕因輸出電壓變得過大而導致負 載裝置31產生損傷之可能性。 12實施例 々第3圖係顯示本實施例之半導體裝置的電路。以下， 。第1貝施例相备之構造標示相同之符號，並省略其說 明。本實施例與第1實施例的相異點在於：本實施例存在 316179 10 1336519 兩個利用作調節器的電晶 $ 1 a,, π 第1電日日體Q1的配置係與 弟1貝施例相同。追加的第2 汲炻介彻膂！ 士 幕日日體Q2，其閘極、源極、 及極亦與第i電晶體Q1共通 第1電晶體Q1進行相同作動 # tB曰體Q2係與 „ 動 在本貫施例中，即使11 晶體的尺寸較小，亦可葬“里 r卩使各電 駆叙At七 由配置兩個電晶體而確保必要的 驅動此力。以上構成之開線 13實施例 饱剔糸與第1貫施例相同。 第4圖係顯示本實施例之半導體裝置的電路。 與第2實施例相當之構造俨_ 下 田稱以才示不相同之符號，並省略1今 明。本實施例與第2實施例的相里 /… 々目/、點在於.在輸入側西p署 兩個銲墊而不是在輸出側，並 - 在5亥處配置二極體。因此， 在本貫施例中，控制電路传开{士 γ .,φ ^ 係形成糟由兩個銲墊的兩系統接 收電池電壓而產生標的電壓的 ^ 雄a 旳構成。如第4圖所示，新設 第2輸入用鲜塾pi 1 a，並將盆 卫將其以弓丨線連接於輸入端子Pi2。 另一方面，廢除復位用銲墊Pfl，同時亦廢除p、第2 二極體D1、D2，而將第1、笛 ^ ± 弟1 # 2電晶體Qi、Q2之汲極直 接連接於輸出用銲墊PGl。第1電晶體Qi的源極係盘第2 實施例相同’但第2電晶體Q2的源極係連接於新設之輪 入用録塾pila’並在第2電晶體Q2與第i電晶體Q1的沒 極間，連接有以由前者朝後者之方向為順方向之第3二極 ϋΜα及逆方向之第4二極體D4。以上構成之開線的檢 測係利用以下之方法進行。 (1 )新設的輸入引線Wila斷裂時 由於第2電晶體Q2的源極電位由Vti下降第4二極 316179 11 1336519 體D4的順方向下降電壓vf之份量，故使得第2電晶體 Q2的導通程式變弱。結果，因IC晶片^體的驅動能力 ::::利用輸入端子P〇2監視驅動電流’即可檢測出 开、 ，即使引線斷裂’藉由使第2電晶體Q2進行 一定程度的作動’即可避免第1電晶體Q1負荷過度的負 擔。 只 (2 )最初就存在的引線Wi丨斷裂時 可利用與（1 )相同的方法進行檢測。 (3 )原本的引線Wo 1斷裂時 當然，即使vti產生變化M旦由於Vt〇未顯現， 輕易地檢測出。 .第4實施例 第5圖係顯示本實施例之半導體裝置的電路。餘a 例係結合第2以及第3實施例，不論是在輸入側或心： 均配置兩個銲墊。亦即，輸入側係與第3實施例為相 構成，而輸出側則與第2實施例為相同之構成。因此， 入側之開線檢測可利用與第3實施例相同之方法，而辁兩 侧之開線的檢測則可利用與第2實施例相同之方法。〜出 本實施例同時具有第2實施例與第3實施例之效果。 首先，本實施例能以微弱的電流檢測出開線故障。並且，。 即使輸出側的引線產生斷裂亦不容易對負載裝置Μ、告’ 損傷。再者，即使輸入側的引線產生斷裂，也不會^成 電晶體產生過負載。不論是輸出或輸人，因路徑的θ多重1何 故本實施例適於進行大電流的驅動。 ’ 316179 12 的概念構成n::::半導體裝置之電子機器 的内部’在此則將其配置在外部 第| “也例中，輸出用銷ρ。 在第1 例中則新設復位專用銷Pf2/兼為设位㈣’但在本實施 ίΓΓ刷基板41上，安裝有半導體裝置21 ;導體裝置21的輸出端子Ρ。2與負鮮 端子本係利用形成於印刷基板41之輸出用配 用配線L。上/，導體裝置21的復位專用銷Pf2與輸出 、 的點N則湘復位用配線L f加以連接。利用 圖二配線將輸入電壓Vi施加於輸入端子扣。第丨二極體 係以由輪出用配線Lo朝復位用配線Lf的方向，第2 ^極體〇2則以與其相反之方向，分別在印刷基板上相連 根據以上之構成，即使半導體裝置21内部未且有二 極體，但亦可獲得與第丨實施例相同之效果，亦即負. 置31的保護與開線的檢測變得十分容易。另外，根據本實 施例’在印刷基板安裝測試步驟中，不但可以檢測出半導 體裝置21内部的開線，將半導體裝置2i安裝於印刷基板 4工時因輸出用銷Po2、復位專用銷pf2的焊接不良所引起 之開線故障亦可檢測出。 一以上，根據實施例說明本發明。上述之實施例均為例 示性’其可涵蓋各種的變形例，且各個變形例亦屬於本發 316179 13 丄 明之範圍當為同業者所能理解。 ，例如:本實施例中，使用M〇s電晶體。但，電 當然可以是雙極型電晶體。 佝於告丨當：中係以串聯調節器做為控制電路來說明, :的：：:路亦可具備開關調節器、充電泵型調節陶 11 31 41 Pil P〇2 V〇 Pfl Ql Dl 【圖式簡單說明】 顯示第1實施例之半導體裝置的構成圖。 第2圖為檢測出第1實施例之丰暮，驻罢从β Μ # 原理之顯示圖。 k+導體裝置的開線故障=3圖為顯示第2實施例之半導體裝置的構成圖。 圖為顯示第3實施例之半導體裝置的構成圖。^圖為顯示第4實施例之半導體裝置的構成圖。目為顯示第5實施例之電子裝置的構成圖。 L主要元件符號說明】 1C晶片 負载裝置 印刷基板 Plla輸入用銲墊 輸出端 輪出電壓 復位用 第1電 第1二 子 銲墊 B曰 極 21 40 Vi Pol Pi2 Vi Pf2 Q2 D2 半導體裝置 電子裝置 輸入電壓 輸出用銲墊 輸入端子 輪入電壓 復位專用銷 第2電晶體 第2二極體 316179 14 1336519 D3 第3二極體 D4 第4二極體 0P1 運算放大器 Verf 輸入基準電壓 R1 第1分壓電阻 R2 第2分壓電阻 Vfb 復位電壓 Vfb’ 比較對象電壓 Wil 輸入引線 Wol 輸出引線 Wfl 復位引線 Lo 輸出用配線 Lf 復位用配線 N 點 BAT 電池 15 316179

Claims (1)

1336519
第931?47幻:;號專利申請案 (96年3月彳6 0) 十、.申請專利範圍 1. 一種半導體裝置，具備：具有第1銲墊以及第2銲墊之 1C晶片，以及 連接於前述第1銲墊以及第2銲墊兩方之端子， 而利用二極體將連接於前述第1銲墊之第1訊號與 連接於前述第2鲜塾之第2訊號予以搞合。 2. 如申請專利範圍第1項之半導體裝置’其中，前述端子 為輸入端子， 該半導體裝置更具有：在將電源電壓施加於前述輸 入端子時，由該電源電壓產生標的電壓之控制電路；以 及輸出所產生之標的電壓之輸出端子， 而前述控制電路係形成以前述第1訊號以及第2 訊號的兩個系統接收前述電源電壓而產生前述標的電 壓的構成。 3. 如申請專利範圍第1項之半導體裝置，其中，前述端子 為輸出端子；該半導體裝置尚具有：施加有預定的電源 電壓之輸入端子；以及由該電源電壓產生標的電壓之控 制電路* 而使前述標的電壓傳輸至前述第1訊號或第2訊號 之任一個。 4. 一種半導體裝置，係包含：施加有電源電壓之輸入端子； 由前述電源電壓產生標的電壓之控制電路；以及輸 出所產生之標的電壓之輸出端子， 而在前述輸入端子或輸出端子的至少其中一方，配 16 316179(修正版） 1336519 ， 第93]2478]號專利申請案 • (96年3月16曰） 置複數個1C晶片側的銲墊，以將訊號傳輸路徑予以多 重化的同時，利用二極體將經多重化之訊號傳輸路徑予 以柄合。 5. —種電子裝置，安裝有半導體裝置與負載裝置， 前述半導體裝置係包含：施加有電源電麼之輸入端 子；由前述電源電壓產生標的電壓之控制電路；以及輸 出所產生之標的電壓之輸出端子， 而在前述輸入端子或輸出端子的至少其中一方，配 ^ 置複數個1C晶片側的銲墊以將訊號傳輸路徑予以多重 化的同時，利用二極體在前述半導體裝置内部或半導體 裝置與前述負載裝置之間的位置，將經多重化之訊號傳 輸路徑間予以耦合。 17 316179(修正版）
TW093124781A 2003-09-12 2004-08-18 Semiconductor device and electronic apparatus capable of detecting open wire using weak current TWI336519B (en)

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