TWI335654B - Package for reducing stress - Google Patents

Package for reducing stress Download PDF

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Publication number
TWI335654B
TWI335654B TW096116028A TW96116028A TWI335654B TW I335654 B TWI335654 B TW I335654B TW 096116028 A TW096116028 A TW 096116028A TW 96116028 A TW96116028 A TW 96116028A TW I335654 B TWI335654 B TW I335654B
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Taiwan
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package
sealant
stress
transition temperature
interposer
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TW096116028A
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TW200845344A (en
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Wei Chung Wang
Meng Jen Wang
Tong-Hong Wang
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Advanced Semiconductor Eng
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Priority to TW096116028A priority Critical patent/TWI335654B/zh
Priority to US12/112,255 priority patent/US20080272486A1/en
Publication of TW200845344A publication Critical patent/TW200845344A/zh
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Publication of TWI335654B publication Critical patent/TWI335654B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10378—Interposers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Description

1335654 九、發明說明： 【發明所屬之技術領域】、 本發明係有關於一種封裝構造，特別係有關於一種可 降低封裝應力之封裝構造。 【先前技術】 «知封裝構造主要包含一承載器 板以及-密封膠，以該晶片與該中介基板係可藉由該曰曰
片之複數個凸塊形成電性連接，而該中介基板與該承載器 之電性則需另由複數個導電元件來形成電性連接，且為了 保護該晶片之該些凸塊與該些導電元件，必須以該密封膠 將該些凸塊與該些導電元件包覆1而在封裝製程之過程 中，由於該承《、該^與該中介基板三者之熱膨服係 數不同，但卻使用相同之密封勝，使得該承載器、該晶片 與該中介基板因受熱產生形變而造成内應力，故習知封裝 構造會因為應力仙而導致電㈣接失敗，增加產品不^ 率。 【發明内容】 本發明之主要目的係在於裎/ 耵你隹於扣供一種可降低封裝應力 之封裝構造，-承載器、-中介基板、複數個第—導電元 件、一第-密封勝、一晶片以及一第二密封膠。該承載器 之一上表面係設置有複數個連接墊，該承 係設置有複數個球塾，該中介基板係設置於該承載器之該 上表面，財介基板係具有一第—表面、—第二表面及複 數個導通孔，該些導通孔係電性導通該第—表面之複數個 6 1335654 第—接點與該第二表面之複數個第二接點，該些第一導電 元件係設置於該承載器與該中介基板之間並電性連接該 中介基板與該承載器，該第一密封膠係包覆該些第一導電 兀件，該第一密封膠係具有一第一玻璃轉化溫度，該晶片 係覆晶接合於該中介基板，該晶片之複數個凸塊係接合至 S亥中介基板之該些第一接點，該第二密封膠係包覆該些凸 塊’该第二密封膠係具有一第二玻璃轉化溫度，其中該第 一密封膠之該第一玻璃轉化溫度係大於該第二密封膠之 該第二玻璃轉化溫度。本發明之功效係在於包覆該些第一 導電元件之該第一密封膠與包覆該些凸塊之該第二密封 膠一者間之玻璃轉化溫度不同，且該第一密封膠之該第一 玻璃轉化溫度係大於該第二密封膠之該第二玻璃轉化溫 度’此種封裝構造可降低封裝構造内之應力作用，使得產 品良率提高。 依本發明之一種可降低封裝應力之封裝構造主要包 含一承載器、一中介基板、複數個第一導電元件、一第一 密封膠、一晶片以及一第二密封膠。該承載器係具有一上 表面與一下表面，該上表面係設置有複數個連接墊，該下 表面係設置有複數個球墊，該中介基板係設置於該承載器 之該上表面，該中介基板係具有一第一表面、一第二表面 及複數個導通孔，該第一表面係設置有複數個第一接點， 該第二表面係設置有複數個第二接點，該些導通孔係電性 導通該些第一接點與該些第二接點，該些第一導電元件係 設置於該承載器與該中介基板之間並電性連接該中介基 7 1335654 板與該承載器，該第一密封膠係包覆該些第一導電元件， 該第一密封膠係具有一第二玻璃轉化溫度，該晶片係覆晶 接合於該中介基板’該晶片係具有複數個凸塊，該些凸塊 係接合至該中介基板之該些第一接點，該第二密封膠係包 覆該些凸塊’該第二密封膠係具有一第二玻璃轉化溫度， 其中該第一密封膠之該第一玻璃轉化溫度係大於該第二 密封膠之該第二玻璃轉化溫度。 【實施方式】 請參閱第1圖，依據本發明之一具體實施例係揭示一 種可降低封裝應力之封裝構造1 〇〇，其係包含有一承載器 110、一中介基板120、複數個第一導電元件130、一第一 密封膠140、一晶片15〇以及一第二密封膠160。該承載 器110係具有一上表面111與一下表面112,該承載器11〇 係可選自於有機基板或導線架，在本實施例中，該承載器 11 〇係為有機基板，該上表面u丨係設置有複數個連接墊 11 3 ’該下表面1 i 2係設置有複數個球墊丨丨4，該中介基板 120係設置於該承載器11〇之該上表面m，該中介基板 120之材質係為矽，該中介基板12〇係具有一第一表面 121、一第二表面丨22及複數個導通孔in，該第一表面 12 1係設置有複數個第一接點丨24，該第二表面122係設 置有複數個第二接點125，該些導通孔123係電性導通該 些第一接點124與該些.第二接點125，較佳地，該中介基 板1 20係另具有至少一積體化被動元件（integrated Passive Device，IPD)126，該積體化被動元件126係嵌設於該中介 8 1335654 基板120之該第一表面121。該些第一導電元件13〇係設 置於5亥承載15 110與該中介基板12〇之間並電性連接該中 介基板120與該承載器11〇 ’該些第—導電元件13〇係可 為凸塊且電性連接該中介基板12〇之該些第二接點125與 省承載态110之該些連接墊113，該第一密封膠14〇係包 覆《玄坠第一導電元件〖30，該第一密封膠14〇係具有一第 玻璃轉化溫度（first glass transiti〇n temperature，)， 泫第一密封膠140之該第一玻璃轉化溫度係介於12〇至 160之間，較佳地，該第一密封膠14〇之該第一玻璃轉化 溫度係為140度。該晶片15〇係覆晶接合於該中介基板 120，在本實施例中，該晶片15〇係為一功能性晶片，該 晶片150之一主動面15ι係具有複數個凸塊152，該些凸 塊152係接合至該中介基板12〇之該些第一接點124使該 晶片150與該中介基板ι2〇形成電性連接，且藉由該中介 基板120電性連接於該承載器i 1〇，在本實施例中，該中 介基板12 0之尺寸係大於該晶片丨5 〇之尺寸，或者，如第 2圖所示’該晶片150之尺寸係可等於該中介基板ι2〇之 尺寸。請再參閱第1圖，該第二密封膠16〇係包覆該些凸 塊1 52，s玄第二密封膠.1 60係具有一第二玻璃轉化溫度 (second glass transition temperature，Tg2)，其中該第一密 封膠140之該第一玻璃轉化溫度係大於該第二密封膠ι6〇 之該第一玻璃轉化溫度’該第二密封膠之該第二玻璃 轉化溫度係小於100度且該第二密封膠16〇之該第二玻璃 轉化溫度係介於50至90之間，較佳地，該第二密封膠1 6〇 9 1335654 之忒第二玻璃轉化溫度係為7〇度，此外，該封裝構造loo 係另包含有複數個第二導電元件17〇’該些第二導電元件 17〇係可為銲球且設置於該承載胃110之該些球塾…， 以外接一印刷電路基板（圖未繪出）。由於包覆該些第一 導電7°件no之該第—密封膠mo與包覆該些凸塊152之 該第一密封膠！ 60二者間之玻璃轉化溫度並不相同，故本 發明之功效係在於藉由該第一密封膠14〇之該第一玻璃轉
化溫度大於該第二密封膠16〇之該第二玻璃轉化溫度，使 得該封裝構造⑽内之應力降低，進而提高產品良率。 、本發明之保護範圍當視後附之申請專利範圍所界定 :為準’任何熟知此項技藝者，在不脫離本發明之精神和 範圍内所作之任何變化與修改，均屬於本發明之保護範 圍。 【圖式簡單說明】- 第1圖：依據本發明之一第一具體實施例’ 一種可降低封 裝應力之封裝構造之截面示意圖。 第2圖：依據本發明之一第三具體實施例，另一種可降低 封裝應力之封裝構造之截面示意圖。 【主要元件符號說明】 100封裝構造 110承載器 113連接墊 1 2 1苐一表面 124第一接點 111上表面 114球墊 1 22第二表面 125第二接點 11 2下表面 120中介基板 123導通孔 10 1335654 126積體化被動元件 · 130·第一導電元件 140第一密封膠 150晶片 151主動面 152凸塊 160第二密封膠 170第二導電元件
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Claims (1)

1335654 十、申請專利範圍： 1 一種可降低封裝應力之封裝構造，其係包含： —承载器’其係具有一上表面與一下表面，該上表面 係設置有叔數個連接墊，續 • ^ β下表面係设置有複數個球 墊； 中介基板，其係設置於該承載器之該上表面，該中 介基板係具有一第一表面、—第二表面及複數個導通 • 孔，該第一表面係設置有複數個第一接點，該第二表 • 面係。又置有複數個第二接點，該些導通孔係電性導通 該些第一接點與該些第二接點； 複數個第一導電元件，其係設置於該承載器與該中介 基板之間並電性連接該中介基板與該承載器； 一第一密封膠，其係包覆該些第一導電元件，該第— 密封膠係具有一第一玻璃轉化溫度； 一晶片，其係覆晶接合於該中介基板，該晶片係具有 • 複數個凸塊，該些凸塊係接合至該中介基板之該些第 一接點；以及 一第二密封膠，其係包覆該些凸塊，該第二密封膠係 具有一第二玻璃轉化溫度’其中該第一密封膠之該第 一破璃轉化溫度係大於該第二密封膠之該第二坡壤 轉化溫度。 2、如申請專利範圍第1項所述之可降低封裝應力之封敦 構造’其中該第二密封膠·之該第二玻璃轉化溫度係小 於100度。 12 如申請專利範圍第i項所.述之可降低封裝應力之封裝 構造，其中該第二密封膠之該第二玻璃轉化溫度係介 於50至90之間。 降低封裝應力之封裝 二玻璃轉化溫度係為 、如申請專利範圍第3項所述之可 構造，其中該第二密封膠之該第 70度。 、如申請專利範圍第 構造’其中該第一 於120至160之間 、如申請專利範圍第 構造’其中該第一 140 度。 1項所述之可降低封裝應力之封裝 检封膠之該第一玻璃轉化溫度係介 5項所述之可降低封裝應力之封裝 密封膠之該第-玻璃轉化溫度係為 構&其中5亥晶片係為—功能性晶片。 ::1凊=範圍第1項所述之可降低封裝應力之南 士： 亥晶片之尺寸係等於該中介基板之尺4 請專利範圍第1項所述之可降低封裝應力之2 構^其中該中介基板之尺寸係大於該晶片… 明專利範圍第1項所述之可降低封裝應力之封 構坆’其中該中介基板之材質係為矽。 =請專利制第1項所述之可降低封裝應力之封 構-，其另包含有複數個第二導電元件，二 電元件係設置於該承载器之該些球墊。-- 如申請㈣範㈣1項所述之可降低封裝應力之封 1335654 13 構造，其中該承載器 戰1益係選‘自於有機基板或 如申請專利範圍第1 〜 項所迷之可降低封裝應力之封裝 構造’其中該中介基板係另具有至少 件（Integrated Passive Device，IPD)。 導線架 積體化被動元
14
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