TWI332244B - Fabrication method of leadframe and semiconductor package - Google Patents

Fabrication method of leadframe and semiconductor package Download PDF

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Publication number
TWI332244B
TWI332244B TW096102973A TW96102973A TWI332244B TW I332244 B TWI332244 B TW I332244B TW 096102973 A TW096102973 A TW 096102973A TW 96102973 A TW96102973 A TW 96102973A TW I332244 B TWI332244 B TW I332244B
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TW
Taiwan
Prior art keywords
layer
semiconductor package
carrier
fabricating
wafer
Prior art date
Application number
TW096102973A
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English (en)
Other versions
TW200832573A (en
Inventor
Chi Chih Lin
Bo Sun
Hung Jen Wang
Jen Feng Tseng
Original Assignee
Taiwan Solutions Systems Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Solutions Systems Corp filed Critical Taiwan Solutions Systems Corp
Priority to TW096102973A priority Critical patent/TWI332244B/zh
Priority to US11/907,137 priority patent/US20080182360A1/en
Publication of TW200832573A publication Critical patent/TW200832573A/zh
Application granted granted Critical
Publication of TWI332244B publication Critical patent/TWI332244B/zh

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    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

1332244 本發明之另一實施例提供一種半導體封骏 法，包含：提供一載板，具有相對之第一表面詉第二、作方 少表面處理第-表面；於第一表面形成複數個凹槽=面；至 -疊加金屬層於凹槽，每一疊加金屬層至少包含；，置 -接合面相對設置；進行一晶片安裝步驟；形成 ：與 載板，移除載板，使疊加金屬層突出於封膠體丨另二〜於 單，以形成數個半導體封裝元件。 行切
本發明之另一實施例提供一種導線架的製 提供一載板，具有一第一表面及一第二表面;至n -表面；分別覆蓋-圖案化絕緣層與—絕緣層於第—面處= 第二表面上，圖案化絕緣層具有複數個開口以暴露乂 第-表面；設置-疊加金屬層於暴露出之第—表面」 加金屬層至少包含-焊接面與—接合面相對設置；以及二 圖案化絕緣層與絕緣層。 夕
本發明之另一實施例提供一種導線架的製作方法 提供-載板，具有-第_表面；至少表面處理第—表面；於第 -表面形成複數個凹槽；以及分別設置—疊加金屬層於凹 槽，每-疊加金屬層至少包含—焊接面與一接合面相對設置。 以下藉由具體實施_合所_圖式詳加制，當更容易瞭 本發明之目的、技術内容、獅及其所達成之功效。 Μ 【實施方式】 第la圖至第h _本發明-實施例铸體封裝元件的製作方 法之流程剖面示意圖，錢，如第la圖所示，提供—載板1〇 者為金屬材質者，載板1G具有相對之第—表面12與第二表面Μ ;在 第-表面12進行特殊之表面處理，形成—凹凸結構或—網狀結構， 7 1332244
如第ib圖之局部放大圖所示，以增加第一表面12的表面積；抹 第lc圖，分卿成-圖案化絕緣層16與_絕緣層18於載板^ -表面η與第二表面14’圖案化絕緣層16上依照後續晶 置與電路設計形成有複數個開口 20，以暴露出部分之第—表面 接著，於每-開口 20處分別設置-疊加金屬層22，如第Id圖所示’， 且每-疊加金屬層22包含位於最下層之谭接面221 接合嫌，其中焊接面221係採用可供谭接之材質，如金H之 錦、銅或錫’而接合面222係採用可供打線或上銲球之材質，如金 銀、錫、銅或把；之後移除圖案化絕緣層16與絕緣層18，以 第le圖所示之導線架結構24，即導線架結構24由載板i〇 j^置於 其第-表面12的複數疊加金屬層22所構成；接著，進行—s日、裝 步驟’如第If義示’以打線方式電性連接複數晶片％ ^ 層22之接合面222，之後如第lg圖所示，於載板1〇上形成:封= 8以覆盍晶片26及複數疊加金屬層22 ;最後如第lh圖所示 板H)移除，且以每-晶片26為單位進行切單，以 示之單顆半導體封裝元件3〇。 乐ία所
其中，圖案化絕緣層16係、利用影像轉移製程、印刷製程或雷射 直接成像技術(laserdireetimaging ’ LDI)形成於第—表面12上。於另 :實施例中，上述晶片安裝步驟亦可以覆晶方式電性連接晶片26與 加金屬層22 ’進而完成如第2圖所示之單顆半導體封裝元件％。 牛Μ於又—實關巾，在魏架結構24製作絲後，上述晶片安舉 二St第％至第对圖所示’包括以塗佈、壓合或模壓方編 笨、$隔層32於載板1G上，如第3a圖所示，覆蓋疊加金屬層22 3，以雷射鑽孔、盲鐵、電践光阻顯影方式顧 =隔層32上形成複數個通孔34,以露出部分疊加金屬層22的部矣 ^面此之後，如第3e _示，械—導電㈣覆蓋絕緣瞧 廢面通孔34内壁及露出的接合面222,於本實施例中，導, 係為鑛鋼層；接著請參閱第3d圖及第3e圖，依照需求於導售
S 丄JOZZ44 層36上製作一圖案化線路38，且於導線層％上設置數個導電塾仙， 以供利用打線方式紐連接晶片26與導電塾仙，如第卵所示；之 /再進行封膠、移除載板及切單等製程，進而^成如第4圖所示之單 顆半導體封裝元件3G。於另—實施例中，請參㈣5圖亦可以覆晶 方式取代上述打線；^式電性連接晶片26與導電塾4()，進喊成 5圖所示之單顆半導體封裝元件3〇。 雷經H發曰月中’疊加金屬層係利用電鑛法、賤鍍法、蒸鍍法或無 積於載板上’ ^，疊加金麟的接著面顧填入載板 板之原預結網狀結構的縫隙中，抑或以原子型態填入載 性接菩λ’且加金屬層與餘間可藉由電鍍所產生的物理 質起，除了不需藉由任何黏著介質來接著兩種不同材 之外，由於兩個原子間的空_當小，可阻止 進金麟之原子·他原子渗人，而職—阻絕效應； 面，防止^續製程㈣膠體之高分子分子滲人兩者之接著 習知貼膠帶于去:::分子巧染疊加金屬層之焊接面，本發明可省略 ^貼料、去料與轉程，具 設計，將可降咖價格、提昇良_===㈣ 質俜、S自:二t層之焊接面與接合面間更包含一中間層，其材 言可為如下之疊合結_中之—’麟4加销層整體而 金纪錄金、繊金、錢錄銀、· ^餘金、雜金、 金飽錄錫、金鎳銅鎳金、錄二鎳錫' 銀錦錫、金録錫、 錄金、銀義聽金、纖綠 '金麟銅 錄鋼錄銀、減鎳銅錄銀、把銀鋅::銅:金、金鎳銅鎳銀 '銀 辣剩錄銀銳、金鎳銅鎳銀鈀、鈀銀鎳 9 1332244 銅鎳金、鈀銀鎳鋼鎳錫、銀錄銅 鈀銀鎳銅錫、銀鎳鋼錫合金鎳鋼鎳錫、金鈀鎳銅鎳錫、 .、銅錫金鎳銅锡、金鈀鎳鋼錫與銀。 各種不疊加金顧的厚度可賴需求製作，而形成 在現有封裝謂的條件下進行難元件的生轉度，以便 支出以提昇競爭力之優點/ 的生產，故具有降低額外設備 加令施财，導線架結構係域板及設置於載板表面之疊 ^屬層所構成；於另一實施例t，導線架結構亦可為另一型態苴 製作流程請參閱第6a圖至第6e圖，魏，如第6a _示提供一 載板1〇 ’常用者為金屬材質者，載板1()具有相對之第一表面u與第 一表面14 ;接著如第6b圖所示’利祕刻、深度控制、電姓或沖壓 方式於第—表面12形成複數個_且進行表面處理，接著於每一凹 2 42中利用電鍵法、、減鍍法、蒸鍍法或無電解電錄法設置-疊加金 屬層22，以完成如第6c ®所示之導線架結構24，即疊加金屬層22 的接合面扭與載板10的第一表面12為等高平面或不等高，屬其層中疊 加金屬層22的結構與材質已說明於之前的實施例巾，在此不再贅述。 在此導線架結構24上亦可輔賴上職續之晶>!安裝步驟 '形成 封膠體、移輯板及切單魏程，進而完成如第7騎示之單顆半導 體封裝S件3G ’其巾’晶# 26係以打線方式與4加金屬層22電性連 接’但不限於此’晶片安裝步驟亦可以覆晶方式電性連接晶片26與 疊加金屬層22 ’以完成如第8圖所示之單顆半導體封裝元件3〇 ;抑 或利用前述第3a至第3f圖所述之晶片安裝步驟，以完成如第9圖所 示之單顆半導體封裝元件30。 < s 10 接續上述說明，由於疊加金屬層係設置於載板之凹槽中，使得 封膠體不致流人疊加金屬層之間，顺雜與疊加金屬層底部之焊接 面之間具有-高度差，因此當載祕除錢行切單後，請再次參閱第 Γ焊接面221與賴28之_高度差⑻將有助 壯 製程時，增加焊錫之信賴性；因此本發明之半導體封 前述之省略習知貼膠帶、去膠帶與除膠等製程以減 =成本★昇良率 '符合R0HS之絲要求鱗健體封裝 、间又的功效之外，亦兼具有提高產品信賴度之優點。 、 點，其广:二之f施例僅係為說明本發明之技術思想及特 並據之人士能夠瞭解本發明之内容 本發明所揭示之精神所作之應即大凡依 發明之專利範圍内。 ）等變化次修飾’仍應涵蓋在本 【圖式簡單說明】 意r本發明—實施例半導軸_製作方法之 圓第。2圏為依據本發財—私例㈣叙半細縣元件結構示意 第知圖至第外圖為本發 意圏。 另#施例晶片安裝步驟之流程剖面示 第4圖為依據本發明又—實施例 圖。 纟之+導體塊树結構示意 ^圖為域本卿又 圖。 +導體封裝元件結構示意 苐6a圓至第6c圖為本發明另— 圖。 ，魏帛之雜流㈣面示意 70件結構示意 第7圓為依據本發明又—實施例所製作之半導體封裝 γ圖為崎本發明又—實關所製作之半導體封裝元件結構示意 第9圖為依據本發明又一實施例所製作之半導體封裝元件結構示竟 【主要元件符號說明】 10 載板 12 第一表面 14 第二表面 16 圖案化絕緣層 18 絕緣層 20 開口 22 疊加金屬層 221焊接面 222接合面 24 導線架結構 26 晶片 28 封膠體 30 半導體封裝元件 32 絕緣間隔層 34 通孔 36 導電層 38 圖案化線路 40 導電墊 42 凹槽 12

Claims (1)

1332244 十、申請專利範圍： fi年5 月《曰修(更)正本 99年5月28日修正替換頁 1.種半導體封裝元件的製作方法，包含： 提供一載板，具有相對之一第—表面與一第二表面； 至少表面處理該第一表面； 刀別覆蓋一圖案化絕緣層與一絕緣層於該第一表面與該 第二表面，該圖案化絕緣層具有複數個開口，以暴露出部分 該第一表面；
設置—疊加金屬層於暴露出之該第一表面，每一該疊加 金屬層至少包含一焊接面與一接合面相對設置； 移除該圖案化絕緣層與該絕緣層； 進行一晶片安裝步驟； 形成一封膠體於該載板； 移除該載板；以及 進行切單，以形成數個半導體封裝元件。 &月求項1所述之半導體封裝元件的製作方法，其中，該第一表面 經該表面處理步驟而形成一凹凸結構或—網狀結構。
=求们所述之半導體封裝元件的製作方法，其中，該覆蓋步驟 糸為/像轉移齡、印刷製程或f射直接錢技術。 4 項1所述之半導體封裝元件的製作方法，其巾，該疊加金屬 一」用麵法、雌法、蒸鍵法及無電解麵法其中之—設置於該 弟 面。 二求項1所述之半導體封裝元件的製作方法 材質係選自金、銀、錫、銅及銳其中之—。 义曰贫、跟、物、荆及紀其中之一。 °月求項1所述之半導體封裴元件的製作 材質主係選自金、銀、&、錦、銅及錫其中之一。，其中’該焊接面的 7. 如凊求項丨所述之半導體封裝元件的製作 層更包含—中間層於該焊接面及該接合面之門/、趟加金屬 8. 如請求項7所述之半祕封裝元件的製財法，其中，該中間層的 13 1332244 月28日修正替換頁 材貝係選自鎳、把、銀及銅其中之一或其組合。 9. 如請求項1所述之半導體封裝元件的製作方法，复 步驟包含： ’孩晶片安裝 設置至少一晶片於該接合面；以及 電性連接該晶片與該接合面。 10. 如請求項9所述之半導體封裝元件的製作方法，复 式電性連接該晶片與該接合面。 〃係、以打線方 η.如請求項9所述之半導體封裝元件的製作方法， 式電性連接該晶片與該接合面。 /、係以覆a曰方 請求項丨所述之半導體龍猶的製作方法， 步驟包含： ’、T 孩日日片女裝 形成一絕緣間隔層於該栽板上，以覆蓋兮聂 於該絕緣間隔層上形成複數個通°暴二屬層; 金屬層之該接合面的部分表面； 暴路》卩刀該疊加 形成-導電層於該絕緣間隔層表面、 接合面的該部分表面； Α 皇''或 =該導電層形成一圖案化線路；以及 設置至少一晶片於該導逮·盛 電層。 s 電性連接該晶片與該導 求項12所述之半導體封裝元件的製作方法， 方式電性連接該晶片與該導電層。 中，係以打線 14. 如請求項12所述之半導體^元件的 方式電性連接該晶#與該導電層。 ’其巾’係以覆晶 15. 如請求項12所述之半導體封楚元件 隔層係利用塗佈、壓合或模壓方式形成。下方法，其中，該絕緣間 I6·如請求項！2所述之半導體簡元)件的製 17 鑽孔、盲鑽、電__影方式形成其中，該通孔係 Π.如明切12所狀半導體 = 1干⑽作方法，其中，該導電層 14
99年5月28叫正替換頁 1332244 -· > 係為一鍍銅層* 18.—種導線架的製作方法，包括： 提供一載板，具有一第一表面及一第二表面； 至少表面處理該第一表面； 分別覆蓋一圖案化絕緣層與一絕緣層於該第一表面與該 第二表面上，該圖案化絕緣層具有複數個開口，以暴露出部 分該第一表面；
設置一疊加金屬層於暴露出之該第一表面’每一該疊加 金屬層至少包含一焊接面與—接合面相對設置；以及 移除該圖案化絕緣層。 I9·如請求項1S所述之導線架的製作方法，其中，該第一表面經該表 面處理步驟而形成一凹凸結構或—網狀結構。 2〇.如請求項18所述之導線架的製作方法，其中，該覆蓋步驟係為影 像轉移製程、印刷製程或雷㈣接成像技術。 ’ 21.^ί、Π8所述之輸^製作綠，其中，該疊加金屬層係利 =電鍍法、麵法、蒸鍍法及無電解電舰其中之—設置於該第一表 22g==!線架的製作方法，其中，該接合面的材質係 選自金、銀、Γ及賴作妓，其巾，該焊接面的材質係 24t請求項18所述之導線架的製作方法，^ 含一中間層於該焊接面及該接合去其中，該疊加金屬層更包 纪、銀及銅其中之_或其組人 間’該中間層的材質係選自銻、 t Si 15 1332244
β年5月沒日修(更)正替換頁丨99年…8日修正替換頁 七、指定代表圖： 二 (一） 、本案代表圖為：第le圖 (二） 、本案代表圖之元件代表符號簡單說明： 10 載板 12 第一表面 22 疊加金屬層 24 導線架結構 八、本案若有化學式時，請揭示最能顯示發明特徵的化學式：
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