TWI324829B - Optical semiconductor package and method for manufacturing the same - Google Patents
Optical semiconductor package and method for manufacturing the same Download PDFInfo
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- TWI324829B TWI324829B TW093102847A TW93102847A TWI324829B TW I324829 B TWI324829 B TW I324829B TW 093102847 A TW093102847 A TW 093102847A TW 93102847 A TW93102847 A TW 93102847A TW I324829 B TWI324829 B TW I324829B
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- 230000003287 optical effect Effects 0.000 title claims abstract description 61
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 238000000034 method Methods 0.000 title claims description 8
- 239000004065 semiconductor Substances 0.000 title 1
- 239000000758 substrate Substances 0.000 claims abstract description 69
- 239000000565 sealant Substances 0.000 claims abstract description 24
- 239000008393 encapsulating agent Substances 0.000 claims abstract 5
- 235000012431 wafers Nutrition 0.000 claims description 67
- 238000005520 cutting process Methods 0.000 claims description 14
- 238000007789 sealing Methods 0.000 claims description 6
- 239000003292 glue Substances 0.000 claims description 4
- 125000006850 spacer group Chemical group 0.000 claims description 3
- 238000003776 cleavage reaction Methods 0.000 claims 1
- 230000007017 scission Effects 0.000 claims 1
- 239000000919 ceramic Substances 0.000 description 6
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000012790 adhesive layer Substances 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- 239000004033 plastic Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 229910052797 bismuth Inorganic materials 0.000 description 2
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 239000002985 plastic film Substances 0.000 description 1
- 229920006255 plastic film Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14618—Containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Light Receiving Elements (AREA)
Description
1324829 六、發明說明: 【發明所屬之技術領域】 本發明係關於一種光學積體電路元件之封裝 構造’尤其係關於一種具有外蓋及透明封勝塑料 之光學積體電路元件之封裝構造。 【先前技術】 在一般的光-電應用中’為了保護採積體電路晶 片形式的光-電元件,諸如影像感應晶片(image · sensor chip),使其不受物理性傷害以及不受環境雜 質污染,一般實務係將該影像感應晶片置放於一封 裝槔造中,並且該封裝構造具有透明蓋密封之開 口,使得影像感應晶片得以感應光學訊號。 舉例而言,該影像感應晶片一般係利用一膠層 女裝在一具有突出接腳(pin)的共燒陶瓷基板上。該 膠層一般需經由固化(curing)製程使其得以將影像镄 感應兀件固定於陶瓷基板。在打線以及窗密封 (window sealing)後,該接腳係被切成適當長度並且 成型而完成整個封裝製程。 於該窗密封之加工過程中,典型上係利用配送 或模造的加工步驟,將一封膠塑料(m〇lding compound)環繞該影像感應元件安裝於該基板上。之 紅,再將一透明外蓋加裴於該封膠塑料之外側,藉 以將該影像感應it件密封於該基板及該外蓋中。舉 3 例而言,1998年9月22日頒予Wu之美國專利第 5,811,799號,發明名稱為,,具有密封外蓋之壁的影 像感應器(Image Sensor Package Having A Wall With A Sealed Cover)’’,其揭示一種影像感應器之封裝構 造,藉由一預鑄之壁(pre-m〇lded wall)將一影像感應 晶片封裝於一陶瓷基板上。前述之光學元件封裝構 壤係易於撓曲(warpage)的,且其必須使用昂貴的陶 瓷*基板,而係昂貴。 因此,對於光學元件之封裝業者,便有需要提 供一種光學件之封裝構造,能夠以較低的成本製 造。 、 【發明内容】 本發明之目的係提供一種光學積體電路元件之 封裝構造,能夠以較低的成本製造。 為達上述目的,本發明提供一種光學元件封裝 構造包括—晶片、—密封谬、-外蓋、-基板、複 數條連接線、一透明封膠體。該晶片具有光學元件 及複數個晶片銲塾。該密封膠係配置環繞該光學元 件。該外蓋係配置於該密封膠上。該基板支掠該晶 片j且具有複數個銲墊。該複數條連接線係用以將 該晶片之該晶片銲墊電性連接至該基板之該銲墊。 該透明㈣體係形成於該基板及該外蓋上,並包封 該連接線。 1324829 根據本發明之光學元件封裝構造具有一外蓋覆 蓋於晶片的光學元件上,而有助於防止水氣以及降 低撓曲(wa卬age)。該光學元件封裝構造係可利用一 般的基板,而非需昂貴的陶瓷或Βτ樹脂 (biSma-leimidetriazineresin)基板始能達成,故其製 造成本因而大幅減少。 、為了讓本發明之上述和其他目的、特徵、和優 點能更明㈣徵’下文特舉本發明較佳實施例,並 配合所附圖示’作詳細說明如下。 【實施方式】 現請參考第1圖,其顯示根據本發明之一實施 例之-料元件封裝構造丨⑼。該封裝構造ι〇〇包 括一晶片110,其具有一主動表面112以及一相對之 背面114,該晶片110之該主動表面112具有一主動 區域(active Z0ne)116,其具有複數個光學元件諸 如光學感應器,用於光學及電氣訊號間之轉換。丨 一密封膠122係環繞該光學元件配置於該晶片 110之該主動表面112上。一外蓋12〇係配置於該密 封膠122上,並藉由該密封膠122黏著並固定於該 晶片110上。該密封膠122係與間隙子,圖中未示, 相混合,藉此使得該外蓋12〇與該晶片u〇間保 -定的間隙。再者,料蓋m係可為單純的透明 外蓋。或者’該外i 12G可用以提供光學特性,諸 5 1324829 如濾光(filter)以及聚焦,亦即該該外蓋12〇可為一 遽光片或一透鏡。 該晶片110係藉由一黏著層142 -基板飢。於該晶片110之該主動表面二 另具有複數個銲墊118 ’藉由複數條連接線14〇電 性連接至該基板150之上表面上之複數個銲墊156 土。該基板150另具有複數條線路丨52,用以將該 銲墊156電性連接至該基板15〇下表面上之複數個 接墊154。一封膠體130係包封該晶片n〇、該外蓋 120、該連接線140、以及該基板15〇之上表面。該 揍塾154可藉由表面黏著技術,電性連接並固定於 外。卩之印刷電路板上(圖未纟會示),亦即該光學元 件封裝構造100係為一平坦格狀陣列(iand grid array) 封裝構造。精於本技藝者將可瞭解,該接墊154可 輕易的替'換為錫球或針狀接腳,而形成球格陣列 (ball grid array)或針格陣列(pin grid array)封裝構 造。 參考第3-9圖,其顯示根據本發明之一實施例 之一方法’用以製造該光學元件封裝構造1〇〇。參 考第3圖’根據本發明之製造方法,首先提供一晶 圓160’具有複數個晶片110’以及複數條切割線 162 ’用以界定該晶片u〇。每個晶片11〇具有―主 動區域116以及複數個銲墊118,環繞該主動區域 6 6配置之後,密封膠122係可藉由一配送器, 圖中t示’個別的配送於該晶月110上,並環繞該 主動區域116’且該銲$ 118係、位於該密封膠⑵ 之外側,詳如第4圖所示。 參考第5圖,一外蓋基板17〇係配置於該晶圓 160上。該外蓋基板17〇具有複數個外蓋,以及 複數2切割線172用以界定該外蓋12〇。如前所述, 該外蓋基板170可為一透明基板、一濾光片、或具# 有複數個透鏡。該密封# 122可為 更化膠且與間隙子(圖中未示)相混合。當該外蓋 基板170與該晶圓16〇相對齊並配置於該晶圓 ^時該密封膠122可藉由紫外光硬化,如此使得 該外蓋120以均勻的間隙固定於該晶片110上,而 在該主動區域116上形成一具有均勻間隙的空腔。 再參4第6圖,刀具18〇以及182係分別沿著 泫晶圓160及該外蓋基板17〇之切割線162及丨72,、 切割該晶圓160及該外蓋基板17〇,藉此單體化分 離》玄aa圓1 60及5亥外盍基板} 以形成複數個封裝 構造190。較佳地,其係先於該晶圓16〇及該外蓋 基板170形成複數個凹槽184、186。之後再於後 續製程中,藉由一破裂製程,沿著該晶圓160及該 外蓋基板1 70之該凹槽} 84、丨86裂開,而形成一封 裝構造190 ’顯示於第7圖中。 參考第8圖,根據本發明之製造方法係提供一 基板條192其具有具有複數個基板15〇,以陣列方 式排列。該封裝構造190係可藉由複數個黏著層! 42 個別的黏著於該基板條192之該基板15〇上。複數 個連接線140係用以將該晶片11〇之該銲墊118電 性連接至該基板150之該銲塾156。 、參考第9圖,一封膠體13 0係由透明封膠塑料 模造於該基板條192上,用以包封該封裝構造19〇、 該連接線140、及該基板15〇之上表面。之後,該 基板條192係被切割,而形成該光學元件封裝構造 100。 如前所述,根據本發明之光學元件封裝構造係 為一平坦格狀陣列(land grid array)封裝構造。精於 本技藝者將可瞭解,該接墊154可輕易的替換為錫 球或針狀盔腳,而形成球格陣列(ball gdd array)或針 格陣列(pin grid array)封裝構造。 根據本發明之光學元件封裝構造具有一外蓋覆 蓋於晶片的光學元件上,而有助於防止水氣以及降 低撓曲(warpage)。該光學元件封裝構造係可利用一 般的基板,而非需昂貴的陶瓷或Βτ樹脂 (biSma-leimidetriazineresin)基板始能達成’故其製 造成本因而大幅減少。再者’由於該封裝構造不具 有外部接腳,因此可提供較短的訊號傳輸通路,而 具有較佳的電氣特性。 雖然本發明已以前述較佳實施例揭示,然其並 非用以限定本發明,任何熟習此技藝者,在不脫離 本發明之精神和範圍内,當可作各種之更動與修 改。因此本發明之保護範圍當視後附之申請專利範 圍所界定者為準。 、【圖式簡單說明】 ^第1圖·係為根據本發明之較佳實施例之一光 學元件封裝構造之上平面視圖。 第2圖 平面視圖。 為第1圖中該光學元件封裝構造之上 第W圖:根據本發明之該光學元件封裳構造 之叙程之示意圖。 【主要元件符號說明】 110 晶片 114 背面 118 銲墊 122 密封膠 140 連接線 150 基板 154 接墊 160 晶圓 170 外蓋基板 180 刀具 184 凹槽 192 基板條
100光學元件封裴構造 112主動表面 1丄6主動區域 120外蓋 13 0封夥體 142黏著層 152線路 156銲墊 162切割線 172切割線 182刀具 186凹错
Claims (1)
1324829 七、申請專利範圍·· 1.一種光學元件封裝構造,包括:. 一晶片,具有光學元件及複數個晶片銲墊; 一密封膠’配置環繞該光學元件; 一外蓋,配置於該密封膠上; -基板’具有一上表面及一下表面,該上表面係 支撐該晶片,且係具有複數個銲墊,及該下表面係 具有複數個接墊,電性連接至該上表面之銲墊,用 以連接至一外部電路裝置; 複數條連接線,將該晶片之該晶片銲墊電性連接 至該基板之該銲墊;以及 透明封膝體’完全覆蓋該基板及該外蓋,並包 封該連接線。 2·依申請專#範圍第1項之光學元件封裝構造,其中 該基板另包括複數個線路,用以將該銲墊電性連接至 該接墊。 3. 依申請專利範圍第 該外蓋係為一濾光片 4. 依申請專利範圍第 該外蓋係為一透鏡。 5. 依申請專利範圍第 該密封膠係提供有間 1項之光學元件封裝構造,其中 〇 1項之光學元件封裝構造,其中 1項之光學元件封裝構造,其中 隙子,如此使得該外蓋與該晶片 保持均勻的間隙。 6.種光學凡件封裝構造之製造方法,其包括下列步 驟: 提供一晶圓,具有複數個晶片,每一該些晶片係 具有光學元件及複數個晶片銲墊,以及複數條第一 切割線,用以界定該些晶片; 於該晶圓上之該些晶片上,配送密封膠,環繞該 光學元件; 提供一外蓋基板,具有複數個外蓋,每一該些外 蓋係與該些晶片之光學元件相對應,以及複數條第 二切割線’用以界定該些外蓋; 將該外蓋基板與該晶圓相對齊,並配置於該晶圓 上; 將該密封膠硬化; ' 沿著該第一切割線及該第二切割線,分別分割該 曰曰圓及S玄外蓋基板,用以形成複數個預先封裝構 造; 、提供一基板條,具有複數個基板; 將該些預先封裝構造,個別的固定於該基板上; 以連接線,將該些晶片之該些銲墊電性連接至該 基板; 於該基板上,模造透明封膠體,用以包封該連接 U24S29 線;以及 分割該基板及該封膠體,以形成複數個光學元件 封裝構造》 7.依申請專利範圍第6項之光學元件封裝構造之製造 方法,其中該基板另包括複數個接墊,電性連接至該 杯塾,用以連接至一外部電路裝置。 8·依申請專利範圍第7項之光學元件封裝構造之製造 方法,其中該基板另包括複數個線路,用以將該銲墊 電性連接至該接墊。 9·依申請專利範圍第6項之光學元件封裝構造之製造 方法,其中該外蓋係為一濾光片。. 〇.依u利|&圍第6項之光學元件封裝構造之製 造方法,其中該外蓋係為一透鏡。 土依申明專利範圍第6項之光學元件封裝構造之製 造=法’其中該密封谬係提供有間隙子,如此使得該 外蓋與該晶片保持均勻的間隙。 依申。月專利範圍第6項之光學元件封裝構造之製 =法’其中在形成該些預先封裝構造之步驟中,該 沿著該第一切割線及該第二切割線,分別分割該晶圓 ^亥外盍基板之切割步驟,係不切穿該晶圓及該外蓋 基板。 13 ·依申請專利範圍第 _ 固弟6項之先學疋件封裝構造之製 12 造方法’其中在形成該 二預先封裝構造之步驟中,該 沿著該第一切割線及呼 «. t,. Μ弟一切割線,分別分割該晶圓 及4外盍基板之切割歩鮮 J 乂驟,係於該晶圓及該外蓋基板 上形成複數個凹槽。 14. 依申清專利範圍第1 9 。 祀固弟12或13項之光學元件封裝構 造之製造方法,1中在开^ 士、— 在形成該些預先封裝構造之步驟 中’另包含-裂開步驟以形成該些預先封裝構造。 15. —種光學元件之封裝構造,包括: 一晶片,具有光學元件及複數個晶片銲墊; 密封膠’包含有間隙子,該密封膠係配置環繞 該光學元件; 、外蓋配置於该密封膠上,其中該密封膠之間 隙子係用以使該外蓋與該晶片保持一間隙; 一基板’·支撐該晶片,且具有複數個銲墊;. 複數條連接線,將該晶片之該晶片銲墊電性連接 至該基板之該銲墊;以及 一透明封膠體,完全覆蓋該基板及該外蓋,並包 封該連接線。 依申請專利範圍第15項之光學元件封裝構造,其 中5玄外蓋係為一濾光片。 17.依申請專利範圍第15項之光學元件封裝構造,其 中該外蓋係為一透鏡。 13 丄 18.—種光學元件封裝構造之製造方法,其包括下列 步驟: 提供一晶圓,具有複數個晶片,每一該些晶片係 具有光學元件及複數個晶片銲墊,以及複數條第一 切割線’用以界定該些晶片; 於該晶圓上之該些晶片上,配送密封膠,環繞該 光學元件; 提供一外蓋基板,具有複數個外蓋,每一該些外 蓋係與„亥aa片之光學元件相對應,以及複數條第二 切割線,用以界定該外蓋; 將《亥外蓋基板與該晶圓相對齊,並配置於該晶圓 上; 將該密封膠硬化; 。沿著該第一切割線及該第二切割線分別於該晶 圓及该外蓋基板上形成複數個凹槽;以及 藉由破裂製程,沿著該些凹槽裂開,以形成複 數個光學元件封裝構造。 19·依申請專利範圍第18項之光學元件封裝構造之製 造方法,其中該外蓋係為一濾光片。 2〇.依申請專利範圍第18項之光學元件封裝構造之製 邊方法,其中該外蓋係為一透鏡。 f依申請專·圍第18項之光學元件封㈣造之製 14 1324829 造方法,其中該密封膠係提供有間隙子,如此使得該 外蓋與該晶片保持均勻的間隙。
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JP2005029743A JP4166759B2 (ja) | 2004-02-06 | 2005-02-04 | 光学装置のパッケージ構造体の製造方法 |
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US7785915B2 (en) * | 2006-10-30 | 2010-08-31 | Aptina Imaging Corporation | Wafer level method of locating focal plane of imager devices |
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CN102194714B (zh) * | 2010-03-05 | 2013-02-27 | 铜陵三佳科技股份有限公司 | 一种带树脂上料光电检测装置的半导体封装设备 |
US9488779B2 (en) | 2013-11-11 | 2016-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus and method of forming laser chip package with waveguide for light coupling |
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US7002241B1 (en) * | 2003-02-12 | 2006-02-21 | National Semiconductor Corporation | Packaging of semiconductor device with a non-opaque cover |
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