1359481 九、發明說明： 【發明所屬之技術領域】1359481 IX. Description of the invention: [Technical field to which the invention belongs]
«I :、本發明係有關於一種半導體封裝件及其製法，尤指— ，種感測式半導體封裝件及其製造方法。 •【先前技術】 - 傳統影像感測式半導體封裝件（Image sensor package) 主要係將感測晶片（Sensor chip)接置於一晶片承載件 上，並透過銲線加以電性連接該感測晶片及晶片承載件 鲁後’於該感測晶片上方封蓋住一透光體，以供影像光線能 為該感測晶片所擷取。如此，該完成構裝之影像感測式半 導體封裝件即可供系統廠進行整合至如印刷電路板 等外部裝置上，以供如數位相機（DSC)、數位攝影機（Dv)、 光學滑鼠、行動電話等各式電子產品之應用。 請參閱第1圖，美國專利第5,534,725號揭示一種感 測式半導體封裝件，係於導線架丨丨之晶片座丨1&上接置 一具有感測區12a之感測晶月12,並以銲線13將感測晶- 片12之銲墊12b與該導線架u之導腳Ub予以電性連接； 再以黏著層14將透光體15黏著於感測晶片12上，該黏著 層14係位於該感測區12a與該銲墊12b間，以封住且不接 觸該感測晶片12之感測區丨2a ;復利用封裝模具（未標示） 以模壓（molding)方式形成包覆該導線架u、該銲線^以 及該感測晶片12周圍之封裝膠體16，同時外露該透光體 15。 惟前述技術於形成該封裝膠體16時，因透光體15係 110627 5 1359481 直接頂抵於封裝模具之上媪允辟= 供/、之上挨内壁頂端，因此容易因模壓壓 .力而使4透光體15發生裂損，甚而壓損設於該透光體u 下方之感測晶片12，士卜外，4 # 土 ·- 片1乙此外，右該透光體15與封裝模具之 .上模内壁因壓合不喊實而產生縫隙時，亦將產生該封轉 體16溢膠至該透光體15表面之問題；再者，於該感測晶 片12上’該感測n 12a與該詳塾m㈤，亦必須留有黏著 層14之空間，如此將使得該感測晶片12必須限縮該感測 區12a之面積，亦或必須擴大感測晶片丨2尺寸如此將降 籲低該感測晶片12之使用效率。 鑑此，請參閱第2圖，美國專利第5, 962, 81〇號案揭 不種可縮小整體封裝件尺寸，且使感測晶片無壓損之虞 的感測式半導體封裝件，其係於基板21上接置—感測晶片 22，並利用銲線23電性連接該感測晶片之銲墊22b與基板 21 ’接著於該銲線23上以點膠技術敷設流動性膠體而作為 攔壩（Dam)結構24,之後於該感測晶片22之感測區22a上 塗佈透明膠25,形成一可縮小整體尺寸之感測式半導體封 裝件。 惟上述之技術中’該流動性膠體不僅製程成本高，且 產品k賴性低，因此無法為業界所普遍使用。 再者’於美國專利第5, 950, 074號、第6, 060, 340號、 第 6, 262, 479 號、第 6, 384, 472 號、第 6, 590, 269 號、第 6,犯9, 296號中，則揭露了另一種感測式半導體封裝件。 。月參閱第3A圖’該習知技術係於一基板31上形成一攔壩 結構34 ’以將一具有感測區32a之感測晶片32接置於基 6 110627 1359481 板31上且容置於該攔壩結構34中，並以銲線33電性連接 該感到晶片32之銲墊32b與基板31，再於該攔壩結構34 上設置一透光體3 5 ’以封蓋該感測晶片3 2。 另請參閱第⑽圖’美國專利第6, 545, 332號中則揭露 •相似之感測式半導體封裝件，係提供一具有晶片座3i〇a -及複數導腳310b之導線架310,於兩者間形成有第一封裝 膠體36,於該晶片座310a接置一具有感測區32a之感測 晶片32,並以銲線33將感測晶片32之銲墊3託盥該導線 #架之導腳31〇b予以電性連接，再形成一摘壤結構34 於該導腳310b上，並包圍該感測晶片32與該銲線犯，復 於該感測晶片32與該攔壩結構34間以點膠技術形成第二 封裝膠體37 ’且包覆部份連接於該導腳31〇b之銲線μ、 晶片座310a及導腳310b’最後於該攔壩結構34上設置一 透光體35,以封蓋該感測晶片32;亦或是先於該導腳 上形成攔壩結構34，再接置該感測晶片32及電性 之銲線33。 一前述技術中，主要是利用攔壩結構34及透光體35封 蓋該感測晶片32,避免透光體35直接接觸感測晶片3卜 使該感測晶片32無受塵損壞之虞，惟前述習知技術中皆存 在-共通問題，即該封裝件之整體平面尺寸係包含有晶片 尺寸、打線空間以及攔壩結構34寬度，尤為該攔壩、:構 34之設置所佔用的面積，造成整體封裝件尺寸需 以供設置該_結構34,是以無法滿足封裝件輕薄短= 110627 7 ⑸ 9481 •请麥閱第4A圖’美國專利第6,995,462號揭露一種無 攔壩結構之感測式半導體封農件，係提供—具凹槽仏之 基板41、，於該凹槽41a内接置一具有感㈣似之感測晶 .片42,並以銲線43電性連接該感測晶片42之銲墊4訃盥 該基板41，復以黏著層44將透光體45黏著於感測晶片42 上’且包覆部份連接於該銲墊42b之銲線43，以封住但不 接觸該感測晶片42之感測區42a，再於該基板41之凹槽 化中利用點勝技術以液態封裝化合物⑴㈣_ Compound, 4β 基板41上方之銲線43部分’同時外露該透 先體45 ’免去攔壩結構之製作。 ::第？圖所示，該液態封裝化合物所形成之縣膠 /d ] j.者層44間之結合性不佳’易形成脫層46a 展Π1:1"1011)’甚者可能導致同時被封裝膠體46及黏著 =4。包覆之料43受損而發生斷裂似，而使其成為不 =何提供—種感測式半導體封裝件及其製法， 传以k南感測晶片之徒用杜盘 、“……， 丰、減少封裝體積、簡化生產 :二：：作之料成本、防止不良品於製作或使用過程 ’確為相關領域上所需迫切面對之課題。 【發明内容】 鑑於前述習知技術之缺失 ^ 本發明之一目的係在提供 種了避免脫層之感測式半導體封裝件及其製法。 本發明之復-目的係在提供一種省略點膠製程之感測 8 110627 式半導體封裝件及其製法。 本發明之又一目的係在 半導體職件及其製法。 種輕㈣小化之感測式 本發明之另一目的係在提一 式半導體封裝件及其製法。/、種間化封裝製程之感測 本發明之再一目的係在提供一 、 測式半導體封裝件及其製法,、β “造成本之感 儀勺ί達ί34目的’本發明揭示之感測式半導體封裝件， 二^板1有感測區之感測晶片’係接置於該基板 線電性連接該基板與該感測晶片·，黏著層，包 J該感測晶片周緣及該鮮線，且不接觸該感測晶片之感測 :，以及透光體’係以該黏著層接置於該基板且封蓋該 感測區。 該基板可為平面格柵陣列基板（Und kid Amy， jGA) ’該I纟著層南度係大於該銲線之線弧頂部至基板之距 離，該黏著層係為遇熱具有低黏滯係數（iGw 之材質；該黏著層於室溫下係為膠片狀之樹脂類材料；該 透光體係玻璃材質。 本發明復提供一種感測式半導體封裝件之製法，係包 括.提供一基板，以於該基板上接置並以銲線電性連接一 具有感測區之感測晶片；製備一透光體，於該透光體形成 有黏著層’且該黏著層具有對應該感測區之開口；以及將 該透光體藉由該黏著層接置於該基板且加熱該基板，使該 黏著層在接著於該基板時呈熔融狀態而包覆該感測晶片肩 110627 9 1359481 緣及該銲線整體，且外露該感測晶片孓感測區，並於該黏 著層固化後使該透光體封蓋該感測區。 本發明又提供一種感測式半導體封裝件之製法，係包 括：提供一呈批次狀之基板，以於該基板接置上並以銲線 電性連接複數具有感測區之感測晶片；製備複數透光體， 其中各該透光體形成有黏著層，且該黏著層具有對應該感 測區之開口；將各該透光體藉由該黏著層接置於該基板且 加熱該基板，使該黏著層在接著於該基板時呈熔融狀態而 #包覆各該感測晶片周緣及該銲線整體，且外露各該感測晶 片之感測區，並於該黏著層固化後使各該透光體封蓋各該 感測區；以及進行切單作業，以形成複數感測式半導體封 裝件。 本發明復提供一種感測式半導體封裝件之製法，係包 括：提供-呈批次狀之基板，以於該基板上接置並以鲜線 電性連接複數具有感測區之感測晶片；製備一透光體，其 鲁中該透光體形成㈣著層，且該黏著層具有複數對應該感 測區之開口；將該透光體藉由該黏著層接置於該基板且加 熱該基板，使該黏著層在接著於該基板時呈溶融狀態而包 覆各該感測晶片周緣及該銲線整體，且外露各該感測晶片 之感測區，並於該黏著層固化後使該透光體封蓋各該感測 區，以及進行切單作業’以形成複數感測式半導體封裝件。 =:前述提供之製法中’該黏著層亦可形成有對應切單 作業時切割線位置之複數第二開口。 因此’本發明之感；則式半導體封襄件及其製法中，係 110627 10 .置於於透光體上，再將該設有黏著層之透光體接 .線，免習知=㈣著層包覆感測晶片周緣及整條銲 *取門，i、技術將黏者層設置於感測晶片之感測區與銲 . 而可省去保留於兩者間之空隙，提高减測晶片之6 •測面積比率；且兮抖牡放針祕 之感 ..,, 該封衣件之整體平面尺寸係僅包含該晶片 =及打線空間’節省了設置攔壩結構所佔用之面積， 攔壩=裳t輕薄短小之需求；另外’本發明復省去製作 攔％、、·。構、進行點膠製程以及形成多層封裝膠體，改以單 鲁種膠體-次料，俾達簡化生產流程，節省製造所需時間 及成本，且可避免因多層膠體間脫層之情形，減少不良品 之產生，俾達提升產品製造良率之效。 【實施方式】 ^下係藉由特定的具體實施例說明本發明之實施方 弋…、自此技蛰之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。 j 一實施例 明參閱第5A至5C圖，係為本發明之感測式半導體封 裝件及其製法第一實施例之剖視示意圖。 如第5A圖所示，提供一基板51，該基板51例如為平 面格栅陣列基板（Land Grid Array, LGA)，並於該基板51 上接置一具有感測區52a及銲墊52b之感測晶片52，復以 銲線53電性連接該銲墊52b與該基板51 ;以及製備一透 光體55(如玻璃板），其中該透光體55周緣形成有黏著層 54 ’該黏著層54高度係大於該銲線53線弧頂部至該基板 11 110627 ~乃481 2間之距離，其中該黏著層54於室溫下係為膠片狀之樹 月曰颁材料，如％、氧樹脂膠片（ep〇xy tape)，且該黏著層Μ 具有對應該感測區52a之開口 54a。 、如第5B圖所不，將該透光體55藉由該黏著層54接置 於感測晶片52且加熱該基板51，使該黏著層“在接著於 k基板51柃壬低黏滯係數（1〇w visc〇sity)之熔融狀態而 包覆該感測晶片52肖緣及該銲線53_，且外露該感測 晶片52之感測區52a。 如第5C圖所示’移除熱源後讓該黏著層54冷卻固化， 而使該透光體55封蓋該感測區52a，以形成一感測式半導 體封裝件50。 本發明復揭示-種感測式半導體封裝件5〇，係包括： 基板51 ;具有感測區52a及銲墊52b之感測晶片52,係接 置=該基板51上’並以銲線53電性連接該基板51與該感 測0曰片52之銲墊52b ;黏著層54，係包覆該感測晶片52 周緣及該料53整體，且不接觸該感測晶片52之感測區 52a’以及透光體55，係以該黏著層54接置於該基板5ι， 且封蓋該感測區52a。 該基板51可為平面格栅陣列基板；該黏著層54高度 1 系大於該銲線53之線弧頂部至該基板51間之距離；該黏 著層54例如為壤氧樹脂膠片’在遇熱時具有低黏滯係數； 該透光體55係為玻璃材質。 多二實施例 另π參閱第6A至6D圖，係為本發明之感測式半導體 110627 12 1359481 封裝件之製法第二實施例之剖視示意圖。本實施例與第一 實施例大致相同，主要差異係將複數感測晶片接置並電性 :連接至呈批次（batch)狀之基板上，再於該基板上接置^數 設有黏著層之透光體，並切割形成複數封裝件。 如第6A圖所示，提供一呈批次狀之基板61，該基板 61具有複數基板單元，以於該基板61上接置複數具有感 測區62a及銲墊62b之感測晶片62，並以銲線63電性連 接該銲墊62b與該基板61;以及製備複數透光體65，於各 •該透光體65形成有黏著層64,且該黏著層64具有對應該 感測區62a之開口 64a。 〆 如第6B圖所示，將各該透光體65藉由該黏著層64 接置於該基板61且加熱該基板61，使該黏著層64在接著 於該基板61時呈低黏滯係數之熔融狀態而包覆各該感測 晶片62周緣及該銲線63整體，且外露各該感測晶片62 之感測區62a。 _ 如第6C圖所示，移除熱源後讓該黏著層64冷卻固化， 而使該透光體65封蓋該感測區62a。 如第6D圖所示，進行切單作業，以形成複數感測式半 導體封裝件6 0。 藉此，於批次狀之基板61上製作形成複數感測式半導 體封裝件60，以達量產及簡化製程之功效。 J三膏施例 5月參閱第7A至7D圖’係為本發明之感測式半導體封 裝件之製法第三實施例之剖視示意圖。本實施例與第一實 110627 13 .施例大致相同，主要差異係將複數感測晶片接置並電性連 • ^至呈批讀之基板上，再於絲板上接置設⑽著層之 :整片式透光體，且該點著層具有複數對應該感測晶月感測 區之開口。 如第7A圖所示，提供一呈批次狀之基板71，並於該 基板71接置複數具有感測區72a及鲜塾⑽之感測晶片 72,且以銲線73電性連接該感測晶片72之銲墊與該 基板71 ;同時製備一對應該批次基板71之整片式透光體 7^5於孩透光體75形成有黏著層74，且該黏著層具有 複數對應該感測區72a之開口 74a。 如第7B圖所示’將該透光體75藉由該黏著層74接置 於該基板71且加熱該基板71，使該黏著層74在接著於該 基板71 _呈低黏滯係數之熔融狀態而包覆各該感測晶片 72周緣及該銲線73整體，且外露各該感測晶片72之感測 區 72a。 φ 如第7C圖所示’移除熱源後讓該黏著層74冷卻固化， 而使該透光體75封蓋該感測區72a。 最後如第7D圖所示，進行切單作業’以形成複數感測 式半導體封裝件70。 藉此，利用批次狀之基板71及整片式透光體75之結 合與切單以製作複數感測式半導體封裝件7〇，進而達到量 產及簡化製程之功效。 第四f施例 4參閱第8A至8D圖，係為本發明之感測式半導體封 110627 14 1359481 裝件之製法第四實施例之剖視示意圖。 本實施例與第一實施例大致相同，主要差異係將複數 具有感測區82a之感測晶片82接置並電性連接至呈批次狀 之基板81上’再於該基板81上接置設有黏著層84之透光 體85,且該黏著層84具有對應該感測晶片82之感測區82a 之開口 84a，以及對應切單作業時切割線之複數第二開口 84b，以節省該黏著層84之使用材料。 因此 尽心月之感測式半導體封裝件及其製法中，係 ♦將黏著層麗於透光體上，再㈣設有㈣層之透光體接 置於基板上，且使該黏著層包覆感測晶片周緣及整條鲜 線，避免習知技術將點著層設置於感測晶片之感測區盘鲜 墊間’而可省去保留於兩者間之空隙，提高感測晶月之感«I: The present invention relates to a semiconductor package and a method of fabricating the same, and more particularly to a sensing semiconductor package and a method of fabricating the same. • [Previous Technology] - A conventional image sensor package is mainly provided by attaching a sensor chip to a wafer carrier and electrically connecting the sensor chip through a bonding wire. And the wafer carrier is rearwardly covered with a light transmissive body above the sensing wafer for image light to be captured by the sensing wafer. In this way, the completed image sensing semiconductor package can be integrated by the system factory into an external device such as a printed circuit board for use in a digital camera (DSC), a digital camera (Dv), an optical mouse, The use of various electronic products such as mobile phones. Referring to FIG. 1 , a sensing semiconductor package is disclosed in the wafer holder 1& of the lead frame, and a sensing crystal 12 having a sensing region 12a is attached thereto, and The bonding wire 13 electrically connects the bonding pad 12b of the sensing wafer 12 to the guiding leg Ub of the lead frame u; and adheres the transparent body 15 to the sensing wafer 12 by the adhesive layer 14, the adhesive layer 14 The sensing region 12a is disposed between the sensing region 12a and the bonding pad 12b to block and not contact the sensing region 丨2a of the sensing wafer 12; and the packaging mold (not labeled) is formed by molding in a molding manner. The lead frame u, the bonding wire ^ and the encapsulant 16 around the sensing wafer 12 are simultaneously exposed to the transparent body 15. However, when the above-mentioned technology is used to form the encapsulant 16, the light-transmitting body 15 is directly connected to the top of the inner wall of the package by the light-transmitting body 15 110627 5 1359481, so that it is easy to be pressed by the pressure. 4 The light-transmissive body 15 is cracked, and even the pressure loss is provided on the sensing wafer 12 under the light-transmitting body u, and the outer surface of the light-transmitting body 15 and the package mold When the inner wall of the upper mold is cracked due to the uncompressed pressing, the problem that the sealing body 16 overflows to the surface of the transparent body 15 is also generated; further, the sensing wafer 12 is 'sensing n' 12a and the detailed description (m), the space of the adhesive layer 14 must also be left, so that the sensing wafer 12 must be limited to the area of the sensing region 12a, or the size of the sensing wafer 丨2 must be enlarged. The sensing wafer 12 is used efficiently. In view of this, please refer to FIG. 2, and a method for reducing the size of the entire package and sensing the wafer without pressure loss is disclosed in the U.S. Patent No. 5,962,81. The substrate 22 is connected to the sensing wafer 22, and the bonding pad 22b and the substrate 21' are electrically connected to the sensing wafer by the bonding wire 23, and then the liquid colloid is laid on the bonding wire 23 by a dispensing technique. A Dam structure 24 is then coated with a transparent adhesive 25 on the sensing region 22a of the sensing wafer 22 to form a sensing semiconductor package that can be reduced in overall size. However, in the above-mentioned technology, the fluid colloid not only has high process cost, but also has low product dependency, and thus cannot be widely used in the industry. Further, 'U.S. Patent Nos. 5,950, 074, 6, 060, 340, 6, 262, 479, 6, 384, 472, 6, 590, 269, 6 In 9, 296, another type of sensing semiconductor package is disclosed. . Referring to FIG. 3A, the conventional technique is to form a dam structure 34' on a substrate 31 to connect a sensing wafer 32 having a sensing region 32a to a substrate 31 of a base 6 110627 1359481 and accommodate it. The dam structure 34 is electrically connected to the solder pad 32b of the susceptor 32 and the substrate 31 by a bonding wire 33, and a light transmitting body 35' is disposed on the dam structure 34 to cover the sensing chip. 3 2. In addition, a similar type of sensing semiconductor package is disclosed in the above-mentioned U.S. Patent No. 6,545,332, the disclosure of which is incorporated herein by reference. A first encapsulant 36 is formed between the two, and a sensing wafer 32 having a sensing region 32a is disposed on the wafer holder 310a, and the bonding pad 3 of the sensing wafer 32 is supported by the bonding wire 33. The lead leg 31〇b is electrically connected, and a picking structure 34 is formed on the lead leg 310b, and surrounds the sensing chip 32 and the bonding wire, and the sensing chip 32 and the dam structure are repeated. 34 solder lines μ, a wafer holder 310a and a lead leg 310b', which are formed by a dispensing technique to form a second encapsulant 37' and have a covering portion connected to the lead 31b, are finally provided on the dam structure 34. The light body 35 is used to cover the sensing wafer 32; or the dam structure 34 is formed on the guiding foot, and the sensing wafer 32 and the electrical bonding wire 33 are connected. In the foregoing technology, the sensing die 32 is mainly covered by the dam structure 34 and the transparent body 35, so as to prevent the transparent body 35 from directly contacting the sensing wafer 3, so that the sensing wafer 32 is not damaged by dust. However, there is a common problem in the prior art that the overall planar size of the package includes the size of the wafer, the space for the wire, and the width of the dam structure 34, especially the area occupied by the dam, the arrangement of the structure 34, The overall package size needs to be set for the _ structure 34, so that the package can not be light and short = 110627 7 (5) 9481 • Please refer to the 4A drawing of US Patent No. 6,995, 462 to disclose a sensing type without dam structure. The semiconductor sealing member is provided with a substrate 41 having a recessed surface, and a sensing substrate 42 having a sensing force is attached to the recess 41a, and the sensing wafer is electrically connected by a bonding wire 43. 42 pads 4 讣盥 the substrate 41, the adhesive layer 44 is adhered to the light-transmissive body 45 on the sensing wafer 42 and the cladding portion is connected to the bonding wire 43 of the bonding pad 42b to seal but not Contacting the sensing region 42a of the sensing wafer 42 and utilizing the dot in the recessing of the substrate 41 The winning technique encapsulates the compound (1) (4)_ Compound, the portion of the bonding wire 43 above the 4β substrate 41, while simultaneously exposing the through-hole 45' to eliminate the fabrication of the dam structure. ::第? As shown in the figure, the combination of the county gel/d] j. formed by the liquid encapsulating compound is not good, and the formation of the delamination 46a is easy to form a delamination 46a. 1:1 "1011)' may cause the encapsulated colloid 46 at the same time. And adhesion = 4. The coated material 43 is damaged and fractured, so that it is not provided by the sensing semiconductor package and its manufacturing method, and the k-nan sensing wafer is used by the disc, "..., Feng Reducing the package volume and simplifying production: 2: The cost of materials and the prevention of defective products in the production or use process are indeed urgent issues for the related fields. [Disclosure] In view of the lack of the aforementioned prior art ^ SUMMARY OF THE INVENTION One object of the present invention is to provide a sensing semiconductor package that avoids delamination and a method of fabricating the same. The present invention is directed to providing a sensing method for omitting a dispensing process, and a method for fabricating the same. Another object of the present invention is to provide a semiconductor device and a method for fabricating the same. The other object of the present invention is to provide a semiconductor package and a method for fabricating the same. A further object of the present invention is to provide a test semiconductor package and a method for fabricating the same, and a beta sensor of the present invention disclosed in the present invention. 1 has a sensing area The sensing chip is electrically connected to the substrate and electrically connected to the sensing substrate, the adhesive layer, the sensing chip periphery and the fresh line, and does not touch the sensing of the sensing wafer: And the light transmissive body is attached to the substrate with the adhesive layer and covers the sensing region. The substrate may be a planar grid array substrate (Und kid Amy, jGA) 'the thickness of the layer is greater than the distance from the top of the wire arc of the bonding wire to the substrate, and the adhesive layer has a low viscosity coefficient due to heat. The material of the iGw; the adhesive layer is a film-like resin material at room temperature; the light-transmissive system glass material. The invention provides a method for manufacturing a sensing semiconductor package, comprising: providing a substrate to A sensing wafer having a sensing region is electrically connected to the substrate, and a light-transmitting body is formed, and an adhesive layer is formed on the transparent body, and the adhesive layer has a corresponding sensing region. And the transparent body is attached to the substrate by the adhesive layer and the substrate is heated, so that the adhesive layer is in a molten state when the substrate is attached to cover the sensing wafer shoulder 110627 9 1359481 and the edge The soldering wire is entirely exposed, and the sensing area of the sensing wafer is exposed, and the transparent body is covered by the sensing area after the adhesive layer is cured. The invention further provides a method for manufacturing a sensing semiconductor package, which comprises : providing a batch of substrate to A plurality of sensing wafers having a sensing region are electrically connected to the substrate and electrically connected to the bonding wires; and the plurality of transparent bodies are formed, wherein each of the transparent bodies is formed with an adhesive layer, and the adhesive layer has a corresponding sensing region Opening, each of the light-transmitting bodies is placed on the substrate by the adhesive layer, and the substrate is heated, so that the adhesive layer is in a molten state when it is next to the substrate, and the periphery of the sensing wafer and the solder are coated. The entire line is exposed, and the sensing regions of the sensing wafers are exposed, and after the adhesive layer is cured, each of the transparent bodies covers the sensing regions; and the singulation operation is performed to form a complex sensing semiconductor package. The invention provides a method for fabricating a sensing semiconductor package, comprising: providing a substrate in a batch shape, and attaching on the substrate and electrically connecting a plurality of sensing regions with sensing regions a light-transmissive body, wherein the light-transmissive body forms a (four) layer, and the adhesive layer has a plurality of openings corresponding to the sensing regions; the light-transmitting body is attached to the substrate by the adhesive layer and Heating the substrate such that the adhesive layer is followed by the substrate And covering the periphery of the sensing wafer and the whole of the bonding wire in a molten state, and exposing the sensing regions of the sensing wafers, and after the adhesive layer is cured, the transparent body covers each of the sensing regions And performing a singulation operation to form a complex sensing semiconductor package. =: In the above-mentioned method of manufacture, the adhesive layer may also be formed with a plurality of second openings corresponding to the position of the cutting line during the singulation operation. The sense of the semiconductor seal and its manufacturing method, 110627 10 . placed on the light-transmitting body, and then the light-transmitting body with the adhesive layer connected to the line, free of knowledge = (four) layer coating Sensing the periphery of the wafer and the entire soldering* to take the door, i, the technology is to set the adhesive layer on the sensing area and the soldering of the sensing wafer, and the gap between the two can be omitted, and the chip can be improved. Measuring the area ratio; and the feeling of shaking the needles of the oysters..,, the overall planar size of the closure only contains the wafer = and the line space 'saving the area occupied by the dam structure, dam = skirt t light and short needs; in addition, 'the invention is re-educated to make the block %,, ·. Structure, carry out the dispensing process and form a multi-layer encapsulant, and change to a single colloidal-primary material, which simplifies the production process, saves time and cost for manufacturing, and avoids delamination between layers of colloids. The production of good products, the company to improve the efficiency of product manufacturing. [Embodiment] The embodiments of the present invention are described by way of specific embodiments, and those skilled in the art can readily appreciate other advantages and effects of the present invention from the disclosure herein. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 5A to FIG. 5C are cross-sectional views showing a first embodiment of a sensing semiconductor package of the present invention and a method of manufacturing the same. As shown in FIG. 5A, a substrate 51 is provided. The substrate 51 is, for example, a Land Grid Array (LGA), and a sensing area 52a and a bonding pad 52b are attached to the substrate 51. The measuring chip 52 is electrically connected to the bonding pad 52b and the substrate 51 by a bonding wire 53; and a transparent body 55 (such as a glass plate) is prepared, wherein the transparent body 55 is formed with an adhesive layer 54'. The height of the 54 is greater than the distance from the top of the wire arc of the bonding wire 53 to the distance between the substrate 11 110627 and the 481 2, wherein the adhesive layer 54 is a film-like tree at room temperature, such as %, oxygen resin film. (ep〇xy tape), and the adhesive layer Μ has an opening 54a corresponding to the sensing region 52a. As shown in FIG. 5B, the light-transmissive body 55 is placed on the sensing wafer 52 by the adhesive layer 54 and the substrate 51 is heated, so that the adhesive layer "has a low viscosity coefficient after the k-substrate 51. The immersion state of the sensing wafer 52 and the bonding wire 53_ are exposed in a molten state of (1〇w visc〇sity), and the sensing region 52a of the sensing wafer 52 is exposed. As shown in FIG. 5C, the heat source is removed. The adhesive layer 54 is then cooled and solidified, and the light transmissive body 55 covers the sensing region 52a to form a sensing semiconductor package 50. The present invention discloses a sensing semiconductor package 5〇, The system includes: a substrate 51; a sensing wafer 52 having a sensing region 52a and a pad 52b, which is connected to the substrate 51 and electrically connected to the substrate 51 and the sensing die 52 by a bonding wire 53. The bonding pad 52b is an adhesive layer 54 that covers the periphery of the sensing wafer 52 and the entire material 53 and does not contact the sensing region 52a' of the sensing wafer 52 and the light transmitting body 55, and is adhered by the adhesive layer 54. The substrate 51 is placed on the substrate 5, and the sensing region 52a is covered. The substrate 51 can be a planar grid array substrate; the height of the adhesive layer 54 is greater than the top of the wire arc of the bonding wire 53 to The distance between the substrates 51; the adhesive layer 54 is, for example, a oxy-resin film having a low viscosity coefficient when heated; the light-transmitting body 55 is made of glass. The second embodiment is further referred to as Figures 6A to 6D. A schematic cross-sectional view of a second embodiment of a method for fabricating a packaged semiconductor of the present invention. The present embodiment is substantially the same as the first embodiment. The main difference is that the plurality of sensing wafers are connected and electrically connected. : connected to a batch-shaped substrate, and then connected to the substrate with a light-transmitting body provided with an adhesive layer, and cut to form a plurality of packages. As shown in FIG. 6A, a batch is provided The substrate 61 has a plurality of substrate units, and the plurality of sensing wafers 62 having the sensing regions 62a and the pads 62b are connected to the substrate 61, and the pads 62b are electrically connected to the pads 62b. And the substrate 61; and the plurality of transparent bodies 65 are formed, and the light-transmissive body 65 is formed with an adhesive layer 64, and the adhesive layer 64 has an opening 64a corresponding to the sensing region 62a. For example, as shown in FIG. 6B The light transmissive body 65 is placed on the substrate 61 by the adhesive layer 64 and heated. The substrate 61 covers the periphery of each of the sensing wafers 62 and the entire bonding wires 63 in a molten state with a low viscous coefficient when the adhesive layer 64 is attached to the substrate 61, and exposes the sense of each of the sensing wafers 62. The measuring area 62a. _ As shown in FIG. 6C, after the heat source is removed, the adhesive layer 64 is cooled and solidified, and the light transmitting body 65 covers the sensing area 62a. As shown in FIG. 6D, the singulation operation is performed. In order to form a complex sensing semiconductor package 60, a plurality of sensing semiconductor packages 60 are formed on the batch substrate 61 to achieve mass production and simplify the process. J. Three Paste Application Example Referring to Figures 7A to 7D in May, it is a schematic cross-sectional view showing a third embodiment of the method of manufacturing the sensing semiconductor package of the present invention. This embodiment is substantially the same as the first embodiment 110627 13 . The main difference is that the plurality of sensing wafers are connected and electrically connected to the substrate for batch reading, and then placed on the silk plate (10). The whole piece of light transmissive body, and the point layer has a plurality of openings corresponding to the sensing of the crystal sensing region. As shown in FIG. 7A, a batch-shaped substrate 71 is provided, and a plurality of sensing wafers 72 having sensing regions 72a and fresh enamels (10) are connected to the substrate 71, and the sensation is electrically connected by the bonding wires 73. The bonding pad of the wafer 72 and the substrate 71 are simultaneously formed; at the same time, a whole-piece transparent body 7^5 for preparing a pair of substrates 71 is formed, and an adhesive layer 74 is formed on the light transmitting body 75, and the adhesive layer has a plurality of corresponding layers. The opening 74a of the sensing region 72a. As shown in FIG. 7B, the light-transmissive body 75 is attached to the substrate 71 by the adhesive layer 74 and the substrate 71 is heated, so that the adhesive layer 74 is melted at a low viscosity coefficient following the substrate 71. The periphery of each of the sensing wafers 72 and the entire bonding wires 73 are covered by the state, and the sensing regions 72a of the sensing wafers 72 are exposed. φ is as shown in Fig. 7C. After the heat source is removed, the adhesive layer 74 is cooled and solidified, and the light transmitting body 75 covers the sensing region 72a. Finally, as shown in Fig. 7D, a singulation operation is performed to form a complex-sensing semiconductor package 70. Thereby, the combination of the batch-shaped substrate 71 and the one-piece translucent body 75 is used to form a plurality of sensing semiconductor packages 7 〇, thereby achieving mass production and simplification of the process. 4F to 4D is a cross-sectional view showing a fourth embodiment of the method for manufacturing the sensing semiconductor package 110627 14 1359481 of the present invention. This embodiment is substantially the same as the first embodiment. The main difference is that the plurality of sensing wafers 82 having the sensing regions 82a are connected and electrically connected to the substrate 81 of the batch shape and then placed on the substrate 81. A light transmissive body 85 having an adhesive layer 84 is provided, and the adhesive layer 84 has an opening 84a corresponding to the sensing region 82a of the sensing wafer 82, and a plurality of second openings 84b corresponding to the cutting line during the singulation operation to save the The material used for the adhesive layer 84. Therefore, in the sensing semiconductor package and the manufacturing method thereof, the adhesive layer is glazed on the transparent body, and (4) the transparent body provided with the (four) layer is placed on the substrate, and the adhesive layer is coated. Sensing the periphery of the wafer and the entire fresh line, avoiding the conventional technique of placing the layer on the sensing pad of the sensing wafer, and eliminating the gap between the two to improve the sensing of the crystal moon. sense
測面積比率；且該封裝件之整體平面尺寸係僅包含該W 尺寸以及打線空間，節省了設置搁壤結構所佔用之面積， ^滿足封裝件輕薄短小之需求；料，省去製作觸結構、 =點膠製程以及形成多層封裳膠體，改以單種膠體一次 叮裝’俾達簡化生產流程’節省製造所需時間及成本，且 ，因多層膠體間脫層之情形，減少不良品之產 達表1升產品製造良率之效。 上述實施例僅例示性說明本發明之原理及 非用於限制本發明，任何孰習 、效而 皆太^ 17㉚自此項技敎人士均可在不違 變。因此之及範訂’對上述實施例進行修娜與改 :圍:：:本發明之權利保護範圍，應如後述之申請“ 110627 15 1359481 【圖式簡單說明】 5，5 3 4，7 2 5藏所揭露之感測式 弟1圖係為美國專利第 半導體封裝件剖面示意圖； 式半案所揭露之感測 第3A圖係為習知感測式半導體封裝件剖面示意圖； 第3B圖係為美國專利第6 545 332號 感測式半導體封裝件剖面示意圖； 号路之白知 第4A圖係為美國專利第6, 995, 462號案所揭露之習知 感測式半導體封裝件剖面示意圖； 表示多層膠體間 第4B圖係為第4A圖之局部放大圖 之脫層現象； 第5A至5C圖係為本發明之感測式半導體封裝件第一 實施例之剖視示意圖； 第6A至6D圖係為本發明之感測式半導體封裝件第二 實施例之剖視示意圖； 一 第7A至7D圖係為本發明之感測式半導體封裝件第二 實施例之剖視示意圖；以及 第8A至8D圖係為本發明之感測式半導體封裝件第四 實施例之剖視示意圖。 【主要元件符號說明】 11，310 導線架 11a, 310a 晶片座 lib, 310b 導腳 110627 16 1359481 12, 22, 32, 42 感測晶片 12a, 22a, 32a, 42a 感測區 12b, 22b, 32b, 42b 銲墊 13, 23, 33, 43 銲線 14, 44 黏著層 15, 35, 45 透光體 16 封裝膠體 21, 31 基板 24 攔壩結構 25 透明膠 34 攔壞結構 36 第一封裝膠 體 37 第二封裝膠 體 41 基板 41a 43a •46 46a 50, 60，70 51， 61， 71， 81 52，62，72，82 52a, 62a, 72a, 82a 52b, 62b, 72b 53, 63, 73 凹槽 銲線斷裂 封裝膠體 脫層 感測式半導體封裝件 基板 感測晶片 感測區 銲墊 銲線 1359481 54，64，74，84 54a, 64a, 74a, 84a 55, 65, 75, 85 84b 黏著層 開口 透光體 第二開口Measuring the area ratio; and the overall planar size of the package includes only the W size and the wire-bonding space, which saves the area occupied by the setting of the soil-staying structure, and satisfies the requirement of lightness and thinness of the package; = Dispensing process and the formation of multi-layer sealant colloids, instead of a single type of colloidal one-time installation 'Simplified production process' saves time and cost of manufacturing, and reduces the production of defective products due to delamination between layers of colloid Up to 1 liter of product manufacturing yield efficiency. The above-described embodiments are merely illustrative of the principles of the present invention and are not intended to limit the present invention. Any of the disadvantages and effects are too much to be used by those skilled in the art. Therefore, it is intended to modify and modify the above embodiments:::: The scope of protection of the present invention should be as described later. "110627 15 1359481 [Simple description of the drawings] 5,5 3 4,7 2 The sensing type 1 shown in the U.S. is a schematic cross-sectional view of a semiconductor package of the U.S. patent; the sensing of the third embodiment is a schematic cross-sectional view of a conventional sensing semiconductor package; FIG. 4A is a schematic cross-sectional view of a sensing semiconductor package disclosed in US Pat. No. 6, 545, 462; FIG. 4A is a schematic cross-sectional view of a conventional sensing semiconductor package disclosed in US Pat. No. 6,995,462. Figure 4B shows a delamination phenomenon of a partial enlarged view of FIG. 4A; FIGS. 5A to 5C are schematic cross-sectional views of the first embodiment of the sensing semiconductor package of the present invention; 6D is a cross-sectional view of a second embodiment of a sensing semiconductor package of the present invention; a 7A to 7D is a cross-sectional view of a second embodiment of the sensing semiconductor package of the present invention; 8A to 8D drawings are the feeling of the present invention Schematic diagram of a fourth embodiment of a semiconductor package. [Main component symbol description] 11,310 lead frame 11a, 310a wafer holder lib, 310b pin 110627 16 1359481 12, 22, 32, 42 sensing wafer 12a, 22a , 32a, 42a Sensing area 12b, 22b, 32b, 42b Pad 13, 23, 33, 43 Bonding wire 14, 44 Adhesive layer 15, 35, 45 Transmissive body 16 Encapsulant 21, 31 Substrate 24 Dam structure 25 Transparent adhesive 34 Barrier structure 36 First encapsulant 37 Second encapsulant 41 Substrate 41a 43a • 46 46a 50, 60, 70 51, 61, 71, 81 52, 62, 72, 82 52a, 62a, 72a, 82a 52b , 62b, 72b 53, 63, 73 Groove wire breakage package colloidal delamination sensing semiconductor package substrate sensing wafer sensing area pad bond wire 1594481 54,64,74,84 54a, 64a, 74a, 84a 55, 65, 75, 85 84b Adhesive layer open transmissive body second opening
18 11062718 110627