TW200929453A - Sensor semiconductor package and method thereof - Google Patents

Sensor semiconductor package and method thereof Download PDF

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Publication number
TW200929453A
TW200929453A TW096150714A TW96150714A TW200929453A TW 200929453 A TW200929453 A TW 200929453A TW 096150714 A TW096150714 A TW 096150714A TW 96150714 A TW96150714 A TW 96150714A TW 200929453 A TW200929453 A TW 200929453A
Authority
TW
Taiwan
Prior art keywords
sensing
adhesive layer
substrate
semiconductor package
wafer
Prior art date
Application number
TW096150714A
Other languages
Chinese (zh)
Other versions
TWI359481B (en
Inventor
Tse-Wen Chang
Chang-Yueh Chan
Chin-Huang Chang
Chih-Ming Huang
Original Assignee
Siliconware Precision Industries Co Ltd
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Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to TW096150714A priority Critical patent/TWI359481B/en
Priority to US12/344,988 priority patent/US20090166831A1/en
Publication of TW200929453A publication Critical patent/TW200929453A/en
Application granted granted Critical
Publication of TWI359481B publication Critical patent/TWI359481B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch

Abstract

This invention provides a sensor semiconductor package and a method thereof. The method includes: providing a substrate; mounting on the substrate a sensor chip with a sensor area; electrically connecting the sensor chip and the substrate by means of a bonding wire; forming on a transparent element an adhesive layer corresponding in position to an opening in the sensor area; and mounting the transparent element on the substrate via the adhesive layer and heating up the transparent element such that the adhesive layer melts when attached to the substrate, encapsulates the rim of the sensor chip and the bonding wire, but exposes the sensor area, thus sealingly covering the sensor area with the transparent element. The sensor semiconductor package is dam-free, light, thin, and compact, and incurs low process costs. Product reliability is enhanced, as the bonding wire is encapsulated by the adhesive layer and therefore prevented from severing.

Description

200929453 九、發明說明： « 【發明所屬之技術領域】 树明係有關於—種半導體封裝件及其製法，尤指一 ：種感測式半導體封裝件及其製造方法。 【先前技術】 傳統影像感測式半導體封裝件（Image sensor package) 主要係將感測晶片（Sensor chip)接置於一晶片承载件 上，並透過銲線加以電性連接該感測晶片及晶片承載件 〇後，於該感測晶片上方封蓋住一透光體，以供影像光線能 為該感測晶片所擷取。如此，該完成構裝之影像感測式半 導體封裝件即可供系統廠進行整合至如印刷電路板（PCB ) 等外部裝置上，以供如數位相機（DSC)、數位攝影機（DV)、 光學滑鼠、行動電話等各式電子產品之應用。 請參閱第1圖，美國專利第5,534,725號揭示一種感 測式半導體封裝件，係於導線架〗丨之晶片座丨la上，接置 ❹一具有感測區12a之感測晶片12，並以銲線13將感測晶 片12之銲墊12b與該導線架η之導腳llb予以電性連接； 再以黏著層14將透光體15黏著於感測晶片12上，該黏著 層14係位於該感測區12 a與該鲜塾12 b間，以封住且不接 觸該感測晶片12之感測區12 a ;復利用封裝模具（未標示） 以模壓（molding)方式形成包覆該導線架u、該銲線13以 及該感測μ片12周圍之封裝膠體16’同時外露該透光體 15 ° 惟前述技術於形成該封裝膠體16時，因透光體15係 110627 5 200929453 •直接頂抵於封裝模具之上模内壁頂端，因此容易因模壓壓 .力而使該透光體15發生裂損，甚而壓損設於該透光體15 下方之感測晶片12，此外，若該透光體15與封裝模具之 :上模内I因壓合不#實而產生縫隙肖，亦將產生該封裝膠 體16溢膠至該透光體15表面之問題；再者，於該感測晶 片12上，該感測區12a與該銲墊12b間，亦必須留有黏著 層14之空間，如此將使得該感測晶片12必須限縮該感測 區12a之面積，亦或必須擴大感測晶片i 2尺寸，如此將降 〇低該感測晶片12之使用效率。 鑑此，請參閱第2圖，美國專利第5,962,81〇號案揭 示一種可縮小整體封裝件尺寸，且使感測晶片無壓損之虞 的感測式半導體封裝件，其係於基板21上接置一感測晶片 22’並利用銲線23電性連接該感測晶片之銲墊22b與基板 21 ’接著於該銲線23上以點膠技術敷設流動性膠體而作為 棚壩（Dam)結構24 ’之後於該感測晶片22之感測區22a上 塗佈透明膠25 ’形成一可縮小整體尺寸之感測式半導體封 W裝件。 惟上述之技術中’該流動性膠體不僅製程成本高，且 產品信賴性低’因此無法為業界所普遍使用。 再者’於美國專利第5, 950, 074號、第6, 060,340號、 第 6’ 262’ 479 號、第 6, 384, 472 號、第 6, 590, 269 號、第 6’989’296號中’則揭露了另一種感測式半導體封裝件。 。月參閱第3 A圖，該習知技術係於一基板31上形成一攔場 結構34 ’以將一具有感測區32a之感測晶片32接置於基 6 110627 200929453 板31上且容置於該攔壩結構34中’並以銲線33電性連接 •該感測晶片32之銲墊32b與基板31，再於該攔壩結構34 上設置一透光體35 ’以封蓋該感測晶片32。 另請參閱第3B圖，美國專利第6, 545, 332號中則揭露 相似之感測式半導體封裝件，係提供一具有晶片座31 〇& 及複數導腳310b之導線架310,於兩者間 膠體36,於該晶片座310a接置一具有感測 晶片32,並以銲線33將感測晶片32之銲墊32b盥該導線 〇架31〇之導腳31〇b予以電性連接，再形成一觸結構以 於該導腳310b上，並包圍該感測晶片32與該銲線”，復 於該感測晶片32與該攔壩結構34間以點膠技術形成第二 封裝膠體37,且包覆部份連接於該導腳31牝之銲線33、 晶片座310a及導腳310b，最後於該攔壩結構34上設置一 透光體35,以封蓋該感測晶片32;亦或是先於該導腳鳩 上形成攔壩結構34,再接置該感測晶片犯及 之銲線33。 〇 則述技術中主要疋利用搁壤結構34及透光體犯封 蓋該感測晶片32,避免透光體35直接接觸感測晶片犯， 使該感測晶片32益受愿;f昌掠少由u. , …又歷損壞之虞，惟前述習知技術中皆存 在一共通問題’即該封裝件之整體 衣什之正體千面尺寸係包含有晶片 尺寸、打線空間以及攔壩結構34寬度， 34之設置所佔料面積，造成整 爛壩…構 以供e又置該攔壩結構3 4，是以|g 疋以無法滿足封裝件輕薄短小之 需求。 110627 7 200929453 • 月4閱第4A圖，美國專利第6, 995, 462號揭露一種盔200929453 IX. Invention Description: «The technical field of the invention belongs to the invention. The invention relates to a semiconductor package and a method for manufacturing the same, and more particularly to a sensing semiconductor package and a manufacturing method thereof. The prior art image sensor package mainly connects a sensor chip to a wafer carrier and electrically connects the sensor chip and the wafer through a bonding wire. After the carrier is folded, a light-transmissive body is capped over the sensing wafer for the image light to be captured by the sensing wafer. In this way, the completed image sensing semiconductor package can be integrated by the system factory into an external device such as a printed circuit board (PCB) for use in, for example, a digital camera (DSC), a digital camera (DV), and optical The application of various electronic products such as mouse and mobile phone. Referring to FIG. 1, a sensing semiconductor package is disclosed on a wafer carrier 丨1a of a lead frame, and a sensing wafer 12 having a sensing region 12a is attached thereto, and The bonding wire 13 electrically connects the pad 12b of the sensing wafer 12 and the guiding leg 11b of the lead frame n; the bonding layer 14 is adhered to the sensing wafer 12 by an adhesive layer 14, and the adhesive layer 14 is located The sensing area 12a is spaced between the sensing area 12b and the sensing area 12a of the sensing wafer 12; and the packaging mold (not labeled) is formed by molding in a molding manner. The lead frame u, the bonding wire 13 and the encapsulant 16' around the sensing microchip 12 simultaneously expose the transparent body 15 °. However, the foregoing technique is used to form the encapsulant 16 because the transparent body 15 is 110627 5 200929453. Directly abutting against the top end of the inner wall of the mold on the package mold, so that the light-transmissive body 15 is easily broken by the pressure of the mold, and even the pressure-damaged sensing wafer 12 is disposed under the light-transmitting body 15, and further, The light-transmissive body 15 and the package mold: the upper mold I is not pressed due to the actual pressure, and will also be The problem that the encapsulant 16 overflows onto the surface of the transparent body 15 is generated. Further, on the sensing wafer 12, the space between the sensing region 12a and the pad 12b must also be left with the adhesive layer 14. This will make the sensing wafer 12 have to be limited to the area of the sensing region 12a, or the size of the sensing wafer i 2 must be enlarged, which will lower the efficiency of use of the sensing wafer 12 . In this regard, referring to FIG. 2, U.S. Patent No. 5,962,81, the disclosure of which is incorporated herein by reference to the entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire all A soldering pad 22 ′ is electrically connected to the sensing pad 22 ′ and the bonding pad 22 b and the substrate 21 ′ are electrically connected to the bonding wire 23 by using the bonding wire 23 , and the fluid colloid is disposed on the bonding wire 23 as a shed (Dam). The structure 24' is then coated with a transparent adhesive 25' on the sensing region 22a of the sensing wafer 22 to form a sensing semiconductor package W assembly that can be reduced in overall size. However, in the above-mentioned technology, the fluid colloid not only has high process cost and low product reliability, and thus cannot be widely used in the industry. Further, 'U.S. Patent Nos. 5,950, 074, 6,060,340, 6' 262' 479, 6,384,472, 6, 590, 269, 6'989'296 In the 'number', another sensing semiconductor package is disclosed. . Referring to FIG. 3A, the prior art is to form a barrier structure 34' on a substrate 31 to connect a sensing wafer 32 having a sensing region 32a to the substrate 6 110627 200929453 and to accommodate In the dam structure 34, and electrically connected by a bonding wire 33, the pad 32b of the sensing chip 32 and the substrate 31 are disposed, and a light transmitting body 35' is disposed on the dam structure 34 to cover the feeling. The wafer 32 is tested. Referring to FIG. 3B, a similar sensing semiconductor package is disclosed in U.S. Patent No. 6,545,332, the disclosure of which is incorporated herein by reference. The inter-colloid 36 is connected to the wafer holder 310a to have a sensing wafer 32, and the bonding pad 32b of the sensing wafer 32 is electrically connected to the lead 31b of the lead truss 31 by the bonding wire 33. Forming a contact structure on the lead 310b and surrounding the sensing die 32 and the bonding wire, and forming a second encapsulant by using a dispensing technique between the sensing die 32 and the dam structure 34. 37, and the covering portion is connected to the bonding wire 33 of the guiding pin 31, the wafer holder 310a and the guiding pin 310b, and finally a light transmitting body 35 is disposed on the dam structure 34 to cover the sensing chip 32. Or forming a dam structure 34 on the guide pedal, and then connecting the welding wire 33 of the sensing chip. In the above-mentioned technology, the main 疋 疋 疋 搁 及 及 及 及 及 及 及The sensing chip 32 prevents the light-transmitting body 35 from directly contacting the sensing wafer, so that the sensing chip 32 is favored; the plunging is less than u. However, there is a common problem in the prior art, that is, the overall size of the package is the size of the wafer, the space for the wire, and the width of the dam structure 34, and the area occupied by the 34 is the entire area. The rotten dam is configured to provide the dam structure 34, which is incapable of meeting the requirements of lightness and thinness of the package. 110627 7 200929453 • 4th, 4th, 4th, US Patent No. 6,995, 462 Revealing a helmet

-攔塌結構之感測式半導體封裝件，係提供-具凹槽41a之 基板41，於該凹槽41a内接置—具有感測區他之感測晶 L片42’並以銲線43電性連接該感測晶片42之銲墊4訃與 :該基板41’復以黏著層44將透光體㈣著於感測晶月U 上，且包覆部份連接於該銲塾42b之銲線43，以封住但不 接觸該感測晶片4 2 $ 7=¾丨r^· /1。 曰乃之感測區42a，再於該基板41之凹 ，中利用點膠技術以液態封裝化合物(LiquidM〇id ❹C卿刪d’ LMC)形成封裝膠體46，以藉由該封裝踢體铛 包覆連接於該基板41上方夕## ㈣π… 線43部分，同時外露該透 光體45，免去攔壩結構之製作。 惟如第4Β圖所示，該液態封裝化人物所报# 壯 體46與黏著層44間之姓人卜f化口物所形成之封裝膠 .、 、、'σ σ性不佳，易形成脫層46a = 時被封裝膠體a及點著 〇 =覆之銲線43受損而發生斷裂他，而使其成為不 因此，如何提供一種感測式半導 得以提高感測晶片之使用效率、 '、 、λ法， 流程、降低製作之料成本:止=積、簡化生產 中產生確為相關領域上所% 【發明内容】 ' 鑑於如述習知技術之缺失， -種可避免脫層之感測式半導體封裝x件及並二:係在提供 本發明之復—目的係在提供一種省略點膠製程之感剩 110627 200929453 式半導體封裝件及其製法。 種輕薄短小化之感測式 種簡化封裝製程之感測 本發明之又一目的係在提供一 半導體封褒件及其製法。 本發明之另一目的係在提供一 式半導體封裝件及其製法。 種可降低製造成本之感 本發明之再一目的係在提供一 測式半導體封裝件及其製法。 /為達上述目的，本發明揭示之感測式半導體封裝件， ❹係匕括、基板，具有感測區之感測晶片係接置於該基板 上，並以鲜線電性連接該基板與該感測晶片；黏著層，包 覆該感測晶片周緣及該銲線，且不接觸該感測晶片之感測 區以及透光體，係以該黏著層接置於該基板且封蓋該 該基板可為平面袼柵陣列基板(Land Gri“rray， lga)，該=著層高度係大於該銲線之線弧頂部至基板之距 ❹離’該黏者層係為遇熱具有低黏滯係數vis⑶^… 之材員，該黏著層於室溫下係為膠片狀之樹脂類材料；該 透光體係玻璃材質。 .^發明復提供-種感測式半導體封裝件之製法，係包 括.提供-基板’以於該基板上接置並以銲線電性連接一 具有感測區之感測晶片；製備一透光體，於該透光體形成 有黏著層，且該黏著層具有對應該感測區之開口；以及將 忒，光體藉由該黏著層接置於該基板且加熱該基板，使該 黏著層在接著於該基板時呈溶融狀態而包覆該感測晶片周 110627 9 200929453 •緣及該銲線整體’且外露該感測晶片之感測區，並於該黏 .著層固化後使該透光體封蓋該感測區。 本發明又提供一種感測式半導體封裝件之製法，係包 : 括··提供一呈批次狀之基板，以於該基板接置上並以銲線 電性連接複數具有感測區之感測晶片；製備複數透光體， 其中各該透光體形成有黏著層，且該黏著層具有對應該感 測區之開口 ·，將各該透光體藉由該黏著層接置於該基板且 加熱該基板，使該黏著層在接著於該基板時呈熔融狀態而 Ο包覆各該感測晶片周緣及該銲線整體，且外露各該感測晶 片之感測區，並於該黏著層固化後使各該透光體封蓋各該 感測區；以及進行切單作業，以形成複數感測式半導體封 裝件。 本發明復提供一種感測式半導體封裝件之製法，係包 括供一呈批次狀之基板，以於該基板上接置並以鋒線 電性連接複數具有感測區之感測晶片；製備一透光體，其 ❾中該透光體形成有黏著層，且該黏著層具有複數對應該感 測區之開口；將該透光體藉由該黏著層接置於該基板且加 熱該基板，使該黏著層在接著於該基板時呈熔融狀態而包 覆各該感測晶片周緣及該銲線整體，且外露各該感測晶片 之感測區，並於該黏著層固化後使該透光體封蓋各該咸測 區；以及進行切單作業，以形成複數感測式半導體封裝件。 另外，前述提供之製法中，該黏著層亦可形成有對應切單 作業時切割線位置之複數第二開口。 因此，本發明之感測式半導體封裝件及其製法中，係 Π0627 10 200929453 .將黏著層預設於透光體上，再將該設有黏著層之透光體接 ，置於基板上’且使該黏著層包覆感測晶#周緣及整條鲜 線，避免習知技術將黏著層設置於感测晶片之感測區與鲜 墊間，而可省去保留於兩者間之空隙，提高感測晶片之感 :測面積比率；且該封襄件之整體平面尺寸係僅包含該晶片 尺寸以及打線空間，節省了設置攔壩結構所佔用之面積， 以滿足封裝件輕薄短小之需求；另外，本發明復省去製作 攔壩結構、進行點膠製程以及形成多層封裝膠體，改以單 〇種膠體一次封裝’俾達簡化生產流程，節省製造所需時間 及成本，且可避免因多層膠體間脫層之情形，減少不良品 之產生，俾達提升產品製造良率之效。 【實施方式】 以下係藉由特定的具體實施例說明本發明之實施方 式’熟習此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。 Q差二^_實施例 請參閱第5A至5C圖，係為本發明之感測式半導體封 裝件及其製法第一實施例之剖視示意圖。 如第5A圖所示，提供一基板51，該基板51例如為平 面格栅陣列基板（Land Grid Array，LGA)，並於該基板51 上接置一具有感測區52a及銲墊52b之感測晶片52,復以 輝線53電性連接該銲墊52b與該基板51 ;以及製備一透 光體55(如玻璃板），其中該透光體55周緣形成有黏著層 54 **亥點著層5 4南度係大於該鲜線5 3線弧頂部至該某板 110627 11 200929453 51間之距離’其中該黏著層54於室溫下係為膠片狀之樹 .脂類材料，如環氧樹脂膠片（epoxy tape)，且該黏著層54 . 具有對應該感測區52a之開口 54a。 :如第5B圖所示，將該透光體55藉由該黏著層54接置 於感測晶片52且加熱該基板51，使該黏著層54在接著於 该基板5 1時呈低黏滯係數（10W v i SC0S i ty )之溶融狀態而 包覆該感測晶片5 2周緣及該鮮線5 3整體，且外露該感測 晶片52之感測區52a。 〇 如第5C圖所示’移除熱源後讓該黏著層54冷卻固化， 而使該透光體55封蓋該感測區52a，以形成一感測式半導 體封裝件5 0。 本發明復揭示一種感測式半導體封裝件5〇，係包括： 基板51 ;具有感測區52a及銲墊52b之感測晶片52,係接 置於該基板51上’並以銲線53電性連接該基板51與該感 測晶片52之銲墊52b ;黏著層54，係包覆該感測晶片52 ❹周緣及該銲線53整體，且不接觸該感測晶片52之感測區 52a ’以及透光體55，係以該黏著層54接置於該基板51， 且封蓋該感測區52a。 該基板51可為平面格柵陣列基板；該黏著層54高度 2大於該鮮線53之線弧頂部至該基板51間之距離；該黏 著層54例如杨氧樹脂膠片’在遇熱時具有低黏滯係數； 該透光體55係為破璃材質。 J二實施例 另吻 &gt; 閱第6A至6D圖，係為本發明之感測式半導體 12 110627 200929453 •封裝件之衣法第一貫施例之剖視不意圖。本實施例與第一 •實施例大致相同’主要差異係將複數感測晶片接置並電性 連接至呈批次（batch)狀之基板上，再於該基板上接置複數 ： 設有黏著層之透光體’並切割形成複數封裝件。 -： 如第6 A圖所示，提供一呈批次狀之基板61，該基板 61具有複數基板單元，以於該基板6丨上接置複數具有感 測區62a及銲墊62b之感測晶片62，並以銲線63電性連 接該銲墊62b與該基板61 ;以及製備複數透光體65,於各 ❹該透光體65形成有黏著層64’且該黏著層64具有對應該 感測區62a之開口 64a。 如第6B圖所示’將各該透光體65藉由該黏著層64 接置於該基板61且加熱該基板61，使該黏著層64在接著 於該基板61時呈低黏滯係數之熔融狀態而包覆各該感測 晶片62周緣及該銲線63整體，且外露各該感測晶片62 之感測區6 2 a。 0 如第6C圖所示’移除熱源後讓該黏著層64冷卻固化， 而使該透光體65封蓋該感測區62a。 如第6D圖所示，進行切單作業，以形成複數感測式半 導體封裝件6 0。 藉此，於批次狀之基板61上製作形成複數感測式半導 體封裝件60，以達量產及簡化製程之功效。 茗三實絲.你| 請參閱第7A至7D圖，係為本發明之感測式半導體封 裝件之製法第三實施例之剖視示意圖。本實施例與第一實 13 130627 200929453 •施例大致相同’主要差異係將複數感測晶片接置並電性連 .接至呈批次狀之基板上，再於該基板上接置設有黏著層之 整片式透光體，且該黏著層具有複數對應該感測晶片感測 區之開口。 如第7A圖所示’提供一呈批次狀之基板71，並於該 ’基板Ή接置複數具有感測區72a及銲墊72b之感測晶片 72 ’且以銲線73電性連接該感測晶片72之銲墊72b與該 基板71 ;同時製備一對應該批次基板71之整片式透光體 〇 75’於該透光體75形成有黏著層74,且該黏著層74具有 複數對應該感測區72a之開口 74a。 如第7B圖所示’將該透光體75藉由該黏著層74接置 於該基板71且加熱該基板71，使該黏著層74在接著於該 基板71時呈低黏滯係數之熔融狀態而包覆各該感測晶片 72周緣及該銲線73整體’且外露各該感測晶片72之感測 區 72a。 q 如第7C圖所示’移除熱源後讓該黏著層74冷卻固化， 而使該透光體75封蓋該感測區72a。 最後如第7D圖所示’進行切單作業，以形成複數感測 式半導體封裝件70。 藉此’利用批次狀之基板71及整片式透光體75之結 合與切單以製作複數感測式半導體封裝件70,進而達到量 產及簡化製程之功效。 第四實施你丨 請參閱第8A至8D圖’係為本發明之感測式半導體封 14 110627 200929453 •裝件之製法第四貫施例之剖視不意圖。 . 本貫施例與第一實施例大致相同，主要差異係將複數 .具有感測區82a之感測晶片82接置並電性連接至呈批次狀 之基板81上，再於該基板81上接置設有黏著層84之透光 了體85’且該黏著層84具有對應該感測晶片82之感測區82a 之開口 84a ’以及對應切單作業時切割線之複數第二開口 84b ’以節省該黏著層84之使用材料。 因此，本發明之感測式半導體封裝件及其製法中，係 〇將黏著層預設於透光體上，再將該設有黏著層之透光體接 置於基板上，且使該黏著層包覆感測晶片周緣及整條銲 線，避免習知技術將黏著層設置於感測晶片之感測區與銲 塾間，而可省去保留於兩者間之空隙，提高感測晶片之感 測面積比率；且該封裝件之整體平面尺寸係僅包含該晶片 尺寸以及打線空間，節省了設置攔壩結構所佔用之面積， 以滿足封裝件㈣短小之需求；另外’省去製作棚塌結構、 ❹進行點膠製程以及形成多層封裝膠體，改以單種膠體一次 封裝’俾達簡化生產流程，節省製造所需時間及成本，且 可避免因多層膠體間脫層之情形，減少不良品之產生，俾 達提升產品製造良率之效。 上述實施例僅例示性說明本發明之原理及其功效，而 非用於限制本發明，任何熟習此項技藝之人士均可在 背本發明之精神及_下’對上述實施例進行修飾與改 ，因此本發明之權利保護範圍，應如後述之中請專利 110627 200929453 ，【圖式簡單說明】 • 第1圖係為美國專利第5, 534, 725號所揭露之感測式 .半導體封裝件剖面示意圖； 第2圖係為美國專利第5, 962, 81 0號案所揭露之感測 式半導體封裝件剖面示意圖； 第3A圖係為習知感測式半導體封裝件剖面示意圖； 第3B圖係為美國專利第6, 545, 332號案所揭露之習知 感測式半導體封裝件剖面示意圖； D 第4A圖係為美國專利第6,995,462號案所揭露之習知 感測式半導體封裝件剖面示意圖； 第4B圖係為第4A圖之局部放大圖，表示多層膠體間 之脫層現象； / θ 第5Α至5C圖係為本發明之感測式半導體封裝件第一 實施例之刮視示意圖； 第6Α至6D圖係為本發明之感測式半導體封裝件第一 @實施例之剖視示意圖； 一 第7Α至7D圖係為本發明之感測式半導體封裝件第二 實施例之剖視示意圖；以及 ' 二 弟8Α至8D圖係為本發明之感測式半導體封聲件第 實施例之剖視示意圖。 四 【主要元件符號說明】 U，310 導線架 11a， 310a 晶片座 lib, 310b 導腳 110627 16 200929453 9 12, 22, 32, 42 感測晶片 12a, 22a, 32a, 42a 感測區 12b, 22b, 32b, 42b 銲墊 13, 23, 33, 43 銲線 14, 44 黏著層 - 15, 35, 45 透光體 16 封裝膠體 21, 31 基板 Ο 24 攔壩結構 25 透明膠 34 攔壩結構 36 第一封裝膠體 37 第二封裝膠體 41 基板 41a 凹槽 ο 43a 銲線斷裂 46 封裝膠體 46a 脫層 50, 60, 70 感測式半導體封裝件 51, 61, 71, 81 基板 52, 62, 72, 82 感測晶片 52a, 62a, 72a, 82a 感測區 52b, 62b, 72b 銲墊 53, 63, 73 銲線 17 110627 200929453 54, 64, 74, 84 f 54a, 64a, 74a, 84a 55, 65, 75, 85 84b 黏著層 開口 透光體 第二開口The sensing semiconductor package of the collapse structure is provided with a substrate 41 having a recess 41a, which is connected in the recess 41a - has a sensing region of the sensing crystal L piece 42' and is bonded to the wire 43 The bonding pad 4 is electrically connected to the sensing pad 42 and the substrate 41' is coated with the adhesive layer 44 to expose the transparent body (4) to the sensing crystal U, and the covering portion is connected to the bonding pad 42b. The bonding wire 43 is sealed to but not in contact with the sensing wafer 4 2 $ 7=3⁄4丨r^· /1. The sensing area 42a of the enamel is further formed in the concave portion of the substrate 41 by using a dispensing technique to form a package colloid 46 with a liquid encapsulating compound (LiquidM〇id ❹Cqing dd' LMC) for kicking the package by the package The cover is connected to the upper portion of the substrate 41. The ## (4) π... line 43 portion is exposed at the same time, and the light-transmissive body 45 is exposed, thereby eliminating the fabrication of the dam structure. However, as shown in Figure 4, the encapsulating glue formed by the liquid encapsulating person reported that the surname of the person between the body and the adhesive layer 44 is not good, and is easy to form. When the delamination 46a = is damaged by the encapsulating colloid a and the bonding wire 43 which is damaged by the encapsulation a, it is not caused, how to provide a sensing type semi-conducting to improve the use efficiency of the sensing wafer, ', λ method, process, reduce the cost of production materials: stop = product, simplify production, it is indeed in the relevant field% [invention content] 'In view of the lack of the prior art, the species can avoid delamination The sensing semiconductor package x and the second aspect of the present invention provide a method for omitting the dispensing process of the 110627 200929453 type semiconductor package and the method of manufacturing the same. Sensing of Lightweight and Thinning Sensing of Simplified Packaging Process Another object of the present invention is to provide a semiconductor package and a method of fabricating the same. Another object of the present invention is to provide a semiconductor package and a method of fabricating the same. A Sense of Reducing Manufacturing Costs A further object of the present invention is to provide a test semiconductor package and a method of fabricating the same. In order to achieve the above objective, the sensing semiconductor package disclosed in the present invention is a substrate, a sensing chip having a sensing region is attached to the substrate, and the substrate is electrically connected with a fresh wire. The sensing wafer; an adhesive layer covering the periphery of the sensing wafer and the bonding wire, and not contacting the sensing region of the sensing wafer and the light transmitting body, the adhesive layer is attached to the substrate and the cover is covered The substrate may be a planar grid array substrate (Land Gri "rray, lga", the landing height is greater than the line arc top of the bonding wire to the substrate distance away from the 'the adhesive layer is low heat when exposed to heat The material of the viscous coefficient vis(3)^..., the adhesive layer is a film-like resin material at room temperature; the light-transmissive system glass material. The invention provides a method for manufacturing a sensing semiconductor package, including Providing a substrate for mounting on the substrate and electrically connecting a sensing wafer having a sensing region to the bonding wire; preparing a light transmissive body, the adhesive layer is formed with an adhesive layer, and the adhesive layer has Corresponding to the opening of the sensing area; and placing the light body by the adhesive layer Substrate and heating the substrate, so that the adhesive layer is in a molten state after the substrate is coated to cover the sensing wafer periphery 110627 9 200929453 • the edge and the bonding wire as a whole and expose the sensing region of the sensing wafer, and After the adhesive layer is cured, the light-transmitting body covers the sensing area. The invention further provides a method for manufacturing a sensing semiconductor package, the package includes: providing a batch-shaped substrate, A plurality of sensing wafers having a sensing region are electrically connected to the substrate and electrically connected to the bonding wires; and the plurality of transparent bodies are formed, wherein each of the transparent bodies is formed with an adhesive layer, and the adhesive layer has a corresponding sensing region Opening, each of the light-transmitting bodies is placed on the substrate by the adhesive layer and the substrate is heated, so that the adhesive layer is molten in a state of being attached to the substrate, and the periphery of each of the sensing wafers is covered The wire is integrally formed, and the sensing regions of the sensing wafers are exposed, and after the bonding layer is cured, each of the transparent bodies covers the sensing regions; and the singulation operation is performed to form a complex sensing semiconductor Package. The invention provides a sensing type semi-conductive The method for manufacturing a package comprises: providing a substrate in a batch form for attaching to the substrate and electrically connecting the plurality of sensing wafers having the sensing regions with a front line; preparing a transparent body, wherein the transparent body is transparent The light body is formed with an adhesive layer, and the adhesive layer has a plurality of openings corresponding to the sensing regions; the light transmitting body is attached to the substrate by the adhesive layer and the substrate is heated, so that the adhesive layer is followed by the substrate Forming a molten state to cover the periphery of each of the sensing wafers and the entire bonding wire, and exposing the sensing regions of the sensing wafers, and after the adhesive layer is cured, the transparent body covers each of the sensing regions And performing a singulation operation to form a complex sensing semiconductor package. In addition, in the above-prepared manufacturing method, the adhesive layer may also be formed with a plurality of second openings corresponding to the position of the cutting line during the singulation operation. In the sensing semiconductor package and the manufacturing method thereof, the system is Π0627 10 200929453. The adhesive layer is preset on the light-transmitting body, and the light-transmitting body provided with the adhesive layer is placed on the substrate, and the adhesive is adhered Layer coated sensing crystal #周缘 and whole strip Wire, avoiding the conventional technique of disposing the adhesive layer between the sensing area of the sensing wafer and the fresh pad, and eliminating the gap remaining between the two, improving the sense of the sensing wafer: measuring the area ratio; and the sealing The overall planar size of the device only includes the size of the wafer and the wire-bonding space, which saves the area occupied by the dam structure to meet the requirements of lightness and thinness of the package; in addition, the present invention saves the dam structure and dispenses. The process and the formation of a multi-layer encapsulant are replaced by a single-ply colloid package. The process is simplified, the time and cost of manufacturing are saved, and the delamination between the layers of colloids can be avoided, and the generation of defective products can be avoided. Improve product manufacturing yield. [Embodiment] The following embodiments of the present invention are described by way of specific embodiments. Those skilled in the art can readily appreciate the advantages and advantages of the present invention from the disclosure herein. </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; As shown in FIG. 5A, a substrate 51 is provided. The substrate 51 is, for example, a Land Grid Array (LGA), and a sense of the sensing region 52a and the pad 52b is attached to the substrate 51. The measuring chip 52 is electrically connected to the bonding pad 52b and the substrate 51 by a glow line 53; and a transparent body 55 (such as a glass plate) is prepared, wherein the transparent body 55 is formed with an adhesive layer 54 at the periphery thereof. The layer 5 4 is more than the distance from the top of the 5 3 line arc of the fresh line to the distance between the board 110627 11 200929453 51. The adhesive layer 54 is a film-like tree at room temperature. A lipid material such as epoxy An epoxy tape, and the adhesive layer 54 has an opening 54a corresponding to the sensing region 52a. As shown in FIG. 5B, the light-transmissive body 55 is placed on the sensing wafer 52 by the adhesive layer 54 and the substrate 51 is heated, so that the adhesive layer 54 is low-viscosed when it is next to the substrate 51. The periphery of the sensing wafer 5 2 and the entire fresh line 53 are covered by the melting state of the coefficient (10W vi SC0S ty ), and the sensing region 52a of the sensing wafer 52 is exposed. ’ As shown in FIG. 5C, after the heat source is removed, the adhesive layer 54 is cooled and solidified, and the light transmitting body 55 covers the sensing region 52a to form a sensing semiconductor package 50. The present invention discloses a sensing semiconductor package 5A, comprising: a substrate 51; a sensing wafer 52 having a sensing region 52a and a pad 52b, which is attached to the substrate 51 and electrically connected by a bonding wire 53 The substrate 51 and the pad 52b of the sensing wafer 52 are connected to each other; the adhesive layer 54 covers the periphery of the sensing wafer 52 and the bonding wire 53 and does not contact the sensing region 52a of the sensing wafer 52. And the light transmissive body 55 is attached to the substrate 51 with the adhesive layer 54 and covers the sensing region 52a. The substrate 51 may be a planar grid array substrate; the height of the adhesive layer 54 is greater than the distance between the top of the line arc of the fresh line 53 and the substrate 51; the adhesive layer 54 such as cation resin film has a low heat when it is heated. Viscosity coefficient; The light transmitting body 55 is made of a glass material. J. Second Embodiment Another Kiss &gt; Read Figures 6A to 6D, which are the sensing semiconductors of the present invention. 12 110627 200929453 • The first embodiment of the package is not intended. This embodiment is substantially the same as the first embodiment. The main difference is that the plurality of sensing wafers are connected and electrically connected to a batch-shaped substrate, and then the substrate is connected to a plurality of substrates: The light transmissive body of the layer is cut and formed into a plurality of packages. -: as shown in FIG. 6A, a batch-shaped substrate 61 is provided, the substrate 61 having a plurality of substrate units for sensing a plurality of sensing regions 62a and pads 62b on the substrate 6 The wafer 62 is electrically connected to the bonding pad 62b and the substrate 61 by a bonding wire 63; and a plurality of transparent transparent bodies 65 are formed, and an adhesive layer 64' is formed on each of the transparent transparent bodies 65 and the adhesive layer 64 has a corresponding The opening 64a of the sensing region 62a. As shown in FIG. 6B, each of the light-transmissive bodies 65 is placed on the substrate 61 by the adhesive layer 64 and the substrate 61 is heated, so that the adhesive layer 64 has a low viscosity coefficient when it is followed by the substrate 61. The periphery of each of the sensing wafers 62 and the entire bonding wires 63 are covered in a molten state, and the sensing regions 6 2 a of the sensing wafers 62 are exposed. 0, as shown in Fig. 6C, the adhesive layer 64 is cooled and solidified after the heat source is removed, and the light transmissive body 65 covers the sensing region 62a. As shown in Fig. 6D, a singulation operation is performed to form a complex sensing type semiconductor package 60. Thereby, a plurality of sensing type semiconductor packages 60 are formed on the batch substrate 61 to achieve mass production and to simplify the process.茗三丝丝. You | Please refer to Figures 7A to 7D, which are schematic cross-sectional views showing a third embodiment of the method of manufacturing the sensing semiconductor package of the present invention. This embodiment is substantially the same as the first embodiment 13 130627 200929453. The main difference is that the plurality of sensing wafers are connected and electrically connected to a batch-shaped substrate, and then placed on the substrate. The entire thickness of the adhesive layer of the adhesive layer, and the adhesive layer has a plurality of openings corresponding to the sensing area of the wafer. As shown in FIG. 7A, a batch-shaped substrate 71 is provided, and a plurality of sensing wafers 72' having sensing regions 72a and pads 72b are electrically connected to the substrate substrate and electrically connected by bonding wires 73. The solder pad 72b of the wafer 72 is sensed and the substrate 71; and a whole-piece light-transmissive body 75' of the pair of substrates 71 is prepared at the same time. The light-transmissive body 75 is formed with an adhesive layer 74, and the adhesive layer 74 has The plurality corresponds to the opening 74a of the sensing region 72a. As shown in FIG. 7B, the light-transmissive body 75 is attached to the substrate 71 by the adhesive layer 74 and the substrate 71 is heated, so that the adhesive layer 74 is melted with a low viscosity coefficient when it is next to the substrate 71. The periphery of each of the sensing wafers 72 and the bonding wires 73 are integrally covered and exposed to the sensing regions 72a of the sensing wafers 72. q As shown in Fig. 7C, after the heat source is removed, the adhesive layer 74 is cooled and solidified, and the light transmissive body 75 covers the sensing region 72a. Finally, a singulation operation is performed as shown in Fig. 7D to form a complex-sensing semiconductor package 70. Thereby, the combination of the batch-shaped substrate 71 and the one-piece translucent body 75 is used to form a plurality of sensing semiconductor packages 70, thereby achieving mass production and simplification of the process. Fourth Embodiment You Please refer to Figures 8A to 8D for the sensing semiconductor package of the present invention. 14 110627 200929453 • The fourth embodiment of the method of manufacturing is not intended. The present embodiment is substantially the same as the first embodiment, and the main difference is that the plurality of sensing wafers 82 having the sensing regions 82a are connected and electrically connected to the substrate 81 in the form of a batch, and then the substrate 81 is attached. The light-transmissive body 85' having the adhesive layer 84 is disposed thereon, and the adhesive layer 84 has an opening 84a' corresponding to the sensing region 82a of the sensing wafer 82 and a plurality of second openings 84b corresponding to the cutting line during the singulation operation. 'To save the material used for the adhesive layer 84. Therefore, in the sensing semiconductor package of the present invention and the method of manufacturing the same, the adhesive layer is preset on the light-transmitting body, and the light-transmitting body provided with the adhesive layer is placed on the substrate, and the adhesive is adhered The layer covers the periphery of the sensing wafer and the entire bonding wire, so as to avoid the prior art, the adhesive layer is disposed between the sensing area of the sensing wafer and the soldering pad, and the gap between the two can be omitted, and the sensing chip can be improved. Sensing area ratio; and the overall planar size of the package includes only the size of the wafer and the wiring space, saving the area occupied by the dam structure to meet the short requirements of the package (4); The collapse structure, the sputum dispensing process and the formation of multi-layer encapsulation colloids are replaced by a single colloid package. The simplification of the production process saves the time and cost of manufacturing, and avoids the delamination between the layers of colloids. The production of good products, the company to improve the efficiency of product manufacturing. The above-described embodiments are merely illustrative of the principles of the present invention and its effects, and are not intended to limit the present invention, and those skilled in the art can modify and modify the above embodiments in the spirit of the present invention. Therefore, the scope of protection of the present invention should be as described in the following patent 110627 200929453, [Simplified Description] Figure 1 is a sensing type disclosed in U.S. Patent No. 5,534,725. FIG. 2 is a schematic cross-sectional view of a sensing semiconductor package disclosed in US Pat. No. 5,962,810; FIG. 3A is a schematic cross-sectional view of a conventional sensing semiconductor package; FIG. FIG. 4A is a cross-sectional view of a conventional sensing semiconductor package disclosed in U.S. Patent No. 6,545,332; Fig. 4B is a partial enlarged view of Fig. 4A showing the delamination between the layers of the colloid; / θ 5th to 5C are the shaving of the first embodiment of the sensing semiconductor package of the present invention. Figure 6 is a cross-sectional view of a first embodiment of a sensing semiconductor package of the present invention; a seventh through 7D is a second embodiment of the sensing semiconductor package of the present invention A schematic cross-sectional view; and a 'secondary 8' to 8D figure is a schematic cross-sectional view of a first embodiment of a sensing semiconductor sound-sounding member of the present invention. 4. [Main component symbol description] U, 310 lead frame 11a, 310a wafer holder lib, 310b lead 110627 16 200929453 9 12, 22, 32, 42 sensing wafer 12a, 22a, 32a, 42a sensing area 12b, 22b, 32b, 42b pads 13, 23, 33, 43 bonding wires 14, 44 adhesive layer - 15, 35, 45 light transmitting body 16 encapsulant 21, 31 substrate Ο 24 dam structure 25 transparent plastic 34 dam structure 36 first Encapsulant 37 Second encapsulant 41 Substrate 41a Groove ο 43a Wire break 46 Encapsulant 46a Debond 50, 60, 70 Sense semiconductor package 51, 61, 71, 81 Substrate 52, 62, 72, 82 Measuring wafers 52a, 62a, 72a, 82a sensing regions 52b, 62b, 72b pads 53, 63, 73 bonding wires 17 110627 200929453 54, 64, 74, 84 f 54a, 64a, 74a, 84a 55, 65, 75, 85 84b Adhesive layer open transmissive body second opening

18 11062718 110627

Claims (1)

200929453 .十、申請專利範圍： • 1. 一種感測式半導體封裝件，係包括： . 基板； :具有感測區之感測晶片，係接置於該基板上，且以 : 銲線電性連接該感測晶片及基板； 黏者層’包覆該感測晶片周緣及該鲜線，且不接觸 該感測晶片之感測區；以及 透光體’係猎由該黏著層而設於該基板，並封蓋該 〇 感測區。 2.如申請專利範圍第1項之感測式半導體封裝件，其中， 該透光體為玻璃材質。 3·如申請專利範圍第1項之感測式半導體封裝件，其中， 該黏著層高度大於該銲線之線弧頂部至該基板之距離。 4. 如申请專利範圍第1項之感測式半導體封裝件，其中， 該黏著層為遇熱具有低黏滯係數（1〇w visc〇sity)之材 〇 貝 5. 如申请專利範圍第4項之感測式半導體封裝件，其中， 該黏著層為環氧樹脂膠片。 6· —種感測式半導體封裝件之製法，係包括： 提供一基板，並將具有感測區之感測晶片接置於該 基板上，且以銲線電性連接該感測晶片及該基板； 製備一透光體，並於該透光體上形成有黏著層，且 該黏著層具有對應該感測區之開口；以及 將該透光體藉由該黏著層接置於該基板，使該黏著 110627 19 200929453 • 層包覆該感測晶片周緣及該銲線，且藉由該開口以外露 , 該感測晶片之感測區，以使該透光體封蓋該感測區。 7. 如申請專利範圍第6項之感測式半導體封裝件之製 法，其中，該透光體為玻璃材質。 8. 如申請專利範圍第6項之感測式半導體封裝件之製 法，其中’該黏著層高度大於該輝線之線弧頂部至該基 板之距離。 9. 如申請專利範圍第6項之感測式半導體封裝件之製 ❹ 法，其中，該黏著層為遇熱具有低黏滞係數之材質。 10. 如申請專利範圍第9項之感測式半導體封裝件之製 法’其中，該黏著層為環氧樹脂膠片。 11. 如申請專利範圍第6項之感測式半導體封裝件之製 法，其中，該透光體藉由該黏著層接置於該基板時，經 由加熱該基板，使該黏著層在接著於該基板時呈低黏滞 係數之溶融狀態而包覆該感測晶片周緣及該銲線，且外 Q 露該感測晶片之感測區，並於移除熱源後讓該黏著層冷 卻固化’而使該透光體封蓋該感測區。 12. —種感測式半導體封裝件之製法，係包括： 、提供一呈批次狀之基板，並將複數具有感測區之感 測晶片接置於該基板上，m線電性連接該感測晶片 與該基板； 製備複數透光體，於各該透光體上形成有黏著層， 且該黏著層具有對應該感測區之開口； 將該些透光體藉由該黏著層接置於該基板，使各該 110627 20 200929453 * 黏者層包覆各該感測晶片周緣及該鲜線，且藉由該開口 外露該感測晶片之感測區’以使各該透光體封蓋各該感 測區；以及 進行切單作業，以形成複數感測式半導體封裝件。 13. 如申請專利範圍第12項之感測式半導體封裝件之製 法’其中，該透光體為玻璃材質。 14. 如申請專利範圍第12項之感測式半導體封裝件之製 法，其中，該黏著層高度大於該銲線之線弧頂部至基板 © 之距離。 15. 如申請專利範圍第12項之感測式半導體封裝件之製 法’其中’該黏著層為遇熱具有低黏滞係數之材質。 16. 如申請專利範圍第15項之感測式半導體封裝件之製 法’其中’該黏著層為環氧樹脂膠片。 17. 如申請專利範圍第12項之感測式半導體封裝件之製 法，其中，該透光體藉由該黏著層接置於該基板時，= 〇 由加熱該基板，使該黏著層在接著於該基板時呈低黏滯 係數之熔融狀態而包覆該感測晶片周緣及該銲線，且外 露該感測晶片之感測區，並於移除熱源後讓該黏著層冷 卻固化’而使該透光體封蓋該感測區。 18·—種感測式半導體封裝件之製法，係包括： 提供一呈批次狀之基板，並將複數具有感測區之感 測晶片接置於該基板上’且以銲線電性連接該感測晶片 與該基板； 製備一整片式透光體，於該透光體形成有黏著層， 110627 21 200929453 • 且該黏著層具有複數對應該感測區之開口； . 將該透光體藉由該黏著層接置於該基板，並使該黏 著層包覆該感測晶片周緣及該銲線，且藉由各該開口外 露各該感測晶片之感測區，而使該透光體封蓋該感測 區；以及 進行切單作業，以形成複數感測式半導體封裝件。 19.如申請專利範圍第18項之感測式半導體封裝件之製 法，其中，該透光體為玻璃材質。 〇 20.如申請專利範圍第18項之感測式半導體封裝件之製 法，其中，該黏著層高度大於該銲線之線弧頂部至基板 之距離。 21. 如申請專利範圍第18項之感測式半導體封裝件之製 法’其中’該黏著層為遇熱具有低黏滯係數之材質。 22. 如申請專利範圍第21項之感測式半導體封裝件之製 法’其中’該黏著層為環氧樹脂膠片。 ❹23.如申請專利範圍第ι8項之感測式半導體封裝件之製 法，其中，該透光體藉由該黏著層接置於該基板時，經 由加熱該基板，使該黏著層在接著於該基板時呈低黏滞 係數之熔融狀態而包覆該感測晶片周緣及該銲線，且外 露該感測晶片之感測區，並於移除熱源後讓該黏著層冷 卻固化’而使該透光體封蓋該感測區。 24.如申請專利範圍第18項之感測式半導體封裝件之製 法，其中，該黏著層復具有對應切單作業之切割線之複 數第二開口。 110627 22200929453. X. Patent Application Range: • 1. A sensing semiconductor package comprising: a substrate; a sensing wafer having a sensing region, which is attached to the substrate, and: wire bonding electrical Connecting the sensing wafer and the substrate; the adhesive layer 'covers the periphery of the sensing wafer and the fresh line, and does not contact the sensing area of the sensing wafer; and the transparent body' is set by the adhesive layer The substrate covers the 〇 sensing area. 2. The sensing semiconductor package of claim 1, wherein the light transmitting body is made of glass. 3. The sensing semiconductor package of claim 1, wherein the adhesive layer has a height greater than a distance from a top of the wire arc of the bonding wire to the substrate. 4. The sensing semiconductor package of claim 1, wherein the adhesive layer is a mussel having a low viscosity coefficient (1〇w visc〇sity) when heated. 5. The sensing semiconductor package of the item, wherein the adhesive layer is an epoxy film. The method for manufacturing a sensing semiconductor package comprises: providing a substrate, and tying a sensing wafer having a sensing region to the substrate, and electrically connecting the sensing wafer with a bonding wire and the a light-transmissive body, and an adhesive layer is formed on the light-transmitting body, and the adhesive layer has an opening corresponding to the sensing region; and the light-transmitting body is placed on the substrate by the adhesive layer, The adhesion 110627 19 200929453 • the layer covers the periphery of the sensing wafer and the bonding wire, and by exposing the opening, the sensing area of the sensing chip is such that the transparent body covers the sensing area. 7. The method of claim 4, wherein the light transmissive body is made of glass. 8. The method of claim 4, wherein the adhesive layer height is greater than a distance from a top of the line arc of the glow line to the substrate. 9. The method of claim 4, wherein the adhesive layer is a material having a low viscosity coefficient when exposed to heat. 10. The method of claim semiconductor package of claim 9, wherein the adhesive layer is an epoxy film. 11. The method of claim 6, wherein the transparent body is heated by the substrate by the adhesive layer, and the adhesive layer is followed by The substrate is in a molten state with a low viscosity coefficient to cover the periphery of the sensing wafer and the bonding wire, and the external Q exposes the sensing region of the sensing wafer, and the adhesive layer is cooled and solidified after removing the heat source. The light transmissive body covers the sensing area. 12. A method of fabricating a sensing semiconductor package, comprising: providing a substrate in a batch shape, and locating a plurality of sensing wafers having a sensing region on the substrate, and electrically connecting the wires to the substrate Sensing the wafer and the substrate; preparing a plurality of transparent bodies, forming an adhesive layer on each of the transparent bodies, and the adhesive layer has openings corresponding to the sensing regions; and the light-transmitting bodies are connected by the adhesive layer Placed on the substrate such that each of the 110627 20 200929453* adhesive layers covers the periphery of the sensing wafer and the fresh line, and the sensing area of the sensing wafer is exposed by the opening to make the transparent body Capping each of the sensing regions; and performing a singulation operation to form a complex sensing semiconductor package. 13. The method of claim 4, wherein the light transmissive body is made of glass. 14. The method of claim 4, wherein the adhesive layer has a height greater than a distance from a top of the wire arc of the bond wire to the substrate ©. 15. The method of claim 4, wherein the adhesive layer is a material having a low viscosity coefficient when exposed to heat. 16. The method of claim semiconductor package of claim 15 wherein the adhesive layer is an epoxy film. 17. The method of claim 12, wherein the transparent body is attached to the substrate by the adhesive layer, and the substrate is heated to cause the adhesive layer to follow. Coating the periphery of the sensing wafer and the bonding wire in a molten state with a low viscosity coefficient on the substrate, and exposing the sensing region of the sensing wafer, and allowing the adhesive layer to cool and solidify after removing the heat source. The light transmissive body covers the sensing area. 18. A method of fabricating a sensing semiconductor package, comprising: providing a substrate in a batch and attaching a plurality of sensing wafers having sensing regions to the substrate and electrically connecting the wires The sensing wafer and the substrate; preparing a whole piece of light transmissive body, the adhesive layer is formed with an adhesive layer, 110627 21 200929453 • and the adhesive layer has a plurality of openings corresponding to the sensing area; The body is attached to the substrate by the adhesive layer, and the adhesive layer covers the periphery of the sensing wafer and the bonding wire, and the sensing regions of the sensing wafers are exposed by the openings, so that the transparent layer is exposed The light body covers the sensing region; and performs a singulation operation to form a complex sensing semiconductor package. 19. The method of claim semiconductor package of claim 18, wherein the light transmissive body is made of glass. 。 20. The method of claim 7, wherein the adhesive layer has a height greater than a distance from a top of the wire arc of the bond wire to the substrate. 21. The method of claim semiconductor package of claim 18, wherein the adhesive layer is a material having a low viscosity coefficient when exposed to heat. 22. The method of claim semiconductor package of claim 21, wherein the adhesive layer is an epoxy film. The method of claim 4, wherein the transparent body is attached to the substrate by the adhesive layer, and the substrate is heated to cause the adhesive layer to follow The substrate is in a molten state with a low viscosity coefficient to cover the periphery of the sensing wafer and the bonding wire, and the sensing region of the sensing wafer is exposed, and the adhesive layer is cooled and solidified after the heat source is removed. The light transmissive body covers the sensing area. 24. The method of claim semiconductor package of claim 18, wherein the adhesive layer has a plurality of second openings corresponding to the dicing lines. 110627 22
TW096150714A 2007-12-28 2007-12-28 Sensor semiconductor package and method thereof TWI359481B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110581111A (en) * 2018-06-11 2019-12-17 海华科技股份有限公司 support, optical assembly and optical module
EP3982412A1 (en) * 2020-10-08 2022-04-13 Samsung Electronics Co., Ltd. Image sensor package and method of fabricating the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110581111A (en) * 2018-06-11 2019-12-17 海华科技股份有限公司 support, optical assembly and optical module
EP3982412A1 (en) * 2020-10-08 2022-04-13 Samsung Electronics Co., Ltd. Image sensor package and method of fabricating the same

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