TWI303474B - A wafer and a die having an integrated circuit and a layer of diamond - Google Patents

A wafer and a die having an integrated circuit and a layer of diamond Download PDF

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Publication number
TWI303474B
TWI303474B TW096143145A TW96143145A TWI303474B TW I303474 B TWI303474 B TW I303474B TW 096143145 A TW096143145 A TW 096143145A TW 96143145 A TW96143145 A TW 96143145A TW I303474 B TWI303474 B TW I303474B
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Taiwan
Prior art keywords
layer
wafer
single crystal
semiconductor material
forming
Prior art date
Application number
TW096143145A
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English (en)
Other versions
TW200822325A (en
Inventor
M Chrysler Gregory
A Watwe Abhay
Agraharam Sairam
V Ravi Kramadhati
Michael Garner C
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Intel Corp
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Publication of TW200822325A publication Critical patent/TW200822325A/zh
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Publication of TWI303474B publication Critical patent/TWI303474B/zh

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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

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1303474 九、發明說明： 【發明所屬之技術領域】 片 片 本發明係關於-種製造一組合晶圓、出自該晶圓之裸晶 、以及-包括該裸晶片之電子總成之方法，其中該裸晶 具有一用於導熱之鑽石層。 【先前技術】 積體電路-般係形成於石夕晶圓上，晶圓係接著切成獨立
的裸晶片《然後，每個裸晶片皆具有該矽晶圓之一部分， 其中積體電路係分別形成於該矽晶圓之一部分上。電子俨 號可輸入或輸出該積體電路。積體電路之運作會使積體電 路本身發熱且積體電路溫度的上升會破壞積^路本身。 積體電路上所有點之溫度因而應該維持低於一特定之最大 溫度。積體電路之運作並不均勾，致使積體電路上之某些 點產生的熱較其它點多，因而產生"熱點，、若沒有該等熱 點’有可能在提升裸晶片之平均功率消耗的同時維持期望 之積體電路溫度，因而可使積體電路之運作頻率更高。 【實施方式】 @ 第一、第二、和第三製程係分別關於圖la_g、圖2a· 。矛圖3 a j而作S兒明，藉以在每一個實例中製造一晶 圓、-出自該晶圓之裸晶片、以及一包括該裸晶片之電子 總成。該裸晶片具有一鑽石f，該鑽石層之主要功用在於 散佈出自-位於裸晶片中之積體電路之熱點之熱量。 在第-製程中’形成—較厚之層，該較厚之層散佈較多 的.’、、里然而，第一製程利用一種較為繁瑣之礙磨運作。 126326.doc 1303474 特定之雷射切割運作係用於切穿該鑽 因為鑽石層較厚 石層。 在第二製程中，排除第—製程之㈣運作並用—剪切運 作予以取代。—厚鑽石層亦形成於第二製程中’具有相關 之優點及缺點。 在第三製程中，一剪切運作亦用於排除一碾磨運作，作 -更易於切割之薄鑽石層係用一傳統鑛割法予以形成。該 薄鐵石層亦藉由一犧牲性多晶石夕晶圓予以被覆以致一組合 性晶圓係作成具㈣上表面切下表面。該組合性晶圓可 更為"透明地，，用於傳統之機械法中以處理傳統之石夕晶圓。 犧牲性多晶石夕晶圓同時提供薄鑽石層所欠缺之結構性支 撐。 在製造一厚鑽石層時利用一種碾磨運作 附圖中之圖la描緣-單晶（單一晶體）石夕晶圓1〇,宜中一 =鑽石層12係沉積於該單晶上。單_晶圓係根 據已知製程予以製造。—長薄垂直之單晶㈣（_種半導 =料）係垂直向下插人-料床（bath Qf suie。小該芯係 接者予n直向上拉出該浴床。1晶石夕在被拉出浴床的同 時>儿積在芯上，致使-單晶料塊因而形成具有—大於芯 直徑之直徑。目前’此種轉壤之直捏約3〇〇董米且其高度 為直徑之倍數。鑄塊接著係錄割成許多晶圓。由一鑄塊所 錄割出來之晶圓最好具有約750微米之厚度1晶石夕晶圓 1〇因而具有約300釐米之直徑及約750微米之厚度。 厚鑽石層12係利用化學氣相鑽石沉積_)技術予以 126326.doc 1303474 沉積。單晶石夕曰曰曰圓10係置於CVDD室中並予以加熱至例如 、勺1000 c之較南溫度。接著將彼此反應而形成鑽石之玻璃 π入该室中。鑽石接著由玻璃沉積至單晶矽晶圓10之整個 上表面上。》儿積在單晶矽晶圓i 0上之鑽石係熱導率約1000 W/mK且附著至單晶石夕晶圓i〇上表面之固態多晶鑽石。此 製私持績進行直到厚鑽石層12的厚度約介於微米與 祕米之間。所產生之厚鑽石層12因而具有3 〇〇釐米之直 徑。接著自CVDD室移出圖1&之組合晶圓並予以冷卻。多 晶鑽石沉積之進一步觀點在本技藝係已知且不在此詳述。 如圖lb所示，接著將圖“之組合晶圓翻轉以使單晶矽晶 圓10位於上方。接著將厚鑽石層12置於碾磨機器之表面 上。一碾磨機器之碾磨頭接著向下碾磨單晶矽晶圓丨〇。 圖1C描繪將單晶矽圓1〇向下碾磨之後的組合晶圓。單晶 矽晶圓10之厚度一般介於10至25微米之間。接著自碾磨機 器移出示於圖lc之組合晶圓。由於厚鑽石層12之厚度介於 300至500微米之間，故組合晶圓在移出碾磨機器及後續之 搬動（handle)時並未毀損。厚鑽石層12因而對較薄之單晶 矽晶圓10提供結構性支揮。單晶矽晶圓丨〇之上表面接著係 經過蝕刻及研磨（polish)以得到期望之結果。導因於碾磨 運作之應力亦得以移除。 圖1 d描繪在單晶矽晶圓1 〇上所實行之後續製造。首先， 一磊晶矽層14係生長於單晶矽晶圓1〇上。該磊晶矽層14順 著單晶矽晶圓10之晶體結構且因而亦為單晶。磊晶矽層14 與單晶矽晶圓1 〇之間的主要差異在於磊晶矽層丨4包含摻雜 126326.doc 1303474 物。因此，磊晶矽層14係屬於n型摻雜或卩型摻雜。 其次’形成積體電路16A和16B。積體電路16A或16B包 含複數個如電晶體、電容、二極體等之半導體電子元件、 以及連接該等電子元件之上槓桿金屬化（upper lever metalization)。一電晶體具有佈植至磊晶矽層I#内之源極 和汲極區。這些源極和汲極區之摻雜類型與磊晶矽層14之 摻雜類型相反。源極和汲極區係佈植至磊晶矽層丨4内至一 期望之深度，但通常未完全佈植穿透磊晶矽層14，致使在 各別源極或汲極區下方維持某些未經佈植之磊晶矽。金屬 化包含全部置於磊晶矽層14上方之金屬線。接觸窗引腳接 著係形成於積體電路16A和16B上。積體電路16A和16B係 彼此完全相同且係以一小切割道18予以彼此分離。雖然未 予不出’凸塊20係在一各自之積體電路16八和16B上排成 列及行所組成之陣列。 圖le描繪上述圖ld之組合晶圓。組合晶圓具有一直徑約 為300釐米之外緣22。許多積體電路16係成列及行形成於 邊緣22内。每一個積體電路16皆具有一矩形輪廓。一各別 之切割道係置於一各別之列或行之間。 接著雷射切穿該等切割道18將圖le之組合晶圓分成複數 個裸晶片。每一個裸晶片從而僅包括該等積體電路16中之 個 日日圓之切割係視為”切斷（singulation)，，或，，切判 (dicing)"。厚鑽石層12非常硬且由於其厚度，難以利用|專 統鋸割運作切割厚鑽石層12，因而需用到更為精密的雷射 切割。 126326.doc 1303474 圖If描繪兩個裸晶片24A和24B。每一個裸晶片24A和 24B皆包括各自的厚鑽石層12、單晶矽晶圓1〇、及磊晶矽 層14。裸晶片24A包含積體電路16A且裸晶片24B包含積體 電路16B。每一個裸晶片24A及24B皆各自包含一組凸塊 20 〇 圖lg描繪一含有一封裝基底3〇和裸晶片24A之電子組 裝。裸晶片24A係相對於其在圖1 f中的位置翻轉致使凸塊 20位於底部且厚鑽石層12位於上方。每一個凸塊2〇皆各自 置於一位於封裝基底上方之接觸引腳（未示）上。然後將電 子總成28置於一熔化凸塊20之熔爐中，並接著予以冷卻， 致使凸塊20附著至封裝基底30上之接觸引腳。 使用時，電子信號可經由封裝基底32中之介層窗與金屬 線並自凸塊20予以提供。該等電子信號經由凸塊2〇傳送至 積體電路16A或自積體電路16A傳出。積體電路16A之運作 使其本身發熱。積體電路16A之發熱在各點之間並不均 勻。熱點因而係橫跨積體電路16A之不同位置產生。 熱里由積體電路1 6 A經由蠢晶碎層14和單晶碎晶圓1〇傳 導至厚鑽石層12。熱量因單晶矽晶圓丨〇較薄而能輕易地傳 導至厚鑽石層12。由於厚鑽石層丨2較高之導熱率，熱量自 該等熱點水平傳導至厚鑽石層12之冷卻區。從而減低位於 熱點之溫度。與一薄鑽石層相比較，可經由厚鑽石層12水 平傳導更多熱量。 在製造一厚鑽石層時利用一種剪切運作 圖2a描繪一犧牲性多晶矽晶圓5〇，一厚鑽石層52係沉積 126326.doc -10- 1303474 於該犧牲性多晶矽晶圓50上， 獲著為積一多晶秒層5 4。 用於製造多晶石夕晶圓之製程你 枉係已知的。一多晶矽鑄塊一般 係在澆鑄運作時予以赞拌日& ^ I仏且接者自鑄塊鋸割出晶圓。厚鑽 石層52係根據引用圖la所說 几乃 < 相冋咼溫技術予以沉積且 亦具有一介於300至5〇〇微#夕鬥AA庙十 办 似木之間的厚度。多晶矽層54係利
用已知技術予以沉稽且且古· X 積五具有一介於10至15微米之間的厚 度0
如圖所$接著翻轉組合晶圓致使多晶矽層54位於底 部。 一 圖2 C描繪具有引用圖1 a而說明之型式之單晶晶圓5 6。單 晶晶圓56亦具有約3〇〇釐米之直徑及約75〇微米之厚度。氫 離子58係佈植至單晶晶圓％之上表面。
圖2d描繪圖2c之單晶矽晶圓％在佈植離子％之後的狀 況。離子58在低於圖以之單晶矽晶圓兄之上表面下方約⑺ 至25微米處產生一邊界6〇。為了進一步說明，低於邊界 之部分係視為，，單晶矽晶圓56A，，且高於邊界之區域係視 為”最終單晶矽薄膜56B”。空隙係形成於邊界6〇。該等空 隙減弱最終單晶矽薄膜56B對單晶矽晶圓56A之附著力。 如圖2e所示，多晶矽層56係置於最終單晶矽薄膜56B上 且係用已知之矽連結法予以連結至該最終單晶石夕薄膜 56B。邊界60從未曝露至用於形成厚鑽石層52且會破壞邊 界60之高CVDD溫度下。 如圖2f所示，犧牲性多晶矽晶圓5〇係在一蝕刻運作時予 以移除。由於厚鑽石層52作用為一餘刻中止層，故不需對 126326.doc 11 1303474 蝕刻運作施以嚴密控制。犧牲性多晶矽晶圓5〇因而可相對 快速地予以移除。 在圖2g中，接著將圖2f之組合晶圓翻轉致使單晶矽晶圓 56A位於上方。 如圖2h所示，單晶矽晶圓56A係在剪切運作時自最終單 晶矽薄膜56B予以移除。剪切運作可例如含括一衝射至單 曰曰矽晶圓56A之氣體喷射。由於該等空隙，單晶矽晶圓 56A於邊界60處自最終單晶矽薄膜56B剪切，從而僅將最 1 終單晶石夕薄膜56B遺留在多晶矽層54上。最終單晶石夕薄膜 56B係藉著予以蝕刻和研磨，並如在此之前引用圖^8之 說明實行後續之製程。 引用圖2a_h所說明之製程與引關㈣所說明之製程因 排除了用以得到圖1〇之組合性晶圓所作的碾磨運作而有所 不同。一更加快速之剪切運作係用於得到㉛之組合晶圓。 如圖2h所示，製造出一厚鑽石層52。厚鑽石層u具有如 圖1 c之尽鑽石層12所具有之相同優點及缺點。 在製造一薄鑽石層時利用一種剪切運作 在圖3a中，提供一犧牲性多晶矽晶圓7〇，其中一薄鑽石 層72係沉積於該犧牲性多晶石夕晶圓7〇中，接著為沉積一多 晶矽層74。薄鑽石層72之厚度係介於5〇至15〇微米之間且 係利用在此之前所說明之相同CVDD技術予以沉積。在圖 中圖3a之組合晶圓係經由翻轉致使多晶矽層74位於底 P在圖3c中，一單晶矽晶圓80係用離子82予以佈植。如 圖3d所不，该等離子於一較低之單晶矽晶圓與接著較 126326.doc •12- 1303474 高處之最終單晶㈣膜56B之間產生—邊㈣。在圖化 中’多晶石夕層74係連結至最終單晶石夕薄媒56B。圖3a-3e與 圖2a-2e之間的類似性係明顯的。 J在圖3f中，圖3e之組合晶 圓係經過翻轉致使單晶矽θ圆 平日日矽日日® 56Α位於上方。如圖3g所 示，單晶石夕晶圓⑽接著係自最終單晶石夕薄膜56B予以f 剪㈣心引用圖2h所說明之剪切。最終單晶石夕薄 膜56B之上表面係接著予以蝕刻並研磨。
如圖3h所示，接著實行進一步處理以形成積體電路說 和80B，然後係形成焊接凸塊接觸窗82。犧牲性多晶矽晶 圓70對所有形成於其上之層和元件提供結構性支撐。若不 藉助犧牲性多晶㈣7〇,薄鑽石層72的厚度通常是不足以 支撐該等位於其上之層。犧牲性多晶石夕層7()提供一類似於 傳統矽晶圓之下方矽表面。設計用來處理傳統矽晶圓之傳 統工具及設備亦可用於處理圖化和扑之組合性晶圓。 一傳統鋸割法係藉著用來鋸穿一介於積體電路8〇A與 80B之間的切割道9〇。此鋸割法切穿最終單晶矽薄顏 56B、多晶矽層74、薄鑽石層72、以及犧牲性多晶矽晶圓 70° —傳統鑛片因其厚度僅介於5〇至15〇微米之間而可用 於切穿薄鑽石層72。 圖3i描繪一包括一封裝基底102之電子總成100和一位於 該封裝基底102上之裸晶片1〇4。裸晶片1〇4包含犧牲性多 晶石夕晶圓70、薄鑽石層72、多晶矽層74、最終單晶矽薄膜 56B和蠢晶矽層78之各別部分。裸晶片74亦包括積體電路 80A、以及某些凸塊82。該等凸塊82係置於封裝基底102上 126326.doc -13- 1303474 方之接觸窗上。 總成100係接著置於一熔爐中而使得該等凸塊82熔化， 然後自熔爐移出總成100致使該等凸塊82固化並附著至封 裝基底102上之接觸窗引腳，從而使裸晶片ι〇4緊固至封袭 基底102。 封裝基底102之厚度及強度足以支撐裸晶片1〇4而不需用 到犧牲性多晶矽晶圓7〇。如圖3j·所示，犧牲性多晶矽晶圓 70接著係在例如蝕刻運作時予以移除。即使未移除多晶矽 晶圓70 ’薄鑽石層仍然能夠將熱量自積體電路8〇a之熱點 導出然而，若是將犧牲性多晶矽晶圓70移除，則得以更 容易地將熱量自薄鑽石層72之上表面移除。在移除犧牲性 多晶石夕晶圓70之後，較薄之裸晶片⑽係藉由封裝基底ι〇2 予以結構性支撐。 雖然在附时已說明並表㈣定之㈣性具體實施例， 要瞭解該等具艘實施例僅具描述性質而不局限本發明，且 士有能力作修改，故本發明不局限於所表示及 說月之特定建構和配置。 【圖式簡單說明】 本發明係以實施例的方式予 叭卞以進一步說明，其中： 圖1 a係一其上具有一厚鑽 时 圖； 9之單晶矽晶圓之剖面側視 圖lb係一類似於圖u之圖示 方，· 一 /、單晶梦晶圓係位於上 圖 I26326.doc ic係在碾磨（grind)單晶矽晶圓之後 類似於圖lb之 -14- 1303474 - 圖不， 圖1 d係在將一磊晶矽層、積體電路、及接觸窗形成於單 晶矽晶圓上之後，一類似於圖丨0之圖示； 圖le係一圖Id所示架構之上視圖，其特地標示積體電路 之位置及介於該等積體電路之間的切割道（scribe street); 圖If係在執行一雷射切割以產生單顆裸晶片之後，一類 似於圖le之圖示； 圖1 g係具有其中一顆裸晶片之電子封裝之剖面側視 圖’該其中一顆裸晶片係經翻轉並置於一封裝基底上； 圖2a係一其上具有一厚鑽石層和一多晶矽層之犧牲性多 晶矽晶圓之剖面側視圖； 圖2b係一類似於圖2a之圖示，但其多晶矽層係位於底 部； 圖2c係一單晶矽晶圓之剖面侧視圖，其中該單晶矽晶圓 之上表面具有離子佈植； 圖2d係一類似於圖2c表示一邊界之圖示，該邊界之形成 係導因於離子佈植； 圖係一組合晶圓之剖面側視圖，其係藉由將多晶矽層 矽連結至最終單晶矽薄膜而建構； 圖2f係在移除犧牲性多晶矽晶圓之後，一類似於圖“之 圖不， 圖2g係一類似於圖2f之圖示，但單晶矽晶圓係位於上 方； 圖2h係在一剪切（shearing)運作之後，一類似於圖以之 126326.doc -15- 1303474 圖示； 圖3a係一犧牲性多晶矽晶圓之剖面側視圖，其上方具 —薄鑽石層和一多晶石夕層； x、有 圖3b係一類似於圖3a之圖示’但多晶矽層係位於底部； 圖3c係-單晶碎晶圓之剖面側視圖，其中離 上表面内； …、 圖3d係一類似於圖3c表示一邊界之圖示，該邊界係導因 於離子佈植； 圖3e係一組合晶圓之剖面侧視圖，其係藉由將多晶矽層 矽連結至單晶矽晶圓之最終單晶矽薄膜而形成； 圖3f係一類似於圖3e之圖示，但單晶矽晶圓係位於上 方； 圖3g係在一剪切運作之後，一類以於圖3£之圖示； 圖3h係在形成一磊晶矽層、製造積體電路及形成接觸窗 之後，一類以於圖3g之圖示； 圖3i係一源自圖3h之架構含有一裸晶片之電子總成以及 一上置裸晶片内容之封裝基底之剖面側視圖；以及 圖3 j係在使接觸窗附著至封裝基底並移除犧牲性多晶矽 晶圓之後，一類似於圖3i之圖示。 【主要元件符號說明】 1〇 單晶矽晶圓 12 厚鑽石層 14 磊晶矽層 16，16A，16B 積體電路 126326.doc -16- 1303474
18 分界道 20 凸塊 22 外緣 24A，24B 裸晶片 28 電子總成 30,（32) 封裝基底 50 犧牲性多晶矽晶圓 52 厚鑽石層 54 多晶矽層 56 單晶（矽）晶圓 56A 早晶秒晶圓 56B 最終單晶矽薄膜 58 氫離手 60 邊界 70 犧牲性多晶矽晶圓 72 薄鑽石層 74 多晶矽層 78 磊晶矽層 80 早晶碎晶圓 80A，80B 積體電路 82 離子，凸塊 84 邊界 90 切道 100 電子總成 126326.doc 17- 1303474 102 封裝基底 104 裸晶片
126326.doc -18 -

Claims (1)

  1. !3〇3474
    、申請專利範圍： 包含： 上形成 一固態鑽石 一種用於製造複數個裸晶片之方法， 形成一具有一支撐層及在該支撐層 層之一第一組合晶圓； 第— 藉:合將::植入—單晶半_料之-表_成 稽由附著該第一組合 第三組合晶圓； 王緣弟二組合晶圓以 自具有該等離子植入的該單晶 前力 守體材科的一部分修 次有該等離子植入的該單晶半導 材科的一部分，具 有4等離子植入的該單晶半導 平0千导體材科的該部分在該固態 、石層上形成一單晶半導體材料層； 在該單晶半導體材料層上製造複數個積體電路；以及 在該等積體電路之間切開該固態鑽石層。 如申睛專利範圍第1項之方法，進一步包含·· 在亥支樓層與a亥單晶半導體材料層之間以該固態鑽石 層形成一支撐層；以及 切開該支撐層，俾使其個別部分形成該等裸晶片的個 別之一的部分。 3 ·種用於製造複數個裸晶片之方法，包含： 在一犧牲性晶圓上形成一固態鑽石層； 在為固態鑽石層上形成一材料層； 將離子植入一單晶半導體材料； 連、、° ^亥單半導體材料之一侧藉此將該離子植入至該 126326.doc 1303474 材料層； 自連結至該材料層的該單晶半導體材料之一最終部分 切開該單晶半導體材料之一部分； 在該單晶半導體材料上形成一半導體材料蟲生層； 在該蟲生層中與上形成複數個積體電路，以形成一組 合晶圓；以及 口 之裸晶片彼此分割開。 4. 5. 6· 如申請專利範圍第3項之方法’進一步包含： 自该犧牲性晶圓之至少_ ν ^ 部分移除該固態鑽石層。 如申請專利範圍第4項之方法，其中在切開該組;晶圓 以切斷該裸晶片之前自該犧牲層移除該固態鑽日曰困 如申請專利範圍第3項之方法，其巾㈣ / 保留在該犧牲層上直到該 層至少 最終部分切開。 Ρ ^自該 126326.doc
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US20060270135A1 (en) 2006-11-30
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US7432532B2 (en) 2008-10-07
US20030025198A1 (en) 2003-02-06
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