TWI304270B - A wafer and a die having an integrated circuit and a layer of diamond - Google Patents

Description

1304270

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a composite wafer from the present invention. A bare wafer of wafers, and a method of including an electronic assembly of the bare wafer, wherein the bare wafer has a diamond layer for conducting heat. 2) Description of Related Art The integrated circuit is typically formed on a germanium wafer, which is then sliced into individual bare wafers. Then each of the bare wafers has a portion of the shredded wafer * wherein the integrated circuits are formed on a portion of the tantalum wafer, respectively. The electronic signal can be input or output to the integrated circuit. The operation of the integrated circuit causes the integrated circuit itself to heat up and the rise in the temperature of the integrated circuit destroys the integrated circuit itself. The temperature at all points on the integrated circuit should therefore be maintained below a certain maximum temperature. The operation of the integrated circuit is not uniform, causing some points on the integrated circuit to generate more heat than other points, thus producing a π hot spot π. Without such hotspots, it is possible to maintain the desired integrated circuit temperature while increasing the average power consumption of the bare die, thereby allowing the integrated circuit to operate at a higher frequency. BRIEF DESCRIPTION OF THE DRAWINGS The invention is further illustrated by way of example, in which: FIG. 1 a is a cross-sectional side view of a single crystal germanium wafer having a thick diamond layer thereon; FIG. 1 b is similar to FIG. a diagram of a, but its single crystal germanium wafer is located on the upper 1304270 (2) Figure lc is after grinding the single crystal germanium wafer, similar to the diagram of Figure lb; Figure 1 d is in the An epitaxial layer, an integrated circuit, and a contact window are formed on a single crystal wafer, similar to the diagram of FIG. 1 c; FIG. 1 e is a top view of the structure shown in FIG. Specifically, the position of the integrated circuit and the scribe street between the integrated circuits are shown; Figure 1 f is a similar to Figure 1 e after performing a laser cut to produce a single bare wafer. Figure 1 is a cross-sectional side view of an electronic package having one of the bare wafers, one of which is flipped over and placed on a package substrate; Figure 2a has a thick diamond layer thereon A cross-sectional side view of a sacrificial polysilicon wafer with a polysilicon layer; Figure 2b is a diagram similar to Figure 2a, but with polycrystalline The layer of germanium is located at the bottom; FIG. 2 is a cross-sectional side view of a single crystal germanium wafer, wherein the surface of the single crystal germanium wafer has ion implantation; FIG. 2 is a similar to FIG. As shown, the formation of the boundary is due to ion implantation; Figure 2 e is a cross-sectional side view of a composite wafer constructed by joining a polycrystalline germanium layer to a final single crystal germanium film; Figure 2f is After removing the sacrificial polysilicon wafer, an illustration similar to that of Figure 2e; Figure 2g is similar to the diagram of Figure 2f, but the single crystal germanium wafer is located on the upper 1304270 _ (3) 1 Figure 2 h After a shearing operation, a diagram similar to FIG. 2g; FIG. 3a is a cross-sectional side view of a sacrificial polysilicon wafer having a thin diamond layer and a polycrystalline layer thereon; b is a diagram similar to that of Fig. 3a, but the polysilicon layer is at the bottom; Fig. 3 c is a cross-sectional side view of a single crystal germanium wafer in which ions are implanted in the upper surface thereof; Figure 3c shows a diagram of a boundary caused by ion implantation; Figure 3 e is a cross section of a combined wafer a side view formed by bonding a polysilicon layer to a final single crystal germanium film of a single crystal germanium wafer; FIG. 3 f is a diagram similar to FIG. 3 e, but the single crystal germanium wafer is located above Figure 3 g is a diagram of Figure 3 f after a shearing operation; Figure 3 is a diagram of Figure 3 f after forming an epitaxial layer, fabricating an integrated circuit, and forming a contact window. Figure 3 is a cross-sectional side view of a package assembly of the structure of Figure 3h containing a bare die and a package substrate with an upper die content; and Figure 3 is a diagram of attaching the contact window to the package After the substrate and the sacrificial polysilicon wafer are removed, an illustration similar to that of FIG. DETAILED DESCRIPTION OF THE INVENTION The first, second, and third process stages are described with respect to FIG. 1 ag, FIGS. 2a-h, and FIG. 3 aj, respectively, whereby a wafer is fabricated in each of the examples, and a wafer is produced from the wafer. a bare die, and an electronic assembly including the bare die. 1304270 (4) The bare wafer has a diamond layer whose primary function is to dissipate heat from a hot spot of an integrated circuit located in the bare wafer. In the first process, a thicker layer is formed which spreads more heat. However, the first process utilizes a more cumbersome milling operation. Because of the thicker diamond layer, a specific laser cutting operation is used to cut through the rock layer. In the second process, the milling operation of the first process is excluded and replaced with a shearing operation. A thick diamond layer is also formed in the second process with associated advantages and disadvantages. In the third process, a shearing operation is also used to eliminate a milling operation, but a thinner diamond layer that is easier to cut is formed by a conventional sawing method. The thin diamond layer is also coated by a sacrificial polysilicon wafer such that the assembled wafer system has an upper surface and an underlying surface. The composite wafer can be used more "transparently" in conventional mechanical processes to handle conventional twins. Sacrificial polysilicon wafers also provide structural support that is lacking in thin diamond layers. In the manufacture of a thick diamond layer, a single crystal (single crystal) germanium wafer 10 is depicted by a milling operation in the drawing, wherein a thick diamond layer 12 is deposited on the single crystal germanium wafer 10 . Single crystal germanium wafers are manufactured according to known processes. A long thin vertical single crystal core (a type of semiconductor material) is inserted vertically downward into a crushing bed (b a t h 〇 f s i 1 i c ο η). The core is then pulled vertically upwards out of the bath. The single crystal germanium is deposited on the core while being pulled out of the bath, so that a single crystal germanium ingot is thus formed to have a diameter larger than the core diameter. Currently, such ingots have a diameter of about 300 cm and a height of -9 - 1304270 (5) degrees is a multiple of the diameter. The ingot is then sawn into a number of wafers. The wafer sawed by a pound block preferably has a thickness of about 75 Å. The single crystal twin 10 thus has a diameter of about 300 cm and a thickness of about 75 Å. The thick diamond layer 12 is deposited using chemical vapor diamond deposition (CVDD) technology. The single crystal germanium wafer 10 is placed in a CVDD chamber and heated to a higher temperature of, for example, about 1000 °C. The glass that reacts with each other to form a diamond is then brought into the chamber. The diamond is then deposited from the broken glass onto the entire upper surface of the single crystal crucible. A diamond deposited on a single crystal germanium wafer is a solid polycrystalline diamond having a thermal conductivity of about 〇 〇 〇 W/mK and attached to the upper surface of the single crystal germanium wafer. This process continues until the thickness of the thick diamond layer 丨2 is between about 300 microns and 500 microns. The resulting thick diamond layer 12 thus has a straight meridian of 3 cm. The combined wafer of Figure 1a is then removed from the CVDD chamber and cooled. Further views of polycrystalline diamond deposition are known in the art and are not described in detail herein. As shown in Fig. 1b, the combined wafer of Fig. 3 is then flipped so that the single crystal twin 10 is located above. The thick diamond layer 12 is then placed on the surface of the milling machine. A grinding head of a milling machine then grinds the single crystal silicon wafer 1 down. Figure 1c depicts a composite wafer after the single crystal crucible is milled down. The thickness of the single crystal silicon wafer 10 is generally between 1 2 and 25 μm. The combined wafer shown in Figure lc is then removed from the mill. Since the thickness of the thick diamond layer 12 is between 300 and 500 microns, the combined wafer is not damaged when it is removed from the milling machine and subsequent handles. The thick diamond layer 12 thus provides structural support for the thinner single crystal germanium wafer 10. The upper surface of the single crystal germanium wafer 10 is then etched and ground (p 〇 1 i s h ) to obtain the desired result. The stress caused by the grinding operation was also removed. -10- 1304270

(6) Figure 1 d depicts the subsequent fabrication performed on a single crystal germanium wafer 10. First, an epitaxial layer 14 is grown on a single crystal germanium wafer 1 . The epitaxial layer 14 follows the crystal structure of the single crystal germanium wafer 1 and thus is also a single crystal. The main difference between the epitaxial layer 14 and the single crystal wafer 1 is that the amaze layer 14 contains dopants. Therefore, the mesogenic layer 14 is classified as an n-type doping or a p-type doping. Next, integrated circuits 16A and 16A are formed. The integrated circuit 16A or 16A includes a plurality of semiconductor electronic components such as transistors, capacitors, diodes, etc., and upper lever metalizations connected to the electronic components. A transistor has source and drain regions implanted into the moiré layer 14. The doping type of these source and drain regions is opposite to that of the epitaxial germanium layer 14. The source and bungee regions are planted into the wormhole layer 14 to a desired depth, but usually do not completely penetrate the wormhole layer 14' to maintain it under the respective source or bungee zone. Some of the untreated, planted crystals are broken. The metallization includes all of the metal lines placed over the epitaxial layer 14. The contact window pins are then formed on the integrated circuits 16A and 16B. The integrated circuits 16 and 166 are identical to each other and are separated from each other by a small cutting path 18. Although not shown, the bumps 20 are arranged in an array of columns and rows on a respective integrated circuit 16A and 166. Figure 1 e depicts the combined wafer of Figure 1d above. The composite wafer has an outer edge 22 having a diameter of about 3 cm. A plurality of integrated circuits 16 are formed in columns and rows in the edge 2 2 . Each of the integrated circuits 16 has a rectangular outline. A separate scribe line is placed between a separate row or row. The laser then cuts through the dicing streets 18 to divide the combined wafer of Figure 1 e into a plurality of bare wafers. Each of the bare wafers thus only includes the temperature of the hot spot of the integrated circuit 1 6 1304270 1_ (8) 1^^. More heat can be conducted horizontally through the thick diamond layer 1 2 compared to a thin diamond layer. In the manufacture of a thick iron layer, the temple uses a shearing operation. Figure 2a depicts a sacrificial polysilicon wafer 50. A thick diamond layer 52 is deposited on the sacrificial polysilicon wafer 50, followed by deposition of a polysilicon. Layer 5 4. Processes for making polysilicon wafers are known. A polycrystalline ingot is typically fabricated during the casting operation and then sawn from the ingot. The thick diamond layer 52 is deposited according to the same high temperature technique as described with reference to Figure 1a and also has a thickness of between 300 and 500 microns. The polysilicon layer 54 is deposited using known techniques and has a thickness between 10 and 15 microns. As shown in Figure 2b, the flipping of the combined wafer then causes the polysilicon layer 54 to be at the bottom. Figure 2c depicts a single crystal wafer 56 of the type described with reference to Figure la. The single crystal wafer 56 also has a diameter of about 300 cm and a thickness of about 750 microns. Hydrogen ion 58 is implanted onto the upper surface of the single crystal wafer 56. Figure 2d depicts the state of the single crystal germanium wafer 56 of Figure 2c after implantation of ions 58. Ion 58 produces a boundary 60 at about 10 to 25 microns below the surface above the single crystal germanium wafer 56 of Figure 2c. To further illustrate, portions below the boundary 60 are considered to be π single crystal germanium wafers 5 6 A" and regions above the boundary are considered "final single crystal germanium films 56B." The voids are formed at the boundary 60. The voids weaken the adhesion of the final single crystal germanium film 56B to the single crystal germanium wafer 56A. As shown in Fig. 2e, the polysilicon layer 56 is placed on the final single crystal germanium film 56B and bonded thereto by a known germanium bonding method. Final single crystal germanium film

1304270 56B. Boundary 60 is never exposed to the high CVDD temperature used to form thick diamond layer 52 and destroy boundary 60. As shown in Figure 2f, the sacrificial polysilicon wafer 50 is removed during an etch operation. Since the thick diamond layer 52 acts as an etch stop layer, there is no need to tightly control the etching operation. The sacrificial polysilicon wafer 50 can thus be removed relatively quickly. In Figure 2g, the combined wafer of Figure 2f is then flipped such that the single crystal germanium wafer 5 6 A is above. As shown in Figure 2h, the single crystal germanium wafer 56A is removed from the final monocrystalline film 5 6 B during the shearing operation. The shearing operation can, for example, include a gas jet that is directed to the wafer wafer 56A. Due to the voids, the single crystal germanium wafer 56A is sheared from the final single crystal germanium film 56B at the boundary 60, leaving only the final single germanium film 56B on the polysilicon layer 54. The final single crystal germanium film 56B is etched and ground, and the subsequent process is carried out as previously described with reference to Figures Id-g. The process illustrated by reference to Figures 2a-h and the process illustrated by referenced la-g differs in that the milling operation used to obtain the combined wafer of Figure 1c is excluded. A faster cutting operation is used to obtain a combined crystal of 2h. As shown in Figure 2h, a thick diamond layer 52 is fabricated. The thick diamond layer 52 has the same advantages and disadvantages as the thick diamond layer 12 of Figure 1c. In the fabrication of a thin diamond layer, a shearing operation is used in FIG. 3a to provide a sacrificial polysilicon wafer 70 in which a thin diamond layer 72 is deposited in the sacrificial polysilicon wafer 70, followed by deposition. More 1304270 (10) wafer layer 7 4. The thin diamond layer 7 2 has a thickness between 50 and 150 microns and is deposited using the same CVDD technique as previously described. In Figure 3b, the combined wafer of Figure 3a causes the polysilicon layer 74 to be at the bottom via flipping. In Fig. 3c, a single crystal germanium wafer 80 is implanted with ions 82. As shown in Figure 3d, the plasma creates a boundary 84 between a lower single crystal germanium wafer 56A and a higher final single crystal germanium film 56B. In Figure 3e, the polysilicon layer 74 is bonded to the final single crystal germanium film 56B. The similarities between Figures 3a-3e and Figures 2a-2e are evident. In Fig. 3f, the composite wafer of Fig. 3e is flipped so that the single crystal germanium wafer 5 6 A is located above. As shown in Fig. 3g, the single crystal germanium wafer 56A is then sheared from the final single crystal germanium film 56B. This cut is similar to the cut illustrated by reference to Figure 2h. The surface of the final single crystal germanium film 56B is then etched and ground. As shown in Fig. 3h, further processing is then performed to form integrated circuits 80A and 8OB, and then solder bump contact windows 82 are formed. The sacrificial polycrystalline twins provide structural support to all of the layers and components formed thereon. Without the aid of the sacrificial polysilicon layer 70, the thickness of the thin diamond layer 72 is generally insufficient to support the layers thereon. The sacrificial polysilicon layer 70 provides a lower germanium surface similar to conventional tantalum wafers. Traditional tools and equipment designed to handle conventional tantalum wafers can also be used to process the combined wafers of Figures 3g and 3h. A conventional sawing method is used to saw through a scribe line 90 between integrated circuits 80A and 80B. This sawing method cuts through the final single crystal germanium film 5 6B, the polysilicon layer 74, the thin diamond layer 72, and the sacrificial polysilicon wafer 70. A conventional saw blade can be used to cut through the thin diamond layer 72 because its thickness is only between 50 and 150 microns.

1304270 00 Figure 31 depicts an electronic assembly ι0 comprising a package substrate 102 and a bare wafer 104 on the package substrate 102. The bare wafer 104 includes sacrificial extinction; the g layer 72, the polycrystalline layer 74, the final portion of the single crystal thin polycrystalline silicon wafer 70, the thin diamond, and the 溥 d. The bare wafer 74 also includes an integrated film 56B and an epitaxial layer 78. The bumps 82 are placed on the contact substrate ι 2 channel 80A and the contact windows above some of the swells.

The assembly 100 is then melted in a furnace to cause the bumps 82 to melt, and then the assembly is removed from the furnace to cause the bumps 8 2 to solidify and adhere to the contact pins on the package substrate 102. The bare wafer 104 is thereby secured to the package substrate 102.

The package substrate 102 is of sufficient strength and strength to support the bare wafer 1〇4 without the use of a sacrificial polysilicon wafer. As shown in Fig. 3j, the sacrificial polycrystalline crystals are then removed, for example, during an etching operation. Even if the polycrystalline wafer 70 is not removed, the thin diamond layer can still derive heat from the hot spot of the integrated circuit 8A. However, if the sacrificial polysilicon wafer 70 is removed, heat is more easily removed from the upper surface of the thin diamond layer 72. After the sacrificial polycrystalline dream wafer 70 is removed, the thinner bare wafer 104 is structurally supported by the package substrate 102. While the specific embodiments have been illustrated and described in the drawings, the invention is not limited to the nature of the present invention, and the invention is not limited thereto. The specific construction and configuration shown and described. -16 -

Claims (1)

13 touches (four) Patent Application No. 091117302 Patent Replacement of Chinese Patent Application (October 1996) Picking up and applying for patent scope A wafer comprising: a solid diamond layer; and a film film wide material material, a final single crystal semiconductor film on the solid diamond layer; a single crystal semiconductor material layer directly in the final single crystal On the semiconductor thin, the layer has a boundary defined between the final single crystal semiconductor film and the single crystal semiconductor material layer to trim the single crystal semiconductor material layer from the final single crystal semiconductor thin. 2. For wafers of claim 1, the solid diamond layer is at least 200 cm. 3. The wafer of claim 2, wherein the single crystal semiconductor layer has a width of at least 200 cm. 4. The wafer of claim 3, wherein the single crystal semiconductor layer is a single crystal layer. 5. A severed bare wafer comprising: a solid diamond layer having a thickness of less than 150 microns; a single crystal semiconductor material layer on the solid drill layer; a bonding material joining the solid diamond layer to the single crystal a semiconductor material layer; and an integrated circuit on the single crystal semiconductor material layer on the opposite side of the solid diamond layer. 6. The bare wafer as disclosed in claim 5, wherein the solid diamond layer has a bare lower surface. 7. The bare wafer cut off according to item 6 of the patent application, wherein the single crystal half 1304270 The conductor material layer is a single crystal germanium layer. 8. The bare wafer as disclosed in claim 7 of the patent application, further comprising: a polysilicon layer disposed between the solid diamond layer and the single crystal germanium layer. 9. The bare wafer as disclosed in claim 5, further comprising: a plurality of contact windows on the integrated circuit. 10. The bare wafer as in the fifth aspect of the patent application, wherein the bare wafer has a rectangular outline when viewed from above.