CN115732314A - Method for preparing polycrystalline film - Google Patents

Abstract

The invention provides a preparation method of a polycrystalline film, which comprises the following steps: providing a substrate; etching a groove on the surface of the substrate; depositing an amorphous semiconductor material on the side wall of the groove to form a side wall structure; filling a dielectric material in the groove and carrying out planarization treatment to form a filling structure, wherein the surface of the filling structure is flush with the surface of the substrate; growing a thin film layer on the surface of the substrate, wherein the thin film layer covers the side wall structure and the filling structure; and carrying out laser heat treatment on the surface of the thin film layer to form a polycrystalline thin film on the substrate. The invention can reduce the manufacturing cost of the polycrystalline film.

Description

Method for preparing polycrystalline film

Technical Field

The invention relates to the technical field of semiconductors, in particular to a preparation method of a polycrystalline film.

Background

The three-dimensional monolithic integration technology changes the layout of the traditional two-dimensional transistor from flat laying to longitudinal stacking in a stacking mode, and can greatly improve the integration level of the device.

Taking CMOS (complementary metal oxide semiconductor) device fabrication as an example, the conventional method for fabricating a two-dimensional transistor is to fabricate both NMOS (N-type metal-oxide-semiconductor) and PMOS (P-type metal-oxide-semiconductor) in CMOS on the same layer of substrate material. For the three-dimensional integration technology, firstly, after the NMOS (or PMOS) is prepared, the PMOS (or NMOS) is prepared on the top of the NMOS, the bottom device can be directly prepared on the silicon substrate, and the top device requires to prepare an active region material layer, i.e. a thin film, on the top of the bottom device again, so as to prepare the top device. The quality of this active region material layer, which is approximately close to the single crystal material of the substrate, therefore has a significant impact on device performance, the higher the quality of the fabricated CMOS device.

Although the existing method can prepare a film which is made of monocrystalline silicon and is ideal on the top of the advancing bottom layer, the cost is high and the yield is low. Meanwhile, in the existing method, a laser crystallization method is adopted to prepare a polycrystalline silicon film as an active area material layer on a bottom device, and the main method is that after a deep hole is etched on the upper surface of a substrate, a dielectric layer is arranged on the upper surface of the substrate and the deep hole, most of the upper surface of the dielectric layer is melted through laser, so that recrystallization treatment is carried out, polycrystalline material particles with regular shapes are formed on the surface of the substrate, the dielectric layer area which is not melted at the bottom of the deep hole is reserved as a seed crystal layer, and the polycrystalline silicon film is recrystallized after the laser is removed, so that the polycrystalline silicon film is formed. The regular shape means that the polysilicon grains are square one by one, and the characteristics of the single polysilicon grain are close to the quality of a single crystal, so that if a device can be prepared in the single crystal grain, the device performance equivalent to that of a single crystal silicon material can be obtained.

However, the key of the laser crystallization method is to ensure the size and the shape of the deep hole. If the aperture of the laser hole is too large, a single crystal grain with few defects, namely few crystal boundaries, is difficult to form, so the aperture of the deep hole must be controlled to be less than 150nm, and therefore, an LPCVD (low pressure chemical vapor deposition) process must be adopted, but the growth rate of the process is slow, the thermal budget is high, the preparation cost of the polycrystalline film is increased, the shape of the laser hole etched by the process is difficult to ensure, and the yield of the polycrystalline film is reduced.

In addition, during the preparation of an SOI substrate (silicon-on-insulator substrate) device, the silicon-on-insulator material can also adopt a polycrystalline material, and the performance of the polycrystalline material can be close to that of a monocrystalline silicon material.

Therefore, how to reduce the difficulty and cost of manufacturing a polycrystalline thin film and improve the yield of the polycrystalline thin film becomes a difficult problem to be solved urgently.

Disclosure of Invention

In order to solve the problems, according to the preparation method of the polycrystalline thin film provided by the invention, the side wall structure is formed on the side wall of the groove, and the side wall structure is used as the seed crystal filter, so that the thin film layer after laser heat treatment is recrystallized, and the polycrystalline thin film with polycrystalline material particles in a regular shape is obtained.

The invention provides a preparation method of a polycrystalline film, which comprises the following steps:

providing a substrate;

etching a groove on the surface of the substrate;

depositing an amorphous semiconductor material on the side wall of the groove to form a side wall structure;

filling a dielectric material in the groove and carrying out planarization treatment to form a filling structure, wherein the surface of the filling structure is flush with the surface of the substrate;

growing a thin film layer on the surface of the substrate, wherein the thin film layer covers the side wall structure and the filling structure;

and carrying out laser heat treatment on the surface of the thin film layer to recrystallize the thin film layer and form a polycrystalline thin film.

Optionally, before the step of growing the thin film layer on the surface of the substrate, the preparation method further comprises:

and performing reduction annealing treatment to expose the surface of the side wall structure on the surface of the substrate.

Optionally, the width of the groove is greater than 100nm.

Optionally, the thickness of the sidewall structure is less than 150nm.

Optionally, a surface of the substrate facing away from the recess is provided with a metal oxide semiconductor.

Optionally, the material of the substrate comprises: silicon or germanium.

Optionally, the dielectric material is an insulating material.

Optionally, the dielectric material comprises: at least one of silicon oxide, silicon nitride, and silicon oxynitride.

Optionally, the step of growing the thin film layer on the surface of the substrate comprises:

the thin film layer is grown at a temperature of 600 degrees celsius or less.

Optionally, the penetration depth of the laser light source used in the laser heat treatment of the surface of the thin film layer is smaller than the depth of the groove.

Alternatively, the energy density of the laser light source used in the laser heat treatment of the surface of the thin film layer is in the range of 1.5J/cm ² To 3J/cm ² 。

Optionally, the step of performing reduction annealing treatment on the surface of the sidewall structure exposing the surface of the substrate includes:

annealing the surface of the side wall structure exposed out of the surface of the substrate at the temperature of below 600 ℃ and above 200 ℃ in a nitrogen or inert gas environment;

and corroding the surface of the side wall structure exposed out of the surface of the substrate by adopting an acid solution so as to remove the oxide layer on the surface of the side wall structure exposed out of the surface of the substrate.

According to the preparation method of the polycrystalline film, the side wall structure is formed on the side wall of the groove, and the side wall structure wrapped by the insulating medium is used as the seed crystal filter, wherein the thickness of the side wall structure can limit that only a single crystal grain can pass through the side wall structure and enter the film layer in the recrystallization process, so that the effect of limiting the crystal orientation of crystals in the film layer is achieved. Compared with a laser crystallization method, the thickness of the side wall structure in the preparation method of the polycrystalline film provided by the invention is controlled by Kong Gengyi with a specified aperture formed by adopting a photoetching mode, and the side wall structure with the specified thickness can be formed by a direct growth method, even a nanoscale structure can be realized, so that the operation is simpler, and the yield is higher; meanwhile, as the deep hole does not need to be etched, the frequency of using high-precision photoetching is reduced, a hard mask etching technology required for forming the deep hole is omitted, and the preparation efficiency of the polycrystalline film is improved. In addition, the preparation method does not need to adopt LPCVD (low pressure chemical vapor deposition) because the filling problem of amorphous silicon is considered, but the temperature required by forming a side wall structure by adopting PECVD (plasma enhanced chemical vapor deposition) is lower, and the requirement on a seed crystal filter can be completely met, so that the thermal budget of the process is reduced, and the manufacturing cost of a polycrystalline film is reduced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic flow chart of a method for preparing a polycrystalline thin film according to an embodiment of the present disclosure;

FIGS. 2a to 2d are schematic structural diagrams of the related steps in the method for manufacturing a fan polycrystalline thin film according to an embodiment of the present application;

FIG. 3 is a schematic flow chart of a method for preparing a polycrystalline thin film according to an embodiment of the present disclosure;

fig. 4a to 4e are schematic structural diagrams of steps related to a method for manufacturing a polycrystalline thin film according to an embodiment of the present disclosure.

Reference numerals

1. A substrate; 11. a groove; 2. a first preparation layer; 21. presetting a structure; 211. a side wall structure; 212. a bottom surface structure; 3. a second preparation layer; 31. filling the structure; 4. a thin film layer.

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

Spatial relational terms, such as "under," "below," "under," "over," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.

It will be understood that when an element is referred to as being "fixedly attached" to another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.

As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," or "having," and the like, specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

In a first aspect, the present embodiment provides a method for preparing a polycrystalline thin film, referring to fig. 1 in combination with fig. 2a to 2d, the method comprising steps S101 to S106:

step S101: a substrate 1 is provided.

The substrate 1 may be a substrate in a top-level device in a CMOS device, and may also be an SOI substrate.

When the substrate 1 is a substrate in a device at the top layer in a CMOS device, a metal oxide semiconductor is arranged on the lower surface of the substrate 1; the material of the substrate 1 may be silicon or germanium, but is not limited thereto. The metal oxide semiconductor under the substrate 1 may be NMOS or PMOS. In the present embodiment, the material of the substrate 1 is silicon, and the metal oxide semiconductor under the substrate 1 is NMOS.

Step S102: a recess 11 is etched in the surface of the substrate 1.

Wherein, the width of the groove 11 is larger than 100nm, such as 110nm, 120nm, 150nm or 200 nm. In the present embodiment, the groove 11 is located on the upper surface of the substrate 1, and the width of the groove 11 is 120nm. Note that the depth of the groove 11 is determined by the wavelength of the laser used in step S107. If the laser wavelength is 532nm, the depth of the groove 11 is not less than 300nm.

Step S103: amorphous semiconductor material is deposited on the sidewalls of the recess 11 to form a sidewall structure 211.

The thickness of the sidewall structure 211 is less than 150nm, such as less than 100nm, preferably 100nm.

In an alternative embodiment, step S103 includes step S1031, and step S1031 is to deposit amorphous semiconductor material on the upper surface of the substrate 1, the bottom surface of the recess 11 and the sidewalls of the recess 11. The amorphous semiconductor material is amorphous silicon, amorphous Ge, siGe, siC, gaN, or other semiconductor materials, but is not limited thereto.

In this embodiment, the material of the sidewall structure 211 is amorphous silicon.

In an alternative embodiment, step S103 includes step S1032, and step S1032 is to deposit amorphous semiconductor material on the upper surface of the substrate 1, the bottom surface of the recess 11 and the sidewalls of the recess 11, and remove the amorphous semiconductor material deposited on the bottom surface of the recess 11.

Step S104: the groove 11 is filled with a dielectric material and planarized to form a filling structure 31. The surface of the filling structures 31 is flush with the surface of the substrate 1.

The dielectric material is an insulating material. Specifically, the dielectric material includes: at least one of silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, the dielectric material is silicon oxide.

It should be noted that, in the process of filling the dielectric material, the amorphous semiconductor material on the substrate 1 obtained in step S1031 may be covered by the dielectric material; a chemical mechanical planarization process is then performed to remove the dielectric material and the amorphous semiconductor material above the substrate 1, thereby forming the pre-designed structures 21 on the bottom surface and the side surfaces of the recess 11 and the filling structures 31 filling the remaining space in the recess 11 from the amorphous semiconductor material. The preset structure 21 includes a sidewall structure 211, and the upper surface of the filling structure 31 and the upper surface of the sidewall obtained in step S104 are both flush with the surface of the substrate 1. The dielectric material includes: at least one of silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, the dielectric material is silicon oxide.

Step S105: a thin film layer 4 is grown on the surface of the substrate 1.

The thin film layer 4 covers the sidewall structures 211 and the filling structures 31. The material of the thin film layer 4 is the same as that of the sidewall structure 21, and may be amorphous silicon, amorphous Ge, siGe, siC, gaN, or other semiconductor materials, but is not limited thereto. In this embodiment, the material of the thin film layer 4 is amorphous silicon.

Further, the step of growing the thin film layer 4 on the surface of the substrate 1 includes: the thin film layer 4 is grown at a temperature of 600 degrees celsius or less. When the substrate 1 is a substrate in a top device in a CMOS device, the temperature of the grown thin film layer 4 is limited, so that the metal oxide semiconductor under the substrate 1 is not damaged by heat treatment.

In an optional embodiment, before step S105, the preparation method further includes: the reduction annealing treatment exposes the surface of the sidewall structure 211 on the surface of the substrate 1.

By reducing and annealing the upper surface of the side wall structure 211, the upper surface of the side wall structure 211 can be directly contacted with the subsequent thin film layer 4, and hydrogen in the side wall structure 211 can overflow the side wall structure 211, so that the quality of the polycrystalline thin film formed by recrystallizing the thin film layer 4 is ensured.

In an alternative embodiment, the step of performing the reduction annealing process on the surface of the sidewall structure 211 exposing the surface of the substrate 1 includes:

annealing the surface of the side wall structure 211 exposed out of the surface of the substrate 1 at a temperature of below 600 ℃ and above 200 ℃ in a nitrogen or inert gas environment; and corroding the surface of the side wall structure 211 exposed out of the surface of the substrate 1 by using an acidic solution to remove the natural oxide layer on the upper surface of the side wall structure 211. The inert gas may be argon or helium.

Preferably, the surface of the sidewall structure 211 exposed out of the surface of the substrate 1 is annealed at a temperature of 400 degrees celsius.

The step of etching the surface of the sidewall structure 211 exposed on the surface of the substrate 1 with an acidic solution further includes: adopting an acidic solution as a water-solute ratio of 100: the hydrofluoric acid solution of 1 is used to etch the upper surface of the sidewall structure 211 at a temperature of 18-23 degrees celsius for 30 seconds, but is not limited thereto.

Note that, in the process of performing the reduction annealing process on the upper surface of the sidewall structure 211, the reduction annealing process is also performed on the upper surface of the substrate 1 and the upper surface of the filling structure 31. The reduction annealing is only performed on the natural oxide layer formed by oxidizing the air on the upper surface of the side wall structure 211, so that the side wall structure 211 can directly contact with the subsequent thin film layer 4, the polycrystalline silicon thin film can be formed on the thin film layer 4 after laser heat treatment, and the quality of the polycrystalline silicon thin film is improved. In addition, the native oxide layer on the upper surface of the sidewall structure 211 may be removed by grinding, in addition to the native oxide layer on the upper surface of the sidewall structure 211 being removed by using an acidic solution.

Wherein, the natural oxide layer on the upper surface of the substrate 1 can be removed by adopting an acidic solution to corrode the upper surface of the substrate 1.

Step S106: the surface of the thin film layer 4 is heat-treated by laser light to recrystallize the thin film layer 4 and form a polycrystalline thin film.

Wherein the penetration depth of the laser light source used in the surface of the laser heat treatment thin film layer 4 is smaller than the depth of the groove 11; the energy density of the laser light source used in the laser heat treatment of the surface of the thin film layer 4 is in the range of 1.5J/cm2 to 3J/cm2, which is not further limited in this embodiment.

In a second aspect, this embodiment provides a method for preparing a polycrystalline thin film, referring to fig. 3 in combination with fig. 4a to 4e, the method comprising steps S201 to S208:

step S201: a substrate 1 is provided.

Step S202: a recess 11 is etched in the surface of the substrate 1.

Step S203: amorphous silicon is deposited on the upper surface of the substrate 1, the bottom surface of the groove 11, and the sidewalls of the groove 11, forming a first preliminary layer 2.

Wherein amorphous semiconductor material is deposited on the sidewalls of the recess 11 to form a sidewall structure.

Step S204: a dielectric material is deposited on the first preliminary layer 2 to form a second preliminary layer 3.

A dielectric material covers the amorphous silicon on the upper surface of the substrate 1 and fills the remaining space within the recess 11.

Step S205: the first preparation layer 2 and the second preparation layer 3 are subjected to chemical mechanical planarization so that the upper surfaces of the sidewall structures 211 and the upper surfaces of the structures formed of the dielectric material are flush with the upper surface of the substrate 1.

The first preparation layer 2 after the chemical mechanical planarization process forms a sidewall structure 211 and a bottom structure 212 parallel to the upper surface of the substrate 1, that is, the preset structure 21 is formed by the sidewall structure 211 and the bottom structure 212; the dielectric material after the chemical mechanical planarization process constitutes the filling structure 31.

Step S206: the upper surface of the sidewall structure 211 is subjected to reduction annealing.

Step S207: a thin film layer 4 is grown on the upper surface of the substrate 1.

The thin film layer 4 covers the sidewall structures 211 and the filling structures 31.

Step S208: the surface of the thin film layer 4 is heat-treated by laser light to recrystallize the thin film layer 4 and form a polycrystalline thin film.

In the description herein, references to "some embodiments," "other embodiments," "desired embodiments," or the like, mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A method for producing a polycrystalline thin film, comprising:

providing a substrate;

etching a groove on the surface of the substrate;

depositing an amorphous semiconductor material on the side wall of the groove to form a side wall structure;

filling a dielectric material in the groove and carrying out planarization treatment to form a filling structure, wherein the surface of the filling structure is flush with the surface of the substrate;

growing a thin film layer on the surface of the substrate, wherein the thin film layer covers the side wall structure and the filling structure;

and carrying out laser heat treatment on the surface of the thin film layer so as to recrystallize the thin film layer and form a polycrystalline thin film.

2. The method according to claim 1, wherein before the step of growing the thin film layer on the surface of the substrate, the method further comprises:

and carrying out reduction annealing treatment to expose the surface of the side wall structure on the surface of the substrate.

3. The method of claim 1, wherein the width of the groove is greater than 100nm.

4. The method according to claim 1, wherein the thickness of the sidewall structure is less than 150nm.

5. The production method according to claim 1, wherein a surface of the substrate facing away from the recess is provided with a metal oxide semiconductor.

6. The method of claim 1, wherein the dielectric material is an insulating material.

7. The method of manufacturing according to claim 1, wherein the material of the substrate includes: silicon or germanium;

the dielectric material comprises: at least one of silicon oxide, silicon nitride, and silicon oxynitride.

8. The method according to claim 1, wherein the step of growing the thin film layer on the surface of the substrate comprises:

growing the thin film layer at a temperature of 600 degrees Celsius or less.

9. The production method according to claim 1, wherein a penetration depth of a laser light source used in the laser heat treatment of the surface of the thin film layer is smaller than a depth of the groove.

10. The method according to any one of claims 1 to 9, wherein the step of performing the reduction annealing treatment to expose the surface of the sidewall structure on the surface of the substrate comprises:

annealing the surface of the side wall structure exposed out of the surface of the substrate at the temperature of below 600 ℃ and above 200 ℃ in a nitrogen or inert gas environment;

and corroding the surface of the side wall structure exposed out of the surface of the substrate by adopting an acid solution so as to remove an oxide layer on the surface of the side wall structure exposed out of the surface of the substrate.

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