TWI295820B - Process for selectively etching dielectric layers - Google Patents

Process for selectively etching dielectric layers Download PDF

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TWI295820B
TWI295820B TW091134898A TW91134898A TWI295820B TW I295820 B TWI295820 B TW I295820B TW 091134898 A TW091134898 A TW 091134898A TW 91134898 A TW91134898 A TW 91134898A TW I295820 B TWI295820 B TW I295820B
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dielectric layer
layer
plasma
gas
dielectric
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TW091134898A
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TW200300980A (en
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Lin Hsieh Chang
Yuan Jie
Chen Hui
Panagopoulos Theodoros
Ye Yan
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Applied Materials Inc
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31629—Deposition of halogen doped silicon oxide, e.g. fluorine doped silicon oxide
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31633—Deposition of carbon doped silicon oxide, e.g. SiOC

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Description

1295820 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種選擇性蝕刻介電層的製程，例如有 關於雙層鑲嵌製程（Dual Damascene Process)。 【先前技術】 半導體積體電路技術持繽在能於早一積體電路晶片上製造電 晶體（transistor)、二極體（diode)、電容器（capacitor)及/或其 他電子元件上發展。此整合積集度（integration)的提昇，極大部 分係仰賴降低最小特徵結構（feature )尺寸而達成的。 先進的積體電路包含有複數的内連線層，其係由各別的介電 層而與半導體基材以及内連線層彼此之間加以分離。以微處理器 中之邏輯電路為例，其需要多個内連線層，以及介於其中的 介電層。一水平的内連線層係形成在一介電層上，然後再覆 蓋另一介電層。需要在每一介電層上蝕刻出小的接觸窗 (contact )或介層孔（Via hole)，並穿過該介電層，以連接這 些内連線層。 有許多技術可用來產生内連線及介層孔。其中之一係通 常被稱為“雙層鑲嵌製程”之技術。此製程包含，形成一溝 渠（trench )以及下方的介層孔；隨後，該溝渠及介層孔， 被導體材料所填滿，同時形成一内連線層與一下方的介層 孔。 一種特別的雙層鑲嵌製程將在此被討論，請參照第1 a 圖至IF圖’係取材於美國專利號碼6,211，〇92，其全部之揭 1295820 露内容在此併入並引為參考。一蝕刻結構，其包含下列各 層.（a) —底層（underiying layer) 1〇，（b) 一薄的下方終 止層（thin lower stop layer) 12，（〇 一下方介電層（1籍以 dielectric layer) 14,（d)一薄的上方終止層（upper st〇p Uyer) 16 以及（e)—上方介電層（upper dielectric layer) 20。此終止 層12、16之組成相對於介電層14、2〇之組成而言，係可使 一選擇性蝕刻製程可蝕刻穿過上方的介電層，但是終止在此 終止層。 此項技藝領域所熟知的，此介電層14、2 0之材料，包 含有摻雜與未摻雜的氧化矽（silie〇n 〇xide)材料。未摻雜 的氧化矽材料，典型的由分子式（Si〇x)來表示，其中X係 川於1·4至2.1之間，而二氧化石夕（smc〇ndi〇xide，其X接 近於2)是最普遍使用的。摻雜的氧化矽材料包含有矽、氧 以及一或多個添加的材料種類。這些層可以藉由諸如化學氣 相沉積法（chemical vap〇r deposition ; CVD )或者電漿輔助 化學氣相沉積法（plasma_enhanced chemical yap〇r deposition; PECVD)來生長。 氮化矽（Silicon Nitride)是一典型的終止層材料，其中之 介電層為氧化矽材料。氮化矽可以藉由諸如CVD或pEcvD 法來生長。 一第一光阻層44，係被沉積並微影圖案化以形成與相對 介層孔對應之光罩開口（ mask apertures ) 46，在此，以其中 之一來實例說明之。底層1〇典型的包含介電區與金屬區， 而在介層孔區域則具有一金屬區。 1295820 在第一蚀刻步驟，一延伸介層孔5〇，如第1B圖中所示， 被飯刻穿過上方介電層20、上方終止層16、以及下方介電 層1 4，並至下方終止層1 2。選擇恰當的蝕刻化學材料來進 行選擇性的触刻，使餘刻能停止於下方終止層1 2的上表面 52。例如，在第一步驟中，可使用一非選擇性定時蝕刻 (non-selective timed etch)來蝕刻此介層孔5〇，以穿過上 方介電層20、上方氮化物終止層16以及部分的下方介電層 14。之後可使用具有優良氧化物：氮化物選擇性的第二蝕刻 步驟，來選擇性的蝕刻殘餘的下方介電層14，並停止在此下 方終止層12的上表面52，以完成此延伸介層孔5〇。 在未說明的步驟中，第一光阻層44被剝除。然後，如 第1 c圖中所不，一第二光阻層56被沉積並微影圖案化，以 形成一光罩開口 58,其相對應於溝渠的位置。接下來的步 驟，說明於第1D圖，一溝渠62被蝕刻穿過上方介電層2〇, 並至上方終止層16的上表面64。此延伸介層孔5〇的深度因 此被有效的降低，以形成介層孔5〇，。 在更進一步的蝕刻步驟中，於介層孔5〇，的底部顯露出 來的下方終止層12係被蝕刻，如第！ E圖所示，其穿過下方 終止層12’並至底層1〇的上表面68，而其係為一典型的金 屬表面，且至少在此介層孔5〇，的位置處係為一典型的金屬 表面。根據此兩個終止層12及16的成 >，此蝕刻步驟可移 除一部分暴路在溝渠62底部的上方終止層16，以露出一下 方介電層14的上表面7G<)在另—步驟中，其可在#刻步驟 之則或之後執仃，第二光阻層56與任何在介電層蝕刻製程 1295820 中所形成侧壁上的聚合物均被剝除。 然後，如第1F圖中所示，一金屬72被填充至此溝渠62 與底部的介層孔50’以接觸底層1〇的上表面68。接下來， 使用化學機械研磨（chemical mechanical polishing ; CMP ) 移除任何溢出溝渠的金屬材料。此金屬72同時形成水平的 内連線74與介層孔76，而該介層孔76係接觸底層1〇。此 金屬72較合適的係為鋼（c〇pper )，但可以是另一金屬，例 如鋁（aluminum)。但是，此種雙層鑲嵌製程特別合適應用 於銅的金屬化製程中，因為不需要蝕刻銅。 通常在雙層镶嵌結構中的非金屬材料的介電常數k是考 望此越低越好# 如，較低的介電常數&會形成較低的灣 今，其依序降低了串音（。㈣七⑴以及輕纟（wupling) 而使得操作速度提高。但是，典型與終止^ ΜΗ (例女 氮化夕）起使用的材料是具有相當高介電常數^之材料。 例如，ShN4的介電常數k約為7·5 (其係 常數k(典型的…·…·2之間)成對比 因此’極f在雙層鑲嵌結構技術領域 介電常數k材料的不良影響。 與二氧化矽的介電 )° 中，有效地降低高 【發明内容】 ㈣月有效解決目前積體電路之上述介電層#刻製 之問通與其他的問題。 根據本發明之一會 .., 實施例，係提供一種用於蝕刻介電驾 之方法0此介電結構白 再匕含U)未摻雜之氧化矽或摻雜氟之孝 9 1295820 矽的一第一介電層與（b)摻雜碳氫 乳又軋化矽的一第二介雷 層。然後，於一電漿蝕刻步驟中蝕刻此 电〜耩，其中此電 漿餘刻步驟係使用包含氮原子與氟原子 卞 < 電漿源氣體來執 行。第二介電層係相對於第一介電層而於餘 μ⑷步驟中被選擇 性的蝕刻，以提供例如，第二介電層：第— ^ 介電層之蝕刻選 擇比（selectivity )為2.5 : 1或更大，更佳係為3 · 1戈 根據本發明另一較佳實施例，係提供_種在雙層鑲^結 構中蝕刻一溝渠的方法。此雙層鑲崁結構/ 人、、、° 否 · （ a) —底芦 (Underlying Layer);(b)一未摻雜之氧化矽或摻 ^ > 人《 /雕既之氧化石夕 之一；丨層孔介電層，該介層孔介電層係覆蓋於底層之上· (c)一摻雜碳氫之氧化矽的溝渠介電層，該溝渠介電===筌 :”層孔’I電層之上方；以及⑷一圖案化之光罩層，其 蓋於溝渠介電層之上方。此雙層鑲嵌結構亦較佳的包：二 伸介層孔，其延伸穿過溝渠介電層與介層孔介電層。於 漿蝕刻步驟中，在溝渠介電層中蝕刻出一或多個溝渠。蝕刻 係進行以穿過圖奉# +土 s a L β 0a χ 一 牙、α茶化之先罩層上之開口，直到介層孔介電層 之上表面的一部分暴露出為止。此電漿蝕刻步驟係以包含 氮原子及氟原子之電漿源氣體進行。相似於先前的段落中之 較佳實施例，此溝渠介電層較佳是相對於介層孔介電層而被 選擇性的蝕刻’以提供例如，溝渠介電層：介層孔介電層之 選擇比為2·5: 1或更大，更佳S3: 1或更大。 人在一些實施例中，電漿源氣體包含一種氣體，該氣體包 ^或夕個氮原子與一或多個氟原子（例如：三氟化氮； Nh)。在其他實施例中，電漿源氣體包含（a)一包含一或多個 10 1295820 氮原子（例如：氮N2)之氣體，以及（b) —包含一或多個氟原子 (例如：碳氣化合物氣體，Fluorocarbon Gas，如四I化碳， CF4)之氣體。 上述未摻雜之氧化矽層較佳為二氧化矽（Silicon Dioxide)層，且上述摻雜氟之氧化矽層較佳為一氟化矽玻璃 (Fluorinated Silica Glass)層。 在部分實施例中，上述之電漿蝕刻步驟係於一磁性輔助 反應性離子钱刻糸統（Magnetically Enhanced Reactive Ion Etching System)中實施。 本發明優點之一為，相對於一未摻雜之氧化石夕介電層與 一摻雜氣之氧化矽介電層而言，一摻雜碳氫之氧化矽介電層 係較優先被ϋ刻。 當高的介電常數之蝕刻終止層消除。因此，此結構之電 (Capacitance)可被降低。同時進而降低了串音 耦合（Coupling)，並允許增加元件的操作速度。 ’ 在本發明之詳細說明與申請專利範圍揭露之後，本發 之上述之與其他的實施例與優點，對於熟知此項 ： 明顯可見的。 β 【實施方式】 在此需特別注意， ，且全部氣體的成 t部氣體成分 分比率皆為容 如同實施方式的序言， 的百分比皆為容積百分比〇/〇 積比率。 11 1295820 有關於「選擇比（selectivity)」一詞，在此係指a)兩 種或多種材料之㈣率的比例，以及b)在實際㈣的過程 中 材料的蝕刻率相較於另一材料的蝕刻率係為增加的情 乂下將參圖示詳細說明本發明，其中本發明的車声佳實 施例也在此描述。但是’本發明仍可以不同形式被實施，這 些不同態樣不應被解讀為於此所述實施例之限制。 參照第2A圖及第2B圖，以說明本發明之一實施例的流 程。參照第2A圖，其係說明一結構，其包含有下方介電層 208、一上方介電層21〇以及一圖案化的光罩層214。此下方 w電層208係由氧化矽所形成，例如，二氧化矽（典型係由 四乙基正矽酸鹽（tetraethyi〇rth〇siiicate5TE〇s)所形成），或摻 雜I之氧化矽，例如，氟化矽玻璃（fluorinated silica glass ; FSG)。如同上述，二氧化矽的介電常數k典型係介於3·9至 4·2之間。而氟化矽玻璃的介電常數約為3·5。為了這個原因， I化石夕玻璃相較於二氧化矽玻璃而更適合使用於某些情 >兄。下方介電層208，可以為任何適合目前應用的厚度，而 且其可以此項技藝領域所熟知的CVD製程來形成。 上方介電層210係覆蓋於下方介電層208上方。在此實 施例中，上方介電層210係為氧化矽並摻雜有碳（carbon) 以及氫（hydrogen )(在此稱之為“摻雜碳氫之氧化矽”）。 上方介電層210，可以為任何適合目前應用的厚度。Yau等 人近期曾經在美國專利號碼6,054,379，以及6,072,227中發 表一種形成氧化碳-石夕材料 （oxidized carbon-silicon 12 1295820 material )的方法，在此將這兩篇專利之全部内容併入以做 為參考。這樣的薄膜同樣也被發表於美國專利號碼 6，168,726，其全部的揭露内容在此亦引為參考。此層較佳係 使用化學氣相沉積（chemical vapor deposition ; CVD )製 程製造’其使用氧化劑（oxidizer)與有機矽烷（organ〇-silany 的氣體前驅物（gaseous precursor)，以形成一低k介電層，其 具有介電常數在2.5至3之間。此CVD製程較佳係在一低能 量電谷輕合電漿中（其在晶圓上之能量密度小於1 W/cm2 )， 以及溫度小於100°c下實施。較佳的氫含量至少為3〇原子 %(atomic %)，更佳為45至6〇原子％，較佳的碳含量是介於 5至2 0原子％，更佳的是介於6至i 〇原子％，較佳的矽含量 是介於15至30原子％，更佳的是介於17至22原子％，及 較佳的氧含量是介於10至45原子％，更佳的是介於15至 30原子％。一種摻雜碳氫之氧化矽材料，目前正由位於美國 其商品名為 Black 加州聖克拉拉的應用材料公司所銷售+，其商品名為
DiamondTM 〇
的溝渠210t。
設備。傳統的反應性離子钱刻設 reactive ion etching ; RIE)的 設備包含有位於一真空反應室 13 l295820 中之陽極及陰極。此陰極典型的形成一臺座，以在此反應室 中用以支撐半導體晶圓，而陽極係典型的形成牆及/或此反應 室的上頂部。當處理晶圓時，電漿源氣體係注入此真空反應 至而陽極與陰極係由單一的正弦波頻率（RF)源來驅動， 、激發電裝源氣體形成電漿。此單一頻率典型的為 ΐ3·56ΜΗζ，雖然一般經常使用頻率ΙΟΟΚΗζ至2.45GHz，其 他頻率則是偶爾被使用。此RF能量可激發電漿源氣體，並 於反應室中鄰近處理此半導體晶圓處產生電漿。 電漿製程設備亦可為一磁性輔助反應性離子蝕刻設備 (magnetically enhanced reactive i〇n etch : merie)。此設 備典型的提供一或多個磁鐵或磁性線圈，其係能磁性控制電 漿以促進一更均勻的蝕刻製程。 一種可與本發明一起使用的特定MERIE反應室，係為 eMaXw反應室，其由美國加州聖克拉拉的應用材料公司所銷 售0 个竹料，較佳係以内含氮 使用於此蝕刻製程 1、"N D石队 子與氟原子的電漿源氣體為基礎。如一眚你你丨七
貫施例中，可使用N 氣體。在其他的實施例中，可使用一（a)内含氮原子的 體種類’以及（b)内含I原子的氣體種類之混合物。例 可使用包含有一 N2氣體及一或多種的磁翁i人 夕禋的奴虱化合物氣 (fluorocarbon gases，在此定義為具有碳與氟原子之一 體）之混合物的一電漿源氣體。更佳的是一混合N2及一 多種碳氟化合物的氣體’且該碳氟化合物氣體僅包含有碳 氟原子，例如，CF4氣體、GF6氣體或cj8氣體。 14 1295820 此蝕刻的化學材+ 斗疋值得注意的，因為可ii：占μ七入+ 層較佳的蝕刻率（例如 達成上方"電 /每分鐘，較佳是約可、*丨 υ·1微+(nnCron) I, 到大於1微米/每分鐘）。此巍列h與 材料同樣也值得注意 *匕蝕刻化學 因為其k供上方介電層 介電層208之間—個电層210與下方 ! . . f ^ 良好的選擇比。此選擇比典型的為2.5·· 去it彳干t方入f Μ 、 或者更大。由於此良好的選擇比， ^ ^ ^ t私時，下方介電層可被當作一蝕刻 終止層，因此可形成如筮 第2β圖中所示的結構。 在一特定的實施例中，一
J接又的選擇比及钱刻速率可 於一 MERIL·反應室，在 4干J 在相當低的能量（例如，小於500W， 更佳係约300W)以及一相當 々田同的壓力（例如，150 mTorr， 或者以上）下’於包含右w > 匕各有比乳體及eh氣體之電漿源氣體 下操作，以進行如第2A圖中的結構之蝕刻。 另-特定的實施例，一可接受的蝕刻率與選擇比可以實 施於eMaxTM反應室，：i：孫於 ,α ^ ^ ，、係於一相當高的能量（例如，大於 15 1 00W，更佳的是800至1200W)及一知a把认旷丄, ;次 相當低的壓力（例如， 小於150 — ’或更佳的是3〇至50 mTorr)，並於一叫 電聚源氣體下（其較佳流速係介於15至5〇 sccm⑻一 cubic centimeters t0 minute)之間），以完成第2a圖中的結構 的蝕刻。此陰極溫度係例如維持在1〇至2〇<t之間。較佳的 磁場範圍為0至30G F[此製程可以達到大於i微米/每分 鐘的推雜碳氫之氧化石夕的餘刻率，以及大於3:1的摻雜碳 氫之氧化矽：氟化矽玻璃的選擇比。 參照第3A至第3H圖，這些圖表示一特定的雙層鑲嵌製 !295820 程，以說明本發明係有效應用於此製程中。第3 A圖實例說 明-雙層㈣結構’其包含有底層4()1。底層仙典型的包 含介電區域404以及導電區域4〇2 ’例如銅區域。 在底層40 1之上係沉積有一蝕刻終止層4。此蝕刻終 止層406可使用任何針對氧化矽材料為合適的嘸刻終止材料 來形成，包含碳化梦（silic〇n carbide )或者是&化梦（siHc〇n nitride)(典型以《SiNx來代表，其+ χ在―個範圍中變 化，例如，1至1.5，且通常為s#4 )。此蝕刻終止層6可 以為任何適以作為蝕刻終止層的厚度，在此實施例中，其厚 度約為300至1000埃（Angstr〇m)。此蝕刻終止層4〇6可以 此項技藝領域所熟知的CVD製程來形成。 一介層孔介電層408係設置於蝕刻終止層4〇6之上方， 在此實施例中其係由有（a)—未摻雜的氧化碎（典型的由 Τ Ε Ο S所形成），例如-蓋〆卜访 / ι_ \ U如一氧化矽，或（b) —摻雜氟之氧化矽， 例如，氟化石夕玻填所蚯杰。l #、+、 匕t 呀坩、、且烕。如則所述，二氧化矽的介電常數 k典型的’I於3.9 i 4.2之間，且氟化矽玻璃的介電常數約為 3·5:此介層孔介電層4〇8可以是任何適以作為一介層孔層的 適當厚度，例如，在此實施例中之厚度約為3〇〇〇至5〇㈧埃。 一溝渠介電層410係形成在介層孔介電層408之上。在 此實施例中’此溝渠介電層41〇係為一摻雜碳氫的氧化矽， 其成分、構成與性質如參照帛2Α圖中所插述者。此溝渠介 電層410可以是任何適於成為一溝渠介電層的適當厚度，在 此實施例中之厚度係例如為3000至5000埃。 在溝渠介電層410之上方係沉積有一第—圖案化的光罩 16 1295820 層412，而其較佳為一有機光阻層。有關圖案化的光罩層412 的厚度及開口 4 1 2a的尺寸係可以為任何合適用來蝕刻一介 層孔的尺寸。例如，此圖案化光罩層可以為一有機光阻層， 其厚度係介於4000至7000埃之間，且具有一介於0.2至0.5 微米間之開口。 一旦如第3A圖中所述之結構被建立後，接著進行一蝕 刻製程，如第3B圖中所示，蝕刻至蝕刻終止層406以形成 一延伸的介層孔408v。 如上所述，此蝕刻製程可以任何適合的電漿製程設備來 執行，例如，一諸如MERIE反應室之類的電漿輔助反應性 離子餘刻系統（plasma-enhanced reactive ion etching system)。用於此製程步驟之餘刻化學材料可以是任何習知之 用於蝕刻以矽為基礎之材料且對於蝕刻終止層406具有良好 選擇比的蚀刻化學材料。用於此製程步驟之示範性餘刻化學 材料係以含乱的氣體為基礎’較佳係以敦化的碳氫化合物氣 體（fluorinated hydrocarbon gases，在此定義為具有碳、氫 以及氟原子之氣體）為基礎，例如，CH^F氣體。在#刻之 後’可產生如第3B圖中所示之結構。而後去除圖案化的光 罩層412，以產生如第3C圖中所示之結構。 接下來’第二圖案化的光罩層4 1 4係提供在此結構之 上，如第3D圖中所示。此第二圖案化的光罩層414例如可 以是一有機光阻層。有關於此圖案化的光罩層414的厚度及 開口 414a之尺寸可以為任何適以蝕刻一内連線（interc〇nnat) 溝渠的數值。例如’此圖案化的光罩層可以為一具有4〇〇〇 17 1295820 至7000埃之厚度以及約〇·2至0.5微米之開口泠有機光阻層。 參閱第3Ε圖，以一可相對於介層孔介電原408來選擇 性地蝕刻溝渠介電層41 0之蝕刻製程，於溝渠介電層41 〇中 蝕刻出一溝渠41 〇t。如與第2Β圖有關之詳細相述，此蝕刻 製程可以於任何適合的電漿製程設備來執行。如第2B圖中 有關之描述，使用在此製程中之蝕刻化學材料較佳係以内含 氮原子及氟原子的電漿源氣體為基礎（例如，NF3電漿源氣 體或者一内含N2氣體以及一或多種碳氟化合物氣體之混合 物的電漿源氣體）。使用此設備及蝕刻化學材科，可以相對 於介層孔介電層408而以約3 : 1或者更大的選擇比來蝕刻 溝渠介電層410，同時並以大於每分鐘1微米的速率餘刻此 溝渠介電層4 1 0。 如第1圖中有關的描述，雖然在此並未描述，一種如氣 化碎的材料係通常使用於習知技術中，以做為一介於溝渠介 電層與介層孔介電層之間的蝕刻終止層，而避免如角隅面切 割（corner faceting)、微溝渠（micro-trenching)，以及餘刻率 之微觀負載效應（etch rate micro-loading)。但是，因為氮化 矽具有相當高的介電常數k (例如，ShN*的介電常數約為 7 · 5 )’將其由本發明中之結構排除是有利的。如前段中所描 述的，在本發明之溝渠介電層410可以在蝕刻速率大於1微 米/每分鐘進行蝕刻，且同時達到3 : 1或者更大之選擇比。 因此’在習知技藝中介於溝渠介電層與介層孔介電層之間的 蝕刻終止層可以被去除，且並不會產生經驗中明顯角隅面切 割、微溝渠，以及蝕刻率之微觀負載效應。（由第3E圖中可 18 1295820 408所產生％介層孔408v 助於維持介層孔介電層408 以發現’在先前蝕刻介層孔介電層 中的光罩層414材料之存在，係有 肩部的完整性。） 在經過了溝渠㈣步驟，第二圖案化的 留部分被去除，以提供如第3F圖中所示之結幾。 在更進一步的蝕刻製程中 竹徂於；丨層孔408v下方的 餘刻終止層406加以移除，因4卜摆 砂于、口此楗供了通往底層金屬區域4〇2 的入口。為了達到此項目的，盆 ，、所便用之蝕刻化學材料為此 項技藝領域所熟知的。例如， J使用包含有嚷氟氫化合物 (fluorohydrocarbon，如 ，ηυ τ： ^ττ 如 LHF3，CH2F2，CH3F )、氮（ν2)、 氧（〇2)以及選擇性的句冬< 、 疋评I扪匕s有虱（argon)之蝕刻化學材料。 因此形成了第3 G圖中所示的結構。 、之後於金屬化製程中以金屬416 (典型的為銅）填充溝 渠410t與介層孔408v，如同該技術領域已知者。如熟知的 回等積體電路之小特徵結構的金屬化製程，此金屬化製程需 要在溝渠410t與介層孔408v上塗佈阻障層（barHer丨叮“） 以及濕潤層（wetting layers)。此溝渠41〇t及介層孔4〇8v 典型係使用金屬沉積製程填充，其通常至少部分由物理氣相 沉積來完成。典型的填充持續至金屬完全填充此介層孔4〇8v 與溝渠41 〇t，且可以稍微的覆蓋此上表面41〇s。接下來典型 地以化學機械研磨（chemical mechanical polishing )進行研 磨。因為以氧化矽為基礎的材料較金屬為硬，因此當研磨至 溝渠介電層410的上表面410s時，研磨即會停止。 如第3A圖至第3H圖所說明之一特別的雙層鑲嵌製程， 19 95820 其係 的， 中介 發明 用來說明本發明之實用性， 包含其他的雙層鑲嵌製程與 於兩個介電層之間較佳的蝕 之製程亦可以運用到這些製 其他許多的製程同樣是熟知 其他的非雙層鑲嵌製程，其 刻選擇比是需要的。因此本 程中。 及說明，但對 蓋，其並不脫 雖然不同的實施例，在此特別的加以描述 於本發明之修改與變更，均為以上所教示與涵 離本發明所附之申請專利範圍之範圍與精神。 ’包含伴隨的 均可以任何方 在本發明之說明書中所揭露之所有的特徵 摘要以及圖示，及/或任何方法與製程的步驟， 式加以結合，除非此結合彼此互相排斥。 在本發明之說明書中（包含任何所附之申請專利範圍摘 要以及圖示）之每一揭露之特徵，可以被另一相等或者相似目 的之特徵來取代，以提供相等或相似的目的，除非明確的說 明不同，因此，除非明確的說明不同，每一被揭露之特徵， 均為一均等或相似特徵系列的一實施例。 【圖式簡單說明] 為讓本發明之上述和其他目的、特徵、和優點能更明顯 易懂’特舉較佳實施例，並配合下列圖式做更詳細說明，其 中： 第1 A-1 F圖係為習知的雙層鑲嵌製程之部分剖面示意 圖； 第2A-2B圖係為本發明之一實施例之蝕刻製程之之部 分剖面示意圖；以及 20 1295820 第3A-3H圖係為本發明之一實施例之雙過鑲嵌製程之 部分剖面示意圖。 【元件代表符號簡單說明】 10 底層 12 (下方）終止層 14 (下方）介電層 16 (上方）終止層 20 (上方）介電層 44 第一光阻層 46 光罩開口 50 延伸介層孔 50, 介層孔 52 上表面 56 第二光阻層 58 光罩開口 62 溝渠 64 上表面 68 上表面 70 上表面 72 金屬 74 内連線 76 介層孔 208 下方介電層 210 上方介電層 210t 溝渠 214 光罩層 401 底層 402 區域 404 介電區域 406 餘刻終止層 408 介層孔介電層 408v (延伸的）介層孔 410 溝渠介電層 410t 溝渠 410s 上表面 412 光罩層 412a 開口 414 光罩層 414a 開口 416 金屬
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Claims (1)

1295820 十、申請專利範圍： 1. 一種蝕刻一介電結構的方法，至少包含： 提供一介電結構，其至少包含（a)未摻雜之氧化矽 氟之氧化矽的一第一介電層；以及（b)摻雜碳氫之氧化 第二介電層，該第二介電層係設置於該第一介電層上 及 進行一電漿餘刻以餘刻該介電結構’其中該電漿 括使用包含有氮原子與氟原子之一電漿源氣體，其中 介電層係相對於該第一介電層而選擇性地於該電漿 被蝕刻，且其中該電漿蝕刻係避免在該第一介電層及 介電層之間置入一蝕刻終止層之需求。 2. 如申請專利範圍第1項所述之方法，其中上述 源氣體包含一氣體物種，該氣體物種包含一或多個氮 一或多個II原子。 3. 如申請專利範圍第2項所述之方法，其中上述 物種係為三氟化氮（NF3)。 4. 如申請專利範圍第1項所述之方法，其中上述 源氣體包含（a) —包含一或多個氮原子之氣體物種； 一包含一或多個氟原子之氣體物種。 5. 如申請專利範圍第4項所述之方法，其中上述 或摻雜 矽的一 方；以 餘刻包 該第二 餘刻中 該第二 之電漿 原子與 之氣體 之電漿 以及（b) 之電漿 22 1295820 源氣體包含一氮氣（N2)與一碳氟化合物（Fluorocarbon)氣體。 6.如申請專利範圍第5項所述之方法，其中上述之碳氟 化合物氣體係為四氟化碳（CF4)。 7 ·如申請專利範圍第1項所述之方法，其中上述之第一 介電層係為一未摻雜之二氧化矽（Silic〇n Dioxide)層。 8.如申請專利範圍第1項所述之方法，其中上述之第一 介電層係為一氟化石夕玻璃（Fluorinated Silica Glass)層。 9·如申請專利範圍第1項所述之方法，其中上述之電漿 触刻&供 第一介電層·第一介電層之選擇比（selectivity) 為2 · 5 : 1或更大。 10·如申請專利範圍第1項所述之方法，其中上述之電漿 蝕刻提供一第二介電層：第一介電層之選擇比為3:1或更 大0 11·如申請專利範圍第1項所述之方法，其中上述之電漿 蝕刻係於一磁性輔助反應性離子蝕刻系統（MagnetiCally Enhanced Reactive Ion Etching System)中實施 〇 12·—種在一雙層鑲崁（dual damascene )結構中餘刻一 23 1295820 溝渠的方法，其中該方法至少包含： 提供一雙層鑲崁結構，該結構至少包含（a) —底層 (Underlying Layer); (b)未摻雜之氧化石夕或摻雜氟之氧化石夕的 一介層孔介電層，係覆蓋於該底層之上方；（c)摻雜碳氫之氧 化矽的一溝渠介電層，係覆蓋於該介層孔介電層之上方；以 及（d)—圖案化之光罩層，係覆蓋於該溝渠介電層之上方；以 及 藉由電漿蝕刻而透過該圖案化之光罩層上的複數個開 口而在該溝渠介電層中蝕刻一或多個溝渠，直到該介層孔介 電層之一上表面之一部分暴露出，其中該電漿蝕刻包括利用 一包含有氮原子與氟原子之電漿源氣體’且其中該溝渠介電 層係相對於該介層孔介電層而選擇性地於該電漿蝕刻中被 ϋ刻。 13. 如申請專利範圍第12項所述之方法’其中上述之雙 層鑲嵌結構包含一延伸介層孔，其延伸穿過該溝渠介電層與 該介層孔介電層。 14. 如申請專利範圍第12項所述之方法，其中上述之電 漿源氣體包含一氣體物種，該氣體物種包含至少一氮原子與 至少一氟原子。 15. 如申請專利範圍第14項所述之方法，其中上述之氣 體物種係為三氟化氮（NF3)。 24 1295820 16.如申請專利範圍第I]項所述之方法，其中上述之電 裝源氣體包含（a)—包含一或多個氮原子之氣體物種；以及（b) 包含一或多個氟原子之氣體物種。 17·如申請專利範圍第16項所述之方法，其中上述之電 襞源氡體包含一氮氣（N2)與一碳氟化合物（Fluorocarbon)氣 13A 體0 18·如申請專利範圍第12項所述之方法，其中上述之介 層孔介電層係為一未摻雜之二氧化石夕（Silicon Dioxide)層。 19·如申請專利範圍第12項所述之方法，其中上述之介 層孔介電層係為一氟化矽玻璃（Fluorinated Silica Glass)層。 20·如申請專利範圍第12項所述之方法，其中上述之電 聚姓刻提供一溝渠介電層：介層孔介電層之選擇比為3, : 1 或更大。 21. 如申請專利範圍第12項所述之方法，其中上述之電 漿#刻係於一磁性辅助反應性離子蚀刻系統（Magnetically Enhanced Reactive Ion Etching System)中實施。 22. 如申請專利範圍第1項所述之方法，其中摻雜碳氫之 25 1295820 氧化矽的該第二介電層係利用一電漿辅助化學氣相沉積製 程來形成。 2 3.如申請專利範圍第12項所述之方法，其中摻雜碳氫 之氧化矽的該溝渠介電層係利用一電漿輔助化學氣相沉積 製程來形成。 26 1295820 七、指定代表圖·· (一） 、本案指定代表圖為：第 3H 圖。 (二） 、本代表圖之元件代表符號簡單說明： 401 底層 402 區域 404 介電區域 406 餘刻終止層 408 介層孔介電層 410 溝渠介電層 410s 上表面 416 金屬 八、本案若有化學式時，請揭示最能顯示 發明特徵的化學式：
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