CN1322560C - 用于选择性地蚀刻电介质层的工艺 - Google Patents

用于选择性地蚀刻电介质层的工艺 Download PDF

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CN1322560C
CN1322560C CNB028280148A CN02828014A CN1322560C CN 1322560 C CN1322560 C CN 1322560C CN B028280148 A CNB028280148 A CN B028280148A CN 02828014 A CN02828014 A CN 02828014A CN 1322560 C CN1322560 C CN 1322560C
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dielectric layer
etching
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silicon oxide
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CN1618121A (zh
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C-L·谢
J·袁
H·陈
T·帕纳格普洛斯
Y·叶
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Abstract

提供一种用于蚀刻电介质结构的方法。该电介质结构包括：(a)一层未掺杂的氧化硅或F-掺杂的氧化硅；和(b)一层C，H-掺杂氧化硅。在等离子体蚀刻步骤中，蚀刻该电介质结构，其中利用包含氮原子和氟原子的等离子体源气体进行该等离子体蚀刻步骤。作为一个实例，等离子体源气体可以包括包含一种或多种氮原子和一种或多种氟原子的气体物质(例如NF3)。作为另一个实例，该等离子体源气体可以包括(a)包含一种或多种氮原子的气体物质(例如N2)和(b)包含一种或多种氟原子的气体物质(例如CF4气体)。在该蚀刻步骤中，相对于未掺杂氧化硅或F-掺杂氧化硅层，优先蚀刻C，H-掺杂氧化硅层。例如本发明的方法可适用于双镶嵌结构。

Description

用于选择性地蚀刻电介质层的工艺
技术领域
本发明涉及用于例如在双镶嵌工艺情况中选择性地蚀刻电介质层的工艺。
背景技术
制造半导体集成电路的技术不断提高可以在单个集成电路芯片上制造的晶体管、二极管、电容器和/或其它电子器件的数量。这主要通过减小最小特征尺寸来实现这种集成度的提高。
先进集成电路包含通过各电介质层与半导体衬底分离且彼此相分离的多层互连层。例如，诸如出现在微处理器中的逻辑电路需要插入有电介质层的数个互连层。水平互连层形成在电介质层上然后被另一电介质层覆盖。小触点或通路孔需要贯穿每个电介质层蚀刻以连接互连层。
可采用几种技术来制造互连线和通路。一种这样的技术包括通常称之为“双镶嵌工艺”的工艺。该工艺包括形成沟槽和下层通路孔，在其上沟槽和通路孔由导电材料填充，同时形成互连线和下层通路。
下面参考图1A-1F描述来自U.S.专利No.6211092的一种特殊的双镶嵌工艺，其全部公开内容并入这里以作参考。形成包括下述层的蚀刻结构：(a)下层10；(b)薄下停止层(stop layer)12；(c)下电介质层14；(d)薄上停止层16和(e)上电介质层20。停止层12、16具有相对于电介质层14、20的成份，以便选择蚀刻工艺贯穿上面的电介质层蚀刻但停止在停止层上。
现有技术公知的用于电介质层14、20的材料的实例包括掺杂和未掺杂的氧化硅材料。未掺杂的氧化硅材料通常分子式为SiOx，其中x在1.4与2.1之间，二氧化硅(其中x近似2)最为普遍。掺杂氧化硅材料为含硅、氧和一种或多种附加组分。这些层例如可以通过化学气相沉积(CVD)或等离子体增强化学气相沉积(PECVD)生长。
氮化硅通常为停止层材料而电介质为氧化硅材料。氮化硅例如可以通过CVD或PECVD生长。
沉积并光刻图案化第一光阻层(photoresist layer)44以形成相应于通路孔的掩模孔46，图中仅示出其中一个。值得注意的是，下层10通常包括电介质和金属区，金属区存在于孔区域中。
在第一蚀刻步骤中，如图1B中示出，贯穿上电介质层20、上停止层16和下电介质层14向下蚀刻延长的通路孔50至下停止层12。选择有选择性的蚀刻化学性以便蚀刻停止在下停止层12的上表面52。例如，在第一步骤中，可以使用非选择性定时蚀刻来穿过下电介质层20、上淡化物停止层16和贯穿下电介质层14的部分路径来蚀刻通路孔50。第二蚀刻步骤在具有良好的氧化物与淡化物比的情况下，随后即可使用以选择性地蚀刻贯穿下电介质层14的余下路径并停止在下停止层12的上表面52，完成延长的通路孔50。
在未示出的步骤中，剥除第一光阻层44。然后，如图1C中示出，沉积第二光阻层56并将其光刻图案化以形成相应于沟槽的掩模孔58。在图1D中示出的随后的蚀刻步骤中，贯穿上电介质层20向下蚀刻沟槽62至上停止层16的上表面64。由此有效地减小延长的通路孔50的深度以形成通路孔50’。
在进一步的蚀刻步骤中，如图1E中所示，贯穿下停止层12向下蚀刻通路孔50’底部的下停止层12的暴露部分到下层10的上表面68，该暴露部分至少在通路孔50’的位置通常为金属表面。取决于两停止层12、16的成份，该蚀刻步骤除去暴露在沟槽62底部的上停止层16的部分以暴露下电介质层14的上表面70。在该蚀刻步骤之前或之后执行的另一步骤中，将第二光阻层56与电介质蚀刻中形成的任何侧壁聚合物一起剥除。
其后，如图1F中所示，将金属72填充到沟槽62和下面的通路孔50’中，以接触下层10的上表面68。随后，化学机械抛光(CMP)除去溢出沟槽的任何金属。金属72形成水平互连线74以及接触下层10的通路76。金属72优选为铜，但可以为其它金属，诸如铝。然而，双镶嵌工艺特别适用于铜金属化，因为需要无铜蚀刻。
一般理想地，在双镶嵌结构内使用的非金属材料的介电常数k尽可能地低。例如，减小的介电常数k导致减小的电容，这将减小串话干扰和耦合，可以提高工作速度。但是，通常用于连接停止层12、16的材料(例如氮化硅)为介电常数k相对较高的材料。例如，Si3N4的介电常数k为大约7.5。(与此相比较，例如，二氧化硅的介电常数k通常在3.9与4.2之间)。
因此，在双镶嵌结构领域中需要减小这种较高介电常数k材料的不利影响。
发明内容
通过本发明来解决当前集成电路电介质蚀刻工艺的上述及其它困难。
根据本发明的实施例，提供一种用于蚀刻电介质结构的方法。该电介质结构包括：(a)未掺杂氧化硅或F-掺杂氧化硅的第一电介质层和(b)C，H-掺杂氧化硅的第二电介质层。然后在等离子体蚀刻步骤中蚀刻此电介质结构，该等离子体蚀刻步骤利用包括氮原子和氟原子的等离子体源气体进行。在该蚀刻步骤中，相对于第一电介质层选择蚀刻第二电介质层，提供例如2.5∶1或更大的、更为优选的3∶1或更大的第二电介质层比第一电介质层的选择性(selectivity)。
根据本发明的另一个实施例，提供一种用于在双镶嵌结构中蚀刻沟槽的方法。该双镶嵌结构包括：(a)下层；(b)在下层上的未掺杂氧化硅或F-掺杂氧化硅的通路电介质层；(c)在通路电介质层上的C，H掺杂氧化硅的沟槽电介质层；和(d)在沟槽电介质层上的图案化掩模层(patterned masking layer)。双镶嵌结构还优选包括穿过沟槽电介质层和通路电介质层延伸的延长的通路孔。然后通过等离子体蚀刻步骤，在沟槽电介质层内，蚀刻一个或多个沟槽。穿过形成在图案化掩模层中的孔进行蚀刻，蚀刻持续到暴露通路电介质层的上表面部分为止。利用包括氮原子和氟原子的等离子体源气体进行等离子体蚀刻步骤。类似于前面段落中的实施例，相对于通路电介质层优选地选择蚀刻沟槽电介质层，提供例如2.5∶1或更大的、更为优选的3∶1或更大的沟槽电介质层比通路电介质层的选择性。
在一些实施例中，等离子体源气体将包括包含一种或多种氮原子和一种或多种氟原子的气体物质(例如NF3)。在另一实施例中，等离子体源气体会包括：(a)包含一种或多种氮原子的气体物质(例如氮气，N2)和(b)包含一种或多种氟原子的气体物质(例如诸如CF4的碳氟化合物气体)。
未掺杂氧化硅层优选为二氧化硅层，而F-掺杂氧化硅层优选为氟化硅酸盐玻璃层。
在一些实施例中，在磁性增强反应离子蚀刻系统中进行等离子体蚀刻步骤。
本发明的一个优点是可以相对于未掺杂氧化硅电介质层和F-掺杂氧化硅电介质层优先蚀刻C，H-掺杂氧化硅电介质层。
本发明的另一个优点是可以从公知的双镶嵌结构中，消除具有相对较高的介电常数的蚀刻停止层。结果，减小该结构的电容。这将减小串话干扰和耦合，可以提高器件的工作速度。
通过阅读下述详细说明和所附权利要求，本发明的上述和其它实施例以及优点对于所属技术领域普通技术人员而言将变得显而易见。
附图说明
图1A-1F示出现有技术公知的双镶嵌工艺的示意性的局部剖视图。
图2A-2B示出根据本发明实施例的蚀刻工艺的示意性的局部剖视图。
图3A-3H示出根据本发明实施例的双镶嵌工艺的示意性的局部剖视图。
具体实施方式
作为详细说明的前序，应该注意的是，所有列出的气体成份百分比(％)为体积百分比，且所有列出的气体成份比为体积比。
术语“选择性”用来指a)两种或多种材料的比，和b)当一种材料的蚀刻速率与另一种材料相比增加时，蚀刻期间获得的条件。
下面参考附图更加全面地描述本发明，其中示出本发明示例性的实施例。然而，本发明可以以不同形式体现且不应该被限制为这里阐述的实施例。
下面结合图2A和2B描述根据本发明的实施例的工艺。参考图2A，其示出包括下电介质层208、上电介质层和图案化掩模层214的结构。下电介质层208由诸如二氧化硅(通常由四乙基正硅酸盐形成，还称之为TEOS)的氧化硅或例如氟化硅酸盐玻璃(FSG)的氟-掺杂氧化硅构成。如上面提及的，二氧化硅的介电常数k通常在3.9与4.2之间。而氟化硅酸盐玻璃的介电常数k大约为3.5。由于该原因，在一些情况中氟化硅酸盐玻璃比二氧化硅更优选。下电介质层208可以为适合于将要进行的应用的任何适合厚度，并且，例如，其可以利用现有技术公知的CVD工艺形成。
在下电介质层208上提供上电介质层210。本实施例中的上层为掺杂有碳和氢的氧化硅(下文中称之为“C，H-掺杂氧化硅”)。上层210可以为适合于将要进行的应用的任何适合厚度。Yau等人最近已经在U.S.专利No.6054379和No.6072227中描述了形成这种氧化的碳-硅材料的方法，这里将其全文并入以作参考。这种膜还在U.S专利No.6168726中进行了描述，将其全部公开内容并入以作参考。优选利用化学气相沉积(CVD)工艺，采用有机硅烷和氧化剂前体气体(precursor)制造该层，以形成介电常数在2.5至3之间的低k电介质。优选在具有低于1W/cm2的晶片上的功率密度的低功率电容性耦合等离子体中，并且在低于100℃的温度下进行CVD工艺。优选的氢含量为至少30at.％(原子百分比)，更为优选的在45与60at.％(原子百分比)之间，优选的碳含量在5与20at.％之间，更为优选地在6与10at.％之间，优选的硅含量在15与30at.％之间，更为优选地在17与22at.％之间，且优选的氧含量在10与45at.％之间，更为优选地在15与30at.％之间。C，H-掺杂氧化硅材料目前由加利福尼亚州圣克拉拉市的应用材料有限公司以Black DiamondTM商标名出售。
在上层210上提供图案化掩模层214。图案化掩模层214优选为有机光阻层。图案化掩模层214可以为适合于在随后的蚀刻工艺期间保持掩模层214存在的任何厚度，其中蚀刻图2A的结构以形成如图2B中示出的沟槽210t。
可以在任何适合的等离子体处理设备中进行本发明的蚀刻工艺，例如反应离子蚀刻(RIE)设备。传统的反应离子蚀刻设备包含在真空室内的阳极和阴极，阴极一般由室内的用于支撑半导体晶片的基座形式形成，而阳极通常由室壁和/或室顶部形成。为了处理晶片，将等离子体源气体抽吸入真空室，并通过单正弦频率(RF)源驱动阳极和阴极，以将等离子体源气体激活为等离子体。虽然经常使用从100kHz至2.45GHz的频率，偶尔使用其它频率，但是单频通常为13.56MHz。RF功率激活等离子体源气体，在室内接近于要处理的半导体晶片产生等离子体。
等离子体处理设备还可以为磁性增强反应离子蚀刻(MERIE)设备。这种设备设置有一个或多个磁性控制等离子体以促进更均匀的蚀刻工艺的磁体或磁线圈。
用于本发明的特殊MERIE室为加利福尼亚州的圣克拉拉市的提供的eMaxTM室。
在该工艺步骤中使用的蚀刻化学物质优选基于包含氮原子和氟原子的等离子体源气体。如一个实例中，可以使用NF3气体。如另一实例中，可以使用(a)包含氮原子的气体物质和(b)包含氟原子的气体物质的混合物。例如，可以使用含有N2气体和一种或多种氟化碳气体(这里定义为含有碳和氟原子的气体)的混合物的等离子体源气体，更为优选地使用N2气体和仅含有碳和氟原子的诸如CF4气体、C2F6气体或C4F8气体的一种或多种氟化碳气体的混合物。
该蚀刻化学物质是有吸引力的，因为对于上电介质层获得良好的蚀刻速率(例如，可以获得一般大于0.5微米每秒，更为优选地大于1微米每秒的蚀刻速率)。
该化学物质是具有吸引力的，还因为其在上电介质层210与下电介质层208之间提供良好的选择性。该选择性通常为2.5∶1或更大，并且优选为3∶1或更大。作为该良好选择性的结果，下电介质层可以充当用于上电介质层蚀刻工艺的蚀刻停止层，以便于制造向图2B中示出那样的结构。
如一个具体的实例，通过在相对较低的功率下(例如＜500W，更为优选地大约300W)和相对较高的压力下(例如150毫托或更大)操作的存在有由N2气体和CF4气体组成的等离子体源气体的MERIE室中，蚀刻如图2A中示出的结构来获得可接受的选择性和蚀刻速率。
如另一具体实例，通过在相对较高的功率下(例如＞500W，更为优选地800至1200W)和相对较低的压力下(例如＜150毫托，更为优选地30-50毫托)操作的存在有NF3等离子体源气体的eMaxTM室中，蚀刻如图2A中示出的结构来获得可接受的蚀刻速率和选择性，其中NF3等离子体源气体优选以15至50sccm(标准立方厘米每分钟)的流速提供。例如将阴极温度保持在10-20℃。优选磁场范围在0-30高斯。这可以获得大于1微米每分钟的C，H-掺杂氧化硅蚀刻率和大于3∶1的C，H-掺杂氧化硅比氟化硅酸盐玻璃的选择性。
现在转向图3A至3H，这些附图表示本发明的工艺对其有用的具体的双镶嵌工艺。图3A示出包括下层401的双镶嵌结构。下层401通常包括电介质区404和导电区402，例如铜区。
在下层401上沉积蚀刻停止层406。蚀刻停止层406可以由适合用于氧化硅材料的蚀刻停止材料的任何材料形成，包括碳化硅或氮化硅(通常分子式为SiNx，其中x可以在例如1至1.5的范围内略微改变且通常为Si3N4)。蚀刻停止层406可以为适合用作蚀刻停止层的任何厚度，且在该实例中，其厚度为300至1000埃。例如可以利用本领域公知的CVD工艺形成蚀刻停止层。
在蚀刻停止层406之上提供通路电介质层408，在该实施例中，通路电介质层408由(a)例如二氧化硅的未掺杂氧化硅(通常由TEOS形成)或(b)例如氟化硅酸盐玻璃的氟掺杂氧化硅构成。如前所述，二氧化硅的介电常数k通常在3.9与4.2之间，而氟化硅酸盐玻璃的介电常数k大约为3.5。通路电介质层408可以为适合用作通路层的任何合适的厚度，且例如在该实例中厚度为3000至5000埃。
在通路电介质层408上提供沟槽电介质层410。在该实施例中沟槽电介质层410为在上面关于图2A描述过其成份、形成和性质的C，H-掺杂氧化硅。沟槽电介质层410可以为适合用作沟槽电介质层的任何适合厚度，且在该实例中，厚度为3000至5000埃。
在沟槽电介质层410上设置优选为有机光阻层的第一图案化掩模层412。与图案化掩模层412相关的厚度和孔412a的尺寸可以为适合于蚀刻通路孔的任何值。例如，该图案化掩模层可以为具有4000至7000埃厚度和0.2至0.5微米孔的有机光阻层。
一旦建立了图3A的结构，然后使其经历蚀刻步骤，其中蚀刻延长的通路孔408v向下至停止层406，如图3B中所示。
如上所述，可以在任何适合的等离子体处理设备中进行该蚀刻工艺，例如，诸如MERIE室的等离子体增强反应离子蚀刻系统。用于该工艺步骤的蚀刻化学物质实质上可以为任何公知用于蚀刻相对于蚀刻停止层406具有良好选择性的硅酸盐基材料蚀刻化学物质。用于该工艺步骤的示例性蚀刻化学物质为那些基于含氟气体的物质，更为优选地为基于例如CH3F气体的氟化烃气体(这里限定为包含碳、氢和氟原子的气体)的物质。在蚀刻后，制造出图3B示出那样的结构。然后剥除该图案化掩模层412，制造出图3C中示出的结构。
随后，在图3D中示出的结构上，提供第二图案化掩模层414。例如第二图案化掩模层414为有机光阻层。与该图案化掩模层414相关的厚度和孔414a的尺寸可以为适合于蚀刻互连沟槽的值。例如，图案化掩模层可以为具有4000至7000埃厚度和0.2至0.5微米孔径的有机光阻层。
现在转向图3E，利用相对于通路电介质层408选择蚀刻沟槽电介质层410的蚀刻工艺在沟槽电介质层410中蚀刻沟槽410t。如上面关于图2B所讨论的，在任何适合的等离子体处理设备中进行蚀刻工艺，在该工艺中使用的蚀刻化学物质优选基于包含氮原子和氟原子的等离子体源气体(例如，NF3等离子体源气体或包含N2气体和一种或多种氟化碳气体的等离子体源气体)。利用该设备和蚀刻化学物质，可以相对于通路绝缘层408以3∶1或更大的选择性蚀刻沟槽电介质层410，而同时以大于1微米每分钟的速率蚀刻沟槽绝缘层410。
如上面关于图1讨论的，虽然这里不存在，但是现有技术中通常使用诸如氮化硅的材料作为沟槽电介质层与通路电介质层之间的蚀刻停止层以避免诸如拐角面(corner faceting)、微沟槽(micro-trenching)和蚀刻速率微载荷(micro-loading)的问题。然而，因为氮化硅具有相当高的介电常数k(例如Si3N4的介电常数为大约7.5)，其从本结构消除是有利的。如在开篇段落里描述的，在本发明中可以以大于1微米每分钟同时获得3∶1或更大选择性来蚀刻沟槽电介质层410。结果，可以除去存在于沟槽电介质层与通路电介质层之间蚀刻停止层，而不遭受显著的拐角平面、微开槽和蚀刻速率微载荷。
(从图3E可以看出掩模层414材料在先前在通路电介质层408中蚀刻的通路孔408v内的存在有助于保持通路电介质层408肩部区域的完整性。)
在沟槽蚀刻步骤之后，剥除第二图案化掩模层414的剩余部分，以提供如图3F中示出的结构。
然后进行进一步的蚀刻步骤以除去存在于通路孔408v底部的蚀刻停止层406并由此提供至下面金属区402的通道。实现该目的的蚀刻化学物质是现有技术中公知的。例如，可以选择使用包含氟化烃(例如，CHF3、CH2F2、CH3F)、N2、O2和可选的氩的蚀刻化学物质。该最终结构在图3G中示出。
在金属化工艺中，如现有技术公知的用金属416(一般为铜)填充沟槽410t和通路孔408v。金属化工艺需要用阻挡层和润湿层涂敷沟槽410和通路孔408v，如已经在先进集成电路中的小特征金属化中公知的。一般在通常至少部分通过物理汽相沉积来进行的金属沉积工艺中填充沟槽410t和通路孔408v。通常持续填充直到金属完全填满通路孔408v和沟槽410t，并且有一些还覆在上表面410s上。然后通常进行化学机械抛光。由于氧化硅基材料比金属硬，当遇到沟槽电介质层410上表面410s时抛光基本停止。
虽然图3A至3H示出本发明对其有用的特定双镶嵌工艺，还包括公知的其它双镶嵌工艺和其它非镶嵌工艺的大量工艺，其中需要在两电介质层之间良好的蚀刻选择性。因此本发明的工艺也适用于这些工艺。
虽然本文具体示出并描述了各种实施例，应该意识到本发明的修改和变形由上述教导覆盖，并且落在附属权利要求的范围内，而不脱离本发明的精神和保护范围。
在本说明书中公开的所有特征(包括所附的权利要求书、摘要和附图)和/或公开的方法或工艺的所有步骤可以以任何组合方式进行组合，除了至少一些特征和/或步骤互相排斥的组合外。
在本说明书中公开的每一特征(包括所附的权利要求书、摘要和附图)可以由用于相同等效的或相似目的的选择特征替换，除非另外清楚地描述。因此，除了另外清楚地描述，所公开的每一特征仅是等效或相似特征的组类的一个实例。

Claims (24)

1、一种蚀刻电介质结构的方法，包括：
提供电介质结构，该电介质结构包括：(a)未掺杂氧化硅或F-掺杂氧化硅的第一电介质层；和(b)在所述第一介电层之上的C，H-掺杂氧化硅的第二电介质层；以及
执行等离子体蚀刻以蚀刻所述电介质结构，其中所述等离子体蚀刻包括利用等离子体源气体，所述等离子体源气体包括氮原子和氟原子；并且其中在所述等离子体蚀刻中，相对于所述第一电介质层，选择性地蚀刻所述第二电介质层，所述等离子体蚀刻避免在所述第一和第二电介质层之间插入蚀刻停止层的需要。
2、根据权利要求1所述的方法，其中所述等离子体源气体包括气体物质，所述气体物质包含一种或多种氮原子和一种或多种氟原子。
3、根据权利要求2所述的方法，其中所述气体物质为NF3。
4、根据权利要求1所述的方法，其中所述等离子体源气体包括(a)包含一种或多种氮原子的气体物质和(b)包含一种或多种氟原子的气体物质。
5、根据权利要求4所述的方法，其中所述等离子体源气体包括N2和氟化碳气体。
6、根据权利要求5所述的方法，其中所述氟化碳气体为CF4。
7、根据权利要求1所述的方法，其中所述第一电介质层为未掺杂二氧化硅层。
8、根据权利要求1所述的方法，其中所述第一电介质层为氟化硅酸盐玻璃层。
9、根据权利要求1所述的方法，其中所述等离子体蚀刻以至少2.5倍于蚀刻所述第一电介质层的速率蚀刻所述第二电介质层。
10、根据权利要求1所述的方法，其中所述等离子体蚀刻以至少3倍于蚀刻所述第一电介质层的速率蚀刻所述第二电介质层。
11、根据权利要求1所述的方法，其中所述等离子体蚀刻在磁性增强反应离子蚀刻系统内进行。
12.根据权利要求1所述的方法，其中C，H-掺杂氧化硅的所述第二电介质层是利用等离子体辅助的化学气相沉积工艺形成的。
13.根据权利要求1所述的方法，其中C，H-掺杂氧化硅层的所述沟槽电介质层是利用等离子体辅助的化学气相沉积工艺形成的。
14、一种在双镶嵌结构中蚀刻沟槽的方法，所述方法包括：
提供双镶嵌结构，该双镶嵌结构包括：(a)下层，(b)在所述下层上的未掺杂氧化硅或F-掺杂氧化硅的通路电介质层，(c)在所述通路电介质层上的C，H-掺杂氧化硅的沟槽电介质层，和(d)在所述沟槽电介质层上的图案化掩模层；以及
在等离子体蚀刻中，穿过所述图案化掩模层中的孔，在所述沟槽电介质层中，蚀刻一个或多个沟槽，直到暴露所述通路电介质层的部分上表面，其中利用包含氮原子和氟原子的等离子体源气体来进行所述等离子体蚀刻，并且其中，在所述等离子体蚀刻中，相对于所述通路电介质层，选择性地蚀刻所述沟槽电介质层。
15、根据权利要求14所述的方法，其中所述双镶嵌结构包括贯穿所述沟槽电介质层和所述通路电介质层延伸的延长的通路孔。
16、根据权利要求14所述的方法，其中所述等离子体源气体包括气体物质，所述气体物质包含至少一种氮原子和至少一种氟原子。
17、根据权利要求16所述的方法，其中所述气体物质为NF3。
18、根据权利要求14所述的方法，其中所述等离子体源气体包括(a)包含一种或多种氮原子的气体物质和(b)包含一种或多种氟原子的气体物质。
19、根据权利要求18所述的方法，其中所述等离子体源气体包括N2和氟化碳气体。
20、根据权利要求14所述的方法，其中所述通路电介质层为未掺杂二氧化硅层。
21、根据权利要求14所述的方法，其中所述通路电介质层为氟化硅酸盐玻璃层。
22、根据权利要求14所述的方法，其中所述等离子体蚀刻以至少3倍于蚀刻所述第一电介质层的速率蚀刻所述第二电介质层。
23、根据权利要求14所述的方法，其中所述等离子体蚀刻在磁性增强反应离子蚀刻系统内进行。
24.根据权利要求14所述的方法，其中C，H-掺杂氧化硅层的所述沟槽电介质层是利用等离子体辅助的化学气相沉积工艺形成的。
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