TWI292614B - Flip chip on leadframe package and method of making the same - Google Patents

Flip chip on leadframe package and method of making the same Download PDF

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Publication number
TWI292614B
TWI292614B TW095102294A TW95102294A TWI292614B TW I292614 B TWI292614 B TW I292614B TW 095102294 A TW095102294 A TW 095102294A TW 95102294 A TW95102294 A TW 95102294A TW I292614 B TWI292614 B TW I292614B
Authority
TW
Taiwan
Prior art keywords
bumps
bump
lead frame
wafer
flip chip
Prior art date
Application number
TW095102294A
Other languages
English (en)
Other versions
TW200729445A (en
Inventor
Meng Jen Wang
Chien Liu
Tsan Sheng Huang
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW095102294A priority Critical patent/TWI292614B/zh
Priority to US11/636,995 priority patent/US7425468B2/en
Publication of TW200729445A publication Critical patent/TW200729445A/zh
Application granted granted Critical
Publication of TWI292614B publication Critical patent/TWI292614B/zh

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10135Alignment aids
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/1147Manufacturing methods using a lift-off mask
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/1181Cleaning, e.g. oxide removal step, desmearing
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
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    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009Pre-treatment of the bump connector or the bonding area
    • H01L2224/8101Cleaning the bump connector, e.g. oxide removal step, desmearing
    • H01L2224/81011Chemical cleaning, e.g. etching, flux
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    • H01L2224/8112Aligning
    • H01L2224/81136Aligning involving guiding structures, e.g. spacers or supporting members
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    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112Aligning
    • H01L2224/81136Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/81139Guiding structures on the body
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    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81194Lateral distribution of the bump connectors
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    • H01L2224/812Applying energy for connecting
    • H01L2224/8121Applying energy for connecting using a reflow oven
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    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • H01L2224/81815Reflow soldering
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
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    • H01L2924/01082Lead [Pb]
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    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

1292614 九、發明說明: 【發明所屬之技術領域】 本發明係關於一種封裝結構及其製造方法,咩4 "丁 5之,係 關於一種具有覆晶結構封裝結構及其製造方法。 【先前技術】 參考圖1至圖6,顯示習用導線架型覆晶封裝結構之掣造 方法之示意圖。首先,參考圖1,提供一 守線架 (leadframe)lO,該導線架1〇具有複數個内引腳( — a lead)l 1,每一内引腳Π具有一第一表面J i」及_第—老面 112。接著,參考圖2,提供一晶片12,該晶片12具有二主 動面12〗。且於該晶片12之主動面121上形成複數個凸塊 1 3,其中每一該等凸塊〗3之體積與高度大致上皆相同。接 著,參考圖3,將該等凸塊13之頂端浸入一助銲劑μ中, 使該等凸塊13沾附該助銲劑14。接著,參考圖*,將該等 凸塊13接觸對應之内引腳π之第一表面lu。接著,參考 圖5,進灯一迴銲步驟,使該等凸塊i 3溶融而接合於該内 引腳II之表面⑴。最後,參考圖6,形成—封膠材料 15,以包覆該等内引腳u之第—表面lu、該晶片12及該 等凸塊1 3 ’以形成一導線架型覆晶封裝結構1。 該製造方法之缺點如下,在圖5所示之迴銲過程中,該 等凸塊13會因熔融軟化而無法支撐該晶片】2,因而無法有 效地控制該晶片]2之主動面121與該内引腳u之第一表面 1】1間之間距,使得該晶片12容易發生坍塌而壓壞該等凸 塊1 3,造成覆晶接合之效果變差。 104364.doc 1292614 因此,有必要提供一種創新且具進步 及封裝方法,以解決上述問題。 似構 【發明内容】 本發明之主要目的在於提供一 曰κ t,π々 種谈晶接合方法,其係於 之第-八抽π 見之位置外另外再形成材質相同 = 塊’该弟二凸塊之高度小於該等第—凸塊,因此 不冒沾附到助銲劑,因而在迴銲過程中該第二凸塊會 原外形,可用以保持晶片與載體間之間距。因而該等第— 凸塊不會坍塌,可增加覆晶接合之良率。 本發明之另一目的在於接徂 如 挺供一種導線架型覆晶封裝結槿 之製造方法’包括以下步驟: 丨(二)提供一導線架’該導線架具有複數個内引腳(inner 丨’’每-内引腳具有一第一表面及—第二表面; (b)提供一晶片,該晶片具有一主動面; 一⑷於該晶片之主動面上形成複數個第—凸塊及至少—第 :凸塊’該第二凸塊之材質係與該等第—凸塊相同,且該 第一凸塊之高度係小於該等第一凸塊之高度; ⑷將該等凸塊之頂端浸人—助銲劑中^該等第—凸 塊沾附該助銲劑’而該第二凸塊未沾附該助鲜劑; ⑷將該等第—凸塊接觸對應之内引腳之第-表面;及 (外)進订迴h ’使該等第一凸塊熔融而接合於該等内弓I腳 之第—表面,而該第二凸塊未熔接於該内引腳之第—表面 以保持該晶片之主動面與該内引腳之第—表面間之間距。 本么明之又-目的在於提供一種導線架型覆晶封裝結 I04364.doc 1292614 構,其包括一導線架、一晶 有极數個内引腳,每》内引 面。該晶片具有一主動面, 及至少一第二凸塊,該等第 之第一表面。該第二凸塊之 該第一凸塊係接觸該内引腳 主動面與該内引腳之第一表 以包覆該等内引腳之第一表 該第二凸塊。 【實施方式】 片及一封膠材料。該導線架具 腳具有一第一表面及一第二表 該主動面具有複數個第一凸塊 凸塊係接合於對應之内引腳 材質係與該等第一凸塊相同, 之第一表面用以保持該晶片之 面間之間距。該封膠材料係用 面、該晶片、該等第一凸塊及 ,蒼考圖7至圖! 6 ’顯示本發明導線架型覆晶封裝結構之 製造方法之示意圖。首先,參考圖7,提供一導線架2〇, 該導線架20具有複數個内引腳(inner lead)21,每一内引腳 21具有一第一表面211及一第二表面2丨2。接著,參考圖 8 $疋七、日日片22 ’該晶片22具有一主動面22 1。接著,參 考圖9 ’形成一光阻層23於該晶片22之主動面22ι。且形成 複數個第一開口 24及至少一第二開口 25於該光胆層23上, 其中該等第一開口 24之開口面積大於該第二開口 25之開口 面積。接著,參考圖10,填入一金屬26至該等第一開口 Μ 及该第二開口 25中。亦即,該等第一開口 24及該第二開口 25係填入同一材質之金屬。接著,參考圖11,移除該光阻 層23。且進行迴銲,使該等第一開口 24内之金屬26形成複 數個第一凸塊27,且該第二開口 25内之金屬26形成一第二 凸塊28,其中該第二凸塊28之高度係小於該等第一凸塊27 104364.doc 1292614 同^即且該f二凸塊28之材質係與該等第-凸塊27相 點。在本一凸塊28與該等第-凸塊27具有相同之溶 ‘:。貫施例中,該第二凸塊28係為虛凸塊一 劑=:tt圖I㈣等第-凸塊27之項端浸入-助鲜 制,偻二:,忒寺弟一凸塊27之浸入之深度必須加以控 未、、占附:;寺第一凸塊2 7沾附該助銲劑2 9 ’而該第二凸塊2 8 助鲜劑29。接著’參考圖&將該等第一凸塊27 之内引腳21之第—表面21]。此時,該第二凸塊 、呵度較小,因此其並未接觸到該内引腳2】之第一 面2 1 1 〇 又 接者’麥考圖14’進行迴銲步驟,使該等凸塊_ 融:接合於該内引腳21之第一表面211。在本實施例中, 該等第一凸塊27係因助銲劑去除該等第一凸塊”内之氧化 :(圖中未示),使該等第一凸塊27得以完全熔融並共晶接 舍(emectic bonding)於該内引腳u之第一表面。該第二 凸塊28由於未沾附該助銲齊⑵,@此其表面之氧化層(圖 中未不)無法去除,致使該第二凸塊28在迴銲過程中被其 表面氧化層所包覆,而未能完全熔融接於該内引腳2丨上, 係接觸(contact)於該内引腳2:[之第一表面211。在迴銲過程 中,該等第一凸塊27會熔融軟化,因此該晶片22會略微下 P牛,直到忒第二凸塊2 8之底部接觸到該内引腳2】之第_表 面2 Π。该第二凸塊2 8與該内引腳2 1之第一表面2 1】間係為 冷接合(cold j〇int)。此外,由於該第二凸塊28不會完全熔 104364.doc -10- 1292614 融’因此,在迴銲過程中,該第二凸塊28會一直保持其外 形同時可用以保持該晶片22之主動面221與該内引腳^之 第一表面21 1間之間距,因而該等第一凸塊27不會坍塌, 可增加覆晶接合之良率。在本實施例中,經由該迴鲜過程 後,該等第一凸塊27大致上係為一梯型之外型,該第二凸 塊2 8大致上係為一圓形之外型。 參考圖15,顯示圖14之仰視圖。由圖中可看出,在本實 施例中,該第二凸塊28係與一第一凸塊27接觸同一内引= 2 1,且該第二凸塊28係位於四個角落。然而,可以理解的 疋,泫第二凸塊28之數目與位置並不限於如圖1 5所示,其 可以有多種其他之配置方式。 最後,參考圖16,形成一封膠材料3〇,以包覆該等内引 腳21之第一表面211、該晶片22、該等第一凸塊”及該第 二凸塊28,以形成一導線架型覆晶封裝結構2。 再參考圖1 6,顯示本發明導線架型覆晶封裝結構之剖視 示意圖。該導線架型覆晶封裝結構2包括一導線架2〇、一 晶片22及一封膠材料3〇。該導線架2〇具有複數個内引腳 21,每一内引腳21具有一第一表面211及一第二表面212。 該晶片22具有一主動面221,該主動面221具有複數個第一 凸塊27及至少一第二凸塊28,該等第一凸塊”係接合於對 應之内引腳2 1之第一表面2 !丨。在本實施例中,該等第一 凸塊27係共曰曰接合(eutectic b〇nding)於該内引腳2〗之第一 表面2 Π,且该等第一凸塊2 7大致上係為一梯型之外型。 該第二凸塊28之材質係與該等第一凸塊27相同,該第二凸 104364.doc 1292614 塊28係接觸該内引腳21之第一表面211用以保持該晶片22 之主動面22 1與該内引腳2 1之第一表面211間之間距。在本 實施例中,該第二凸塊28大致上係為一圓形之外型,且其 表面係具有一氧化層。該等第一凸塊27之體積大於該第二 凸塊28之體積,且該等第一凸塊27與該等内引腳21之第一 表面2 11之接觸面積大於該第二凸塊28與該等内引腳21之 第一表面2 1 1之接觸面積。在本實施例中,該第二凸塊μ 係與一第一凸塊27接觸同一内引腳21。該封膠材料3〇係用 以包覆該等内引腳21之第一表面21ι、該晶片22、該等第 一凸塊27及該第二凸塊28。 參考圖1 7 ’顯示本發明中另一種型式之導線架之示意 圖。本圖所示之導線架2 〇 a與圖1 5所示之導線架2 〇大致相 同,不同處僅在於本圖所示之導線架2〇a多了 一散熱接塾 (thermal pad)50之設置,該散熱接墊5〇係位於該晶片22&之 下,用以承接該晶片22a上之複數個第三凸塊27 1。其中該 等第三凸塊271可以是散熱凸塊,用以將該晶片22a所產生 之熱傳送至該散熱接墊50後再傳送出去;或是該等第三凸 塊27]也可以是接地凸塊,用以將該晶片22&之接地訊號傳 送至該散熱接墊5〇。 本發明另外關於一種覆晶方法。參考圖丨8至圖25,顯示 本發明覆晶方法之示意圖。首先,參考圖〗8,提供一載體 4 1 (例如一基板或一導線架),該載體4丨具有一第一表面4】! 及一第二表面4〗2。接著,參考圖19 ,提供一晶.片42,該 晶片42具有一主動面42]。接著,參考圖2〇,形成一光阻 1292614
層43於該晶片42之主動面421。且形成複數個第_開口 44 及至少一第二開口 45於該光阻層43上,其中該等第一開口 44之開口面積大於該第二開口 45之開口面積。接著,^考 圖21,填入一金屬46至該等第一開口料及該第二開口 c 中。亦即’該等第-開口 44及該第二開口 45係填入同一材 質之金屬。接著,參考圖22,移除該光阻層43。且進行迴 銲’使該等第一開口 44内之金屬46形成複數個第一凸塊 47’且該第二開口45内之金屬46形成一第二凸塊^,其中 該第二凸塊48之高度係小於該等第一凸塊47之高度,且該 第一凸塊48之材質係與該等第—凸塊47相同,#即,該第 一凸塊48與遠等第一凸塊47具有相同之溶點。在本實施例 中,該第二凸塊48係為虛凸塊(dummy bump)。 接著’苓考圖23,將該等凸塊47之頂端浸入一助銲劑49 中::時’該等第一凸塊47之浸入之深度必須加以控制, 使該寻第一凸塊47沾附該助銲劑49,而該第二凸塊48未沾 附該助銲劑49。接著,參考圖24,將該等第一凸塊47接觸 對應之载肢41之第—表面411。此時,該第二凸塊由於 同^軚小,因此其並未接觸到該載體41之第一表面411。 接者麥考圖25 ’進行迴銲步驟,使該等第一凸塊47完全 熔:而接合於該載體4 1之第-表面4 1 1。在本實施例中, ……凸塊47仏共晶接合(eutectic bonding)於該載體4 1 之第-表面川。而該第二凸塊判由於未沾附該助銲劑 ⑼,因此被其表面之氧化層所包覆而未完全炫融。在本實 施例中,命繁一 、 μ乐一凸塊48係接觸(contact)該載體41之第一表 104364.doc • 13 - 1292614 面4]]。在迴銲過程中,該等第一凸塊”會熔融軟化,因 此該晶片42會略微下降,直到該第二凸塊48之底部接觸到 4載版4 1之第一表面4 }!。此外,由於該第二凸塊μ不會 完全熔融,因此,在迴銲過程中,該第二凸塊48會一直: 持其外形同日可可用以保持該晶片42之主動面42〗與該載體 之第表面4 1 1間之間距。因而該等凸塊4 7不會坍搨, 可增加覆晶接合之良率。 惟上述實施例僅為說明本發明之原理及其功效,而非用 以限制本發明。因此,習於此技術之人士可在不違背本發 明之精神對上述實施例進行修改及變化。本發明之權利範 圍應如後述之申請專利範圍所列。 【圖式簡單說明】 圖]至圖6顯示習用導線架型覆晶封裝結構之製造方法之 示意圖;· 圖7至圖16顯示本發明導線架型覆晶封裝結構之製造方 法之示意圖; 圖〗7顯示本發明中另一種型式之導線架之示意圖;及 圖]8至圖25顯示本發明覆晶方法之示意圖。 【主要元件符號說明】 1 習用導線架型覆晶封裝結構 2 本發明導線架型覆晶封裝結構 10 導線架 1 1 内引腳 12 晶片 104364.doc 14 1292614 凸塊 助銲劑 封膠材料 導線架 導線架 内引腳 晶片 晶片 光阻層 第一開口 第二開口 金屬 第一凸塊 第二凸塊 助銲劑 封膠材料 載體 晶片 光阻層 第一開口 第二開口 金屬 第一凸塊 第二凸塊 I04364.doc 1292614 49 助 銲 劑 50 散熱接墊 111 内 引 腳 之 第 一 表 面 112 内 引 腳 之 第 二 表 面 121 晶 片 之 主 動 面 211 内 引 腳 之 第 一 表 面 212 内 引 腳 之 第 二 表 面 221 晶 片 之 主 動 面 271 第 二 凸 塊 411 載 體 之 第 一 表 面 412 載 體 之 第 二 表 面 421 晶 片 之 主 動 面 104364.doc

Claims (1)

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、申請專利範圍: , 一種導線架型覆晶封裝結構,包括: 一導線架,具有複數個内引腳(inner lead);及 w丄私囬丹,稷数個第一凸 塊及至少一第二凸塊, 寺弟—&塊係接合於對應之内 :腳,该弟二凸塊之材質係與該等第-凸塊相同,該第 -凸塊係接觸該内引腳用以保持 引腳間之間距。 《主動面與该内 2. 3. 如請求項1之導線架型覆晶封裝結構 係為虛凸塊(dummy bump)。 如請求項1之♦線架㈣曰曰曰封裝結構 料,用以包覆該等内引腳、該晶片、 第二凸塊。 ,其中該第二凸塊 ,更包括一封膠材 ϋ亥等第一凸塊及該 4. 6. 7. 如請求項卜之導線架型覆晶封裳結構, 係與該等第一凸塊之一接觸同—内引腳 如請求項I之導線架型覆晶封裝結構, 表面係具有一氧化層。 如請求項1之導線架型覆晶封裝結構, 塊之體積大於該第二凸塊之體積。 如請求項1之導線架型覆晶封裝結構, 塊與該等内引腳之接觸面積大於該第二 之接觸面積。 其中該第二凸塊 0 其中該第二凸塊 其中該等第一凸 其中該等第一凸 凸魏與該内引腳 8· 如請求項】之導線架型覆晶封裝結構 塊係共晶拉八广 · μ寺第一凸 接。(eutectic bonding)於該導線架,— ^)4364.(10( 1292614 塊係接觸(contact)該導線架。
如請求項】之導線架型覆晶封 塊大致上係為一梯型之外型, 圓形之外型。 裝結構,其中該等第一凸 该第二凸塊大致上係為一 其中該導線架更 如請求項1之導線架型覆晶封裝結構 包含一散熱接墊(thermal pad)。 包括以下步 種導線架型覆晶封裝結構之製造方法 驟: (a) 提供一導線架,該導線架具有複數個内引腳; (b) 長:供一晶片,該晶片具有一主動面; (c) 於該晶片之主動面上形成複數個第_凸塊及至少一 第二凸塊,該第二凸塊之材質係與該等第一凸塊相 同,且該第二凸塊之高度係小於該等第一凸塊之高 度; π ()將δ玄寺凸塊之頂端浸入一助鮮劑中,使該等第一凸 塊沾附該助銲劑,而該第二凸塊未沾附該助銲劑; (e) 將該等第一凸塊接觸對應之内引腳;及 (f) 進行迴銲,使該等第一凸塊熔接於該等内引腳,而 戎第二凸塊未熔接於該内引腳以保持該晶片之主動 面與該内引腳間之間距。 1 2·如請求項11之方法,更包括·· (g) 形成一封膠材料,以包覆該等内引腳、該晶片、該 等第一凸塊及該第二凸塊。 1 3 ·如%求項丨1之方法,其中該步驟(e)中,該第二凸塊係與 104364.doc 1292614 . 該等第一凸塊之一接觸同一内引腳。 Μ·如請求項I 1之方法,其中該步驟(c)包括·· • (C 1)形成一光阻層於該晶片之主動面; • (C2)形成複數個第一開口及至少一第二開口於該光阻層 上,其中該等第一開口之開口面積大於該第二開口 之開口面積; (c3)填入一金屬至該等第一開口及該第二開口中; φ (c4)移除該光阻層;及 (c5)進行迴銲,使該等第一開口内之金屬形成複數個第 一凸塊,且該第二開口内之金屬形成一第二凸塊, 其中·該第二凸塊之高度係小於該等第一凸塊之高 度。 1 5.如請求項1丨之方法,其中該步驟(c)中,該第二凸塊係為 虛凸塊。 1 6 ·如請求項11之方法,其中該步驟⑴中,該等第一凸塊係 φ 共晶接合(eutectic bonding)於該導線架,該第二凸塊係 接觸(contact)該導線架。 ]7 · —種覆晶方法,包括以下步驟: U)提供一載體,該載體具有一第一表面及一第二表 面; (b) 提供一晶片,該晶片具有一主動面; (c) 於該晶片之主動面上形成複數個第一凸塊及至少— 第二凸塊,該第二凸塊之材質係與該等第一凸塊相 同,且該第二凸塊之高度係小於該等第一凸瑰之高 I04364.doc 1292614 度; (d) 將該等凸塊之頂端零 貼^曰卞丨山 而/又入一助銲劑中,使該等第一凸 塊沾附該助銲劑,而兮笼-几地土匕 μ第一凸塊未沾附該助銲劑; (e) 將該等凸塊接觸該載體之第一表面;及 ⑴=㈣銲,使該等第-凸塊隸而接合於該载體之 第表.面,而该第二凸塊未炫接於該載體之第 乂保持A a曰片之主動面與該載體之第一表面: 間距。 18·如請求項17之方法,更包括: (g)形成一封膠材料,以包覆 ^曰g 0復巧戟體、該晶片、該等 —凸塊及該第二凸塊。 19. 如請求和之方法,其中該步驟⑷包括: (Cl)形成一光阻層於該晶片之主動面; (C2)形成複數個第一開口及至少一 夕 弟一開口於遠光阻芦 上,其中該等第-開口之開口面積大於該第二開: 之開口面積; ㈨)填入一金屬至該等第一開口及該第二開口中; (c4)移除該光阻層;及 ㈣:行迴銲’使該等第-開口内之金屬形成複數個第 凸塊,且該第二開口内之金屬形成一第二凸塊, 其中該第二凸塊之高度係小於該等第一凸塊之高 度。 20. 如請求項]7之方豆 安”干4步驟(a)中,該載體係為一基 板0 104364.doc 1292614 2 1 ·如請求項1 7之方法,其中該步驟(a)中 線架。 . 22.如請求項17之方法,其中該步驟(c)中 虛凸塊。 23.如請求項17之方法,其中該步驟(f)中, 共晶接合(eutectic bonding)於該載體, 觸(contact)該載體。 ’該載體係為一導 ’該第二凸塊係為 該等第一凸塊係 該第二凸塊係接 104364.doc
TW095102294A 2006-01-20 2006-01-20 Flip chip on leadframe package and method of making the same TWI292614B (en)

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