1263350 九、發明說明： 【發明所屬之技術領域】1263350 IX. Description of invention: [Technical field to which the invention belongs]
本發明係有關於一 立體封裝方法，特別係凑 封裝方法。 【先前技術】 在習知半導體立體封裝（3D package)領域中，複數個 帛導體封裝㈣係縱向堆疊並電性連#，以達到丨能整合 之系統封裝（System In Package)或是記憶體容量之擴大。 其中在較底部之半導體封裝構造，係包含有一基板及一半 導體晶片，該半導體晶片係設置於該基板之一上表面並以 -封膠體密封。該基板之該上表面係形成有複數個球墊 (ball pad)，以接合複數個間隔球（interp〇ser baU)，該些間 隔球係用以電性連接縱向堆疊之另一之半導體封裝構 造。但由於在形成封膠體製程時，該些球墊會有被封膠溢 φ 料（m〇lclflash)污染之問題，因此該些球墊必須遠離形成該 封膠體之封膠區，以避免該些球墊被封膠溢料污染，但因 此造成該基板可排列該些球墊之面積減少，或者是需將該 基板之尺寸加大以排列該些球墊。 在一種習知半導體立體封裝方法，首先，請參閱第1A 圖，提供一基板10,該基板1〇係包含一上表面U及一下 表面12，該上表面11係定義有一封膠區丨3，複數個球墊 1 4及複數個内接墊1 6係形成於該基板1 〇之該上表面n， 該些内接墊1 6係位在該封膠區1 3内，複數個球墊丨5係 1263350 形成於該基板10之該下表面12。接著，請參閱第1B圖 將-晶片20設置於該封膠區13内，並以複數個銲線I 電性連接該晶片20與該些内接墊16。接著，請參閱第π 圖，在壓模封膠製程後’一封膠體3〇係形成於該封膠區 13，以密封該晶片20與該些銲線21。然而在壓模過程中， 該封膠體30會有溢流出該封膠區13之封膠溢料一 flash)31，且該封膠溢料31其係會溢流並沾附至部分之球 墊14，尤其是靠近該封膠區13之該些球墊μ。接著請 參閱第U3圖，在回銲辉料或間隔球之後，複數個間隔: 41係接合於該上表面u之該些球& 14，複數個辉球ο 係接合於該下表面12之該些球墊15，以構成一立體封裝 之較底部半導體封裝構造。但由於部分球t 14係沾附有 該封膠溢料3卜因此造成部分球墊14與間隔球4ι之接合 力較弱。最後，請參閱帛1E圖’將上述之半導體封裝： 造與另一半導體封裝構& 50縱向堆疊，並以該些間隔球 41電性連接該半導體封裝構造與該半導體封裝才籌造5〇， 由於該封膠溢料31阻絕該些球塾14肖該些間隔球41而 減弱部分間隔球4丨與該些球墊14之接合力，因而導致部 分間隔球41產生斷裂41a ’而造成間隔球41發生掉球。 【發明内容】 本發明之主要目的係在於提供一種保護球墊之半導 體立體封裝方法，-基板之一上表面係定義有一封膠區並 形成有複數個球墊，在形成一封膠體之前，係形成一可犧 牲遮罩（sacrificabie protection layer)於該些球墊上，以避 1263350 免該封膠體之-封膠溢料沾附於該些球墊。且在移除該可 犧牲遮罩之後，係顯露出該些球墊，以利複數㈣隔球穩 固地接合於該些球塾’以避免在立體封裝過程中該些間隔 球發生掉球。 本發明之次一目的係在於提供一種保護球墊之半導 體立體封裝方法，在一基板之複數個球墊上形成有一鎳金 層，在該鎳金層上並覆蓋有一可犧牲遮罩，且該可犧牲遮 罩係具有揮發性，以利在封膠製程後以加熱方式、水或酒 精清洗方式移除該可犧牲遮罩，以完整顯露該些球墊。 本卷月之再目的係在於提供一種保護球塾之半導 體立體封裝方法’一基板在包含有一封膠區之一上表面係 形成有複數個球墊，該些球墊係為非銲罩界定（N〇n_s〇ld^ Mask Defined，NSMD)之連接墊，以供一可犧牲遮罩覆蓋 至該些球墊之側邊，以增進間隔球之結合。 依據本發明之一種保護球墊之半導體立體封裝方 法，其係包含：提供一基板，該基板係具有一上表面，該 上表面係定義有一封膠區，在該封膠區之外側係形成有複 數個球墊；將一可犧牲遮罩形成於該些球墊上；將一晶片 係設置於該基板；一封膠體係形成於該基板之該上表面， 以覆蓋泫封膠區；在該封膠體形成之後，移除該可犧牲遮 罩，以顯露出該些球墊，以利複數個間隔球之設置，再進 行另一半導體封裝構造之縱向堆疊。 【實施方式】 在一具體實施例中，本發明之保護球墊之半導體立體 1263350 封裝方法係配合第2A至2G圖說明如後。首先，請參閱第 2A圖，提供一基板11〇,該基板11〇係具有一上表面I。 以及一下表面U2,且該上表面ln係定義有一封膠區 113。在本實施例中，該基板丨1〇係為雙面具有球墊之多 層電路板，複數個第一球墊丨丨4與複數個内接墊11 5係形 成於該上表面m，其中該些第一球墊114係位在該封膠 區Π3之外側；複數個第二球墊116係形成於該下表面 112。The present invention relates to a three-dimensional packaging method, particularly a packaging method. [Prior Art] In the field of conventional semiconductor 3D package, a plurality of germanium conductor packages (four) are vertically stacked and electrically connected to achieve a system in package or a memory capacity. Expanded. The semiconductor package structure at the bottom portion comprises a substrate and a half conductor wafer disposed on an upper surface of the substrate and sealed by a sealant. The upper surface of the substrate is formed with a plurality of ball pads for bonding a plurality of spacer balls (interp〇ser baU) for electrically connecting another semiconductor package structure of the vertical stack . However, since the ball pads may be contaminated by the sealant during the formation of the sealant process, the ball pads must be away from the sealant region forming the sealant to avoid the The ball pad is contaminated by the sealant, but the area of the ball pad that the substrate can be arranged is reduced, or the size of the substrate needs to be increased to arrange the ball pads. In a conventional semiconductor three-dimensional packaging method, first, referring to FIG. 1A, a substrate 10 is provided. The substrate 1 includes an upper surface U and a lower surface 12, and the upper surface 11 defines a glue region 丨3. A plurality of ball pads 14 and a plurality of inner pads 16 are formed on the upper surface n of the substrate 1 , and the inner pads 16 are located in the sealing region 13 , and a plurality of ball pads 丨A 5 series 1263350 is formed on the lower surface 12 of the substrate 10. Next, referring to FIG. 1B, the wafer 20 is disposed in the encapsulation region 13, and the wafer 20 and the inner pads 16 are electrically connected by a plurality of bonding wires I. Next, referring to the πth figure, after the die-casting process, a gel 3 is formed in the sealing zone 13 to seal the wafer 20 and the bonding wires 21. However, during the molding process, the sealant 30 has a flashover 31 that overflows the sealant zone 13, and the sealant 31 overflows and adheres to a portion of the ball pad. 14. In particular, the ball pads μ close to the sealant zone 13. Next, referring to FIG. U3, after reflowing the phosphor or the spacer ball, a plurality of intervals: 41 are attached to the upper surface u of the balls & 14, a plurality of glow balls are attached to the lower surface 12 The ball pads 15 are configured to form a bottom semiconductor package structure of a three-dimensional package. However, since the partial ball t 14 is adhered to the sealant 3, the joint force between the partial ball pad 14 and the spacer ball 4 is weak. Finally, please refer to FIG. 1E' to package the semiconductor package described above: another semiconductor package structure & 50 longitudinal stack, and electrically connect the semiconductor package structure and the semiconductor package with the spacer balls 41 to prepare 5 图Because the sealant 31 blocks the ball 塾 14 and blocks the ball 41 and weakens the engaging force of the partial ball 4 丨 with the ball pads 14 , thereby causing the partial ball 41 to break 41a ′ and causing the gap The ball 41 has dropped the ball. SUMMARY OF THE INVENTION The main object of the present invention is to provide a semiconductor three-dimensional packaging method for protecting a ball pad. One of the upper surfaces of the substrate defines a rubber area and a plurality of ball pads are formed. Before forming a gel, the system is formed. A sacrificabie protection layer is formed on the ball pads to prevent the sealant from adhering to the ball pads. And after removing the sacrificial mask, the ball pads are exposed to facilitate the plurality (four) of the ball to firmly engage the ball 塾 to avoid ball drop of the ball during the three-dimensional packaging process. A second object of the present invention is to provide a semiconductor three-dimensional packaging method for protecting a ball pad, wherein a nickel gold layer is formed on a plurality of ball pads of a substrate, and the nickel gold layer is covered with a sacrificial mask, and the The sacrificial mask is volatile to facilitate removal of the sacrificial mask by heating, water or alcohol cleaning after the encapsulation process to fully reveal the ball pads. The purpose of this volume is to provide a semiconductor three-dimensional packaging method for protecting a ball '. A substrate has a plurality of ball pads formed on one surface of a rubber-containing region, and the ball pads are defined by non-welding pads ( The connection pads of N〇n_s〇ld^ Mask Defined (NSMD) are provided for a sacrificial mask to cover the sides of the ball pads to enhance the bonding of the spacer balls. A semiconductor three-dimensional packaging method for protecting a ball pad according to the present invention includes: providing a substrate having an upper surface defining a glue region, the side portion being formed outside the sealant region a plurality of ball pads; a sacrificial mask is formed on the ball pads; a wafer system is disposed on the substrate; an adhesive system is formed on the upper surface of the substrate to cover the sealant region; After the colloid is formed, the sacrificial mask is removed to reveal the ball pads to facilitate placement of the plurality of spacer balls, and then longitudinal stacking of another semiconductor package structure. [Embodiment] In a specific embodiment, the semiconductor stereo 1263350 packaging method of the protective ball pad of the present invention is described in conjunction with FIGS. 2A to 2G. First, referring to Fig. 2A, a substrate 11 is provided, which has an upper surface I. And a surface U2, and the upper surface ln defines a glue area 113. In this embodiment, the substrate 丨 1 is a multi-layer circuit board having a ball pad on both sides, and a plurality of first ball pads 4 and a plurality of inner pads 11 5 are formed on the upper surface m, wherein the substrate The first ball pads 114 are positioned on the outer side of the seal zone 3; a plurality of second ball pads 116 are formed on the lower surface 112.
接著，請參閱第2B圖，可運用例如網板印刷（screen p inting)戳印（stamping)或點膠（以叩⑶以％)等方式形成一 可犧牲遮罩12〇於該些第一球墊114，該可犧牲遮罩12〇 係不遮蓋該些内接墊115。該可犧牲遮罩12〇係為一種可 輕易運用熱量或溶劑加以移除之有機材料，例如有機保銲 劑（Organic S〇iderability Preservative，〇sp)，以在形成封 膠體時保護該些第一球墊丨14。請參閱第3圖，該些第一 球墊114上係依序形成有一鎳層117以及一金層ία，而 該可犧牲遮罩120係覆蓋該金層118。較佳地，該些第一 球墊114係可為非銲罩界定（N〇n-S〇lder Mask NSMD)之連接墊，該些第一球墊114之一側邊ιΐ4Α係対 露於該基才反110之一銲罩| 119，在本實施例中，該側邊 114A亦被該可犧牲遮罩12〇所覆蓋保護。 之後，請參閱第2C圖，將一晶片13〇設置於該基板 110之該上表面111，並以複數個銲線131電性連接該晶 片1 30與該些内接塾！ ！ 5。此外，在不同實施例中，該晶 1263350 片1 3 0亦以覆晶接合方式設置於該基板丨丨〇之該上表面 111 〇 接著，請參閱第2D圖，以壓模封膠技術，形成一封 膠體1 40於該基板11 〇之該上表面η丨，以覆蓋該封膠區 Π 3 ’並且該封膠體丨4〇係密封該晶片丨3 0與該些銲線 131°由於在強大的注膠壓力下，該封膠體14〇可能會溢 流擴散至該封膠區113之外，而形成一溢料（m〇ld flash)141。然而在該可犧牲遮罩12〇之保護下，該溢料ι41 •係不會直接沾附於該些第一球墊丨丨4。 請參閱第2E圖，在該封膠體14〇形成及固化之後， 移除5亥可犧牲遮罩12 〇，以顯露出該些第一球墊丨14，以 利没置間隔球。在本實施例中，該可犧牲遮罩12〇係具有 揮發性，其係可以加熱方式、水或酒精清洗方式完全移 除。之後，清參閱第2F圖，設置複數個間隔球丨5丨於該 些第一球墊114,由於該些第一球墊114上方之該溢料141 • 在移除該可犧牲遮罩12〇時已被移除，因此該些間隔球151 係能穩固地接合至該些第一球墊114，其中該些間隔球151 之材質係可為錫鉛 '或是無鉛銲料。通常該間隔球151之 球高應約大於該封膠體140之厚度。另，複數個銲球152 係接合至該些第二球墊丨丨6，以構成一立體封裝中之其中 可堆豐半導體封裝構造。最後，請參閱第2G圖，可將 另一半導體封裝構造160縱向堆疊於該基板110之該上表 面111上，並回銲該些間隔球151，^接該半導體封裝 構造160。此外，在不同實施例之變化中，該些間隔球⑸ 10 1263350 係可先接合該該半導體封裝構 少兮t卜货+ ^ 冓乂〗60，再連接該基板110 之該些第一球墊1 1 4。 因此’依據上述之半導命 〇 ^ 體立體封裝方法，能藉由該可 犧牲遮罩120在製程中暫時 r保護该些弟一球墊114，以 解決習知半導體立體封裝製 丁衣衣k中間隔球掉球之問題。 本發明之保護範圍當視後 寸之申蚺專利範圍所界定 者為準，任何熟知此項技蓺去 技*者，在不脫離本發明之精神和 孝巳圍内所作之任何變化盥佟 ，、修改，均屬於本發明之保護範 固0 【圖式簡單說明】 苐1八至1E圖:一基板在傳統半導體封裝過程中之截面示 意圖。 第2A至2G圖：依據本發明 ^ 基板在弟一具體實施例之 々 半導體立體封裝過程中之截面示意圖。 第3 W .依據本發明，該基板之局部截面示意圖。 【主要元件符號說明】 10 13 16 20 30 41 50 110 基板 封 内 膠區 11 14 上表面 球墊 12 15 a曰 接墊 片 膠體 下表面 球塾 封 間 半導體封 隔球 基板 21 31 裝構造 ill 上表面 銲線 封膠 斷裂處 溢料 42 銲球 112 下表面 11 1263350 1 13 封膠區 114 第一球墊 Π4Α側邊 115 内接墊 116 第二球墊 117 鎳層 118 金層 119 銲罩層 120 可犧牲遮罩 130 晶片 131 銲線 140 封膠體 141 溢料 151 間隔球 152 鲜球 160 半導體封裝構造 12Next, referring to FIG. 2B, a sacrificial mask 12 can be formed on the first ball by, for example, screen p inting stamping or dispensing (in 叩 (3) in %). The pad 114, the sacrificial mask 12 does not cover the inner pads 115. The sacrificial mask 12 is an organic material that can be easily removed by heat or solvent, such as an Organic S〇iderability Preservative (〇sp), to protect the first ball when forming the sealant. Pad 14. Referring to FIG. 3, the first ball pads 114 are sequentially formed with a nickel layer 117 and a gold layer ία, and the sacrificial mask 120 covers the gold layer 118. Preferably, the first ball pads 114 can be non-welded cover NSMD connection pads, and one of the first ball pads 114 is 侧4Α In one embodiment, the side 114A is also covered by the sacrificial mask 12A. Then, referring to FIG. 2C, a wafer 13 is disposed on the upper surface 111 of the substrate 110, and the wafer 130 and the interconnects are electrically connected by a plurality of bonding wires 131! ! 5. In addition, in different embodiments, the crystal 1263350 sheet 130 is also disposed on the upper surface 111 of the substrate by flip-chip bonding. Next, please refer to FIG. 2D to form a stamper sealing technique. a colloid 1 40 is on the upper surface η of the substrate 11 to cover the encapsulation region Π 3 ' and the encapsulant 〇 4 密封 seals the wafer 丨 30 with the bonding wires 131° due to the strong Under the glue injection pressure, the sealant 14 may overflow and spread out of the sealant zone 113 to form a flash 141. However, under the protection of the sacrificial mask 12, the overflow ι 41 • does not directly adhere to the first ball pads 4 . Referring to FIG. 2E, after the encapsulant 14 is formed and cured, the 5 hasa sacrificial mask 12 移除 is removed to expose the first ball pads 14 to facilitate the placement of the spacers. In this embodiment, the sacrificial mask 12 has a volatility which can be completely removed by heating, water or alcohol cleaning. Thereafter, referring to FIG. 2F, a plurality of spacer balls 设置 5 are disposed on the first ball pads 114, because the flash 141 above the first ball pads 114 • the sacrificial mask 12 is removed. The spacer balls 151 are firmly bonded to the first ball pads 114, wherein the spacer balls 151 are made of tin-lead or lead-free solder. Generally, the ball height of the spacer ball 151 should be greater than the thickness of the sealant 140. In addition, a plurality of solder balls 152 are bonded to the second ball pads 6 to form a stackable semiconductor package structure in a three-dimensional package. Finally, referring to FIG. 2G, another semiconductor package structure 160 may be stacked longitudinally on the upper surface 111 of the substrate 110, and the spacer balls 151 may be soldered back to the semiconductor package structure 160. In addition, in the variation of the different embodiments, the spacer balls (5) 10 1263350 may first join the semiconductor package structure to reduce the number of the first package of the substrate 110, and then connect the first ball pads of the substrate 110. 1 1 4. Therefore, according to the semi-conductor three-dimensional packaging method described above, the sacrificial mask 120 can be used to temporarily protect the brother-ball pads 114 in the process to solve the conventional semiconductor three-dimensional package. The problem of dropping the ball in the middle of the ball. The scope of protection of the present invention is subject to the definition of the scope of the patent application, and any change in the spirit and filial piety of the present invention is subject to any change in the scope of the invention. Modifications belong to the protection of the present invention. [Simplified description of the drawings] 苐18 to 1E: a schematic cross-sectional view of a substrate in a conventional semiconductor packaging process. 2A to 2G are schematic cross-sectional views showing a substrate in a semiconductor three-dimensional packaging process according to the present invention. Section 3 W. A partial cross-sectional view of the substrate in accordance with the present invention. [Main component symbol description] 10 13 16 20 30 41 50 110 Substrate seal inner rubber area 11 14 Upper surface ball pad 12 15 a 曰 pad gasket lower surface ball 塾 sealing semiconductor sealing ball substrate 21 31 mounting structure ill Surface wire sealant breakage flash 42 Solder ball 112 Lower surface 11 1263350 1 13 Sealing zone 114 First ball pad 4Α Side 115 Inner pad 116 Second ball pad 117 Nickel layer 118 Gold layer 119 Welding cap layer 120 Sacrificial mask 130 wafer 131 bonding wire 140 encapsulant 141 flash 151 spacer ball 152 fresh ball 160 semiconductor package structure 12