TWI286238B - Driving method for liquid crystal display, liquid crystal display, and portable electronic machine - Google Patents

Abstract

The subject of the present invention is to employ the common reversed driving on a large, and high definition LCD. The solution is to configure most of the scanning lines at floating state during common reversed driving, so as to greatly reduce the common capacitance. Moreover, the time sequence for scanning lines being at floating state can be changed according to the polarity of common potential. Specifically, if the pixel switch device is N-type channel, it is configured as floating state when the common potential is high; and, for P-type channel, it is configured as floating state when the common potential is low.

Description

1286238 (1) Description of the Invention [Technical Field] The present invention relates to a driving method of a liquid crystal display device, a liquid crystal display device, and a portable electronic device, and more particularly to a common inversion driving of a liquid crystal display device using an active matrix substrate. [Prior Art] In recent years, liquid crystal display devices using active components such as thin film transistors have been rapidly popularized from notebook personal computers or monitors. In a liquid crystal display device using a general nematic liquid crystal material, it is necessary to perform an AC drive for polarity inversion for a certain period of time in order to ensure reliability applied to the voltage of the liquid crystal. In general, the black/white display has a voltage difference of 3 to 5 v applied to the liquid crystal. Therefore, when the active matrix substrate holding the liquid crystal and the electrode (common electrode) of the counter substrate are set to a fixed potential by AC driving, a voltage amplitude signal of 6 to 10 V is input to the pixel electrode of the active matrix substrate. However, in general, when 1C wants to output a signal having a voltage amplitude of 5 V or more, it is required to be manufactured in a special process with excellent high withstand voltage characteristics, and the cost becomes high. In order to avoid this point, the common inversion driving method can be considered, that is, the input signal is lowered by driving the potential of the common electrode by AC (refer to Patent Document 1). Hereinafter, in FIG. 12, the common inversion driving is performed for the common inversion driving and the polarity inversion of the liquid crystal application voltage in accordance with each scanning line selection period (1 Η period), and the normally white mode and the pixel switching element are An example of a liquid crystal display device of a channel type thin film transistor.

Vc〇m ( 1 ) is the common electrode potential, and when the auxiliary capacitance (Cs -4- (2) 1286238 ) is formed, the potential of the common electrode of the auxiliary capacitor is also the same. Ve()m ( 1 ) is driven at a certain period in the common inversion drive. . Reverse driving between the heart and ve()mL. Vg 1 to Π ( 2 - 1 to 2 - η) is the potential supplied from the scanning line driving circuit to the scanning line of n, and the selection of one scanning line is sequentially applied every time Ve()m ( 1 ) is inverted. At the potential (VG0N), the pixel switching element is set to the on state (on state), and at other times, one of VG0FFH or VG0FFL is selected as the non-selection potential according to the potential of Ve()m (1) to be connected. The pixel switching element is set to the OFF state (non-conducting state). Here, the reason why the non-selected potential is set to Vgoffh and VG0FFL according to the potential of ve()m (1) is to ensure the reliability of the pixel switching element, which is disclosed, for example, in Patent Document 2. V s ! (3 - 1) ~ V s n ( 3 - m ) is the image signal potential supplied from the data line driving circuit to the data line, and has an amplitude between VVIDE0H and VviDEOL. When liquid crystal molecules used for liquid crystal materials or gaps are selected, they are white (transmissive) when held by electrodes with potential difference, and black (non-transmission) when held by electrodes with ±乂81^(:1<:potential difference) When displayed, set to VC 〇MH= VvidE0H> VviDEOL= Vc〇ML j Vc〇MH— VviDEOH = VviDEOL— Vc〇ML = VwHITE, VC Ο Μ H — VVIDE 0 L = VVIDE Ο H — VC Ο ML II V b The potential of LACK 0 VS1 (3 - 1) to Vsn ( 3 - m) is applied to the pixel electrode via the pixel switching element connected to the scanning line of the selection potential (VG0N), assuming Vmd.m~乂^^^ When the potential of the pixel electrode connected to the m-th data line and the n-th scan line is Vpixm Vpm + 2 is the potential (Vsl, VS2) charged to the data lines 1 and 2 when the scan line 1 becomes the selection potential (VG0N). It becomes the potential of VviDEOH and VviDEOL respectively. At this time, the common -5- (3) 1286238 potential is VC0MH, and the liquid crystal on the corresponding pixel electrode is applied with the potential of VviDEOH - VCOMH II-VWHITE, and the pixel corresponding to VpiX4 - Bu 2 The liquid crystal on the electrode is applied with VviDEOL — Vc〇MH = — VblaCK That is, the pixel corresponding to Vpm-w becomes a transparent (white) display, and the corresponding pixel becomes a non-transmissive (black) display. Then, when scan line 2 is selected, the common potential is inverted to VC0ML, ViMxm Vpm The pixel electrode corresponding to -u becomes a floating state because the connected pixel is high resistance. Assuming that the capacitance other than the capacitance of the common electrode and the capacitance line is small enough to be negligible, Vmxhu, Vmx^ can be made by capacitive coupling. The inversion of -2 simultaneously reduces the variation of the common electrode potential (VCOML - VCOMH), the pixel corresponding to VHX4-M is kept through (white) display, and the corresponding pixel remains non-transmissive (black) display. As explained above, Even if the common potential is repeatedly inverted, the potential difference between the pixel electrodes connected to the scan line of the non-selected potential is unchanged, and the same gray scale display can be maintained between the next scan line becoming the selection potential. In addition, the fj Vpmn VPIX4.2_2 is charged to the potentials of the data lines 1 and 2 (Vsl, Vs2) when the scanning line 2 becomes the selection potential (VG0N), and becomes the potential of VviDEOL and VVIDE0H respectively. At this time, VpiX4-2-l corresponds to The liquid crystal on the element electrode is applied with a potential of V VIDEOL — Vc〇ML two VWHITE, and the liquid crystal on the pixel electrode corresponding to VPIX 4-2-2 is applied with a potential of VviDEOH — Vc 〇 ML ^ VbLACK, respectively, to become a transparent (white) display. Non-transmission (black) display. However, the polarity of the voltage applied to the liquid crystal and the pixel corresponding to VtMxm Vhxu-2 are reversed. As in the previous description, even if the common potential is reversed after the scanning line 2 becomes the non-selected potential -6 - (4) (4) 1286238, the potential difference between the common potential and the pixel potential does not change, and the display can be maintained. After the update write time corresponding to the update rate, when the next frame scan line becomes the selection potential again, the common potential is VC0ML when the scan line 1 becomes the selection potential (V〇〇N), and the scan line 2 becomes the selection potential ( When V〇〇N), the common potential is VC〇MH, and the polarity of the potential applied by the liquid crystal molecules is reversed from the previous frame, so that AC driving can be realized. The above is a conventional 1 Η common inversion driving method. According to this method, the amplitude of the input image signal from the external 1C is 3 to 5 V, and the cost can be reduced by using a cheap 1C manufactured by a general CMOS process. This is because the driving circuit of the active matrix substrate is all added, or when the driving circuit is built in the built-in LCD of the driving circuit of the active matrix substrate, the image signal needs to be output 1C when driving analog signals of the input image analog signal. When the digital driving is built in the DAC or the decoder, the power supply 1C is required to supply DC power to the DAC or the decoder, and when the power generation circuit is built in the power supply/drive circuit built-in type LCD of the active matrix substrate, The larger the power supply voltage range is, the larger the circuit area and the consumption current are, and the adverse effect on the reliability of the thin film transistor is caused. Therefore, the common inversion driving is an effective method. [Patent Document 1] JP-A-62-49399 (Patent Document 2) Japanese Laid-Open Patent Publication No. JP-A No. Hei. High-definition (5) 1286238 degree panel problem. That is, with the development of large-scale and high-definition, the capacitance (C) of the common electrode becomes large, and the resistance (R) of the common electrode also becomes large. When the common potential is reversed, the capacitance delay (RC delay) becomes large. It takes a lot of time to cause the inversion of the common potential, and the current flowing in during the common inversion is increased, and the consumption current is also increased. (Means for Solving the Problems) The present invention solves the above problems. When inverting the common potential (common inversion timing), at least a part of the scanning lines are electrically cut off by the potential power sources by high resistance. That is, it is set to a so-called floating state to reduce the common capacitance. According to the calculation by the inventors, when the data line is set to the floating state in the common inversion timing, more than 80% of the capacitance of the common electrode in the conventional common inversion driving method is the capacitance between the scanning lines. Therefore, it is preferable to set a plurality of scanning lines as floating as possible, and it is preferable to set all of the scanning lines to a floating state. In this case, the inversion time of the common potential can be reduced to 20% as compared with the conventional example. However, as will be described later, even if only one specific scanning line is not in a floating state in order to match the driving, for example, when the total number of scanning lines is 480, as long as the remaining 479 scanning lines become floating, then all scanning is performed. When the line is in a floating state, the difference in capacitance is only 1% or less and there is no problem. As described above, by setting the scanning line to the floating state, even if the size of the scanning line increases and the number of scanning lines increases, the 1 Η common inversion driving method or other common inversion can be performed, which has the advantage of reducing the power consumption. Further, in the present invention, the timing of the scanning line is set to the floating state, and when the pixel transistor is of the channel type, the timing at which the common potential is high is selected. Therefore, it is not necessary to -8-(6) (6) 1286238, as in the conventional example, the non-selection potential of the scanning line is switched by the common potential'. In addition, the non-selection potential can be lowered during the selection period without reliability. The scanning line potential does not exceed the lowest potential of the image signal of the source, and the pixel TFT can be surely set to the OFF state, and the type of potential supplied to the scanning line driving circuit can be reduced, and the cost can be reduced without degrading the display quality of the panel. Can improve reliability. When the pixel transistor is of the P channel type, the same effect can be obtained by selecting the timing at which the common potential is low, that is, the potential of the next common potential is inverted, and the scanning line is set to a floating state, and the pixel switching element is used for complementary transmission. At the gate, the scan line connected to the N-channel transistor of the transfer gate is set to a floating state when the common potential is high, and the scan line connected to the P-channel transistor is set to a floating state when the common potential is low, and the same can be obtained. effect. Further, in the present invention, after the pixel writing is completed, the length of time from when the non-selected potential is applied to the scanning line until the scanning line is in a floating state is not constant, but a plurality of driving methods are employed. According to this, when the scanning line selection period is fixed, the timing of the scanning line being set to the floating state can be selected by the level of the common potential, so that the display quality is not lowered. Further, in the driving method of the present invention, after the write potential is applied to the scanning line to terminate the connection of the pixels, the non-selection potential is applied to the scanning line to turn off the pixel switching element, and then the scanning line is set at an appropriate timing. A non-selection potential is applied once or more between the floating state and the time when the selection potential is applied to the next scanning line. According to this, it is possible to prevent the leakage current from flowing during the pixel holding period from causing the scanning line potential to rise, and the connected pixel switching element to be turned on at the timing other than the expected timing. In addition, the present invention also proposes that during the non-selective potential application period of the ninth to the ninth (7) 1286238, when the pixel switching element is an N-channel type transistor, it is limited to a period in which the common potential is high, and When the switching element is a P-channel type transistor, it is limited to a period in which the common potential is low. According to this, it is not necessary to apply the potential according to the change in the non-selection period, the number of power supply potentials of the scanning line driving circuit connection can be reduced, the reliability can be improved, and the cost can be reduced. Further, in the driving method of the present invention, the period in which the common potential is high and the period in which the common potential is lower is different in the common inversion, and the period in which the common potential is high when the pixel switching element is the N-channel type thin film transistor is common. The period during which the potential is low is set to be long, and when the pixel switching element is a P-channel type thin film transistor, the period in which the common potential is low is longer than the period in which the common potential is high. According to this, when the scanning line selection/non-selection period is fixed or the variation is not within a large range, the timing of the scanning line can be selected as the floating state by the level of the common potential, and the configuration can be easily realized without degrading the display quality. Drive circuit. Further, in the driving method of the present invention, the non-selection potential of the scanning line is not affected by the co-energization fl/·, and is often a constant (V g 〇 f f ). According to this, 'the number of power sources connected to the scanning line driving circuit can be reduced, the structure of the driving circuit can be simplified' and the timing of the scanning line is set to the floating state, and the scanning line potential can surely drive the pixel switch to the OFF state. . Further, when the pixel switching element is an N-channel type field effect transistor, the lowest potential of the image signal potential applied by the data line driving circuit is set to VVIDE0L, and the threshold of the pixel switching element is set to Vth, and the potential of the common electrode is high. The potential is set to VC0MH, and the potential of the common electrode is set to Vcoml -10- (8) 1286238, and [J VGOFF is set to satisfy VviDEOL+Vth>VGOFF>VviDEOL — (VcOMH — Vc〇ML). When VviDEOL+Vth>VGOFF', the pixel switching element can remain off even when the image signal is at the lowest potential. Moreover, by setting Vg 〇 FF > VvIDEOL - (VcOMH - Vc 〇 ML), the reverse bias applied to the pixel switching element can be reduced, which contributes to a reduction in reliability or leakage current, which is set by the scanning line. The timing of the floating state is selected. When the common reverse driving is performed, the scanning line potential is not greater than VVIDE0L, and the display quality is not lowered. Moreover, it is better to consider the threshold voltage of the pixel switching element, the leakage current of the secondary threshold region or the reverse bias voltage, and set it as Vvideol2Vgoff>

Vvideoh — 6 volts. Similarly, when the pixel switching element is a P-channel type field effect transistor, it is preferable to satisfy VviDEOH + Vth < Vg 〇 FF < VyiDEOL - (VcOMH - Vc 〇 ML), and more preferably to satisfy VvIDEOhSVg 〇 FfSVvIDEOL + 6 volts. Further, in the driving method of the present invention, the length of the scanning line supplied to the non-selection potential period is always constant, and the non-selection potential is 上述 (= Vgoffh) of the common high state and the common low state (= Vg 〇 FFL). They are different from each other, and Vg〇FFH>Vg〇FFL. In comparison with the above-described driving method in which the non-selected potential is always kept constant, there is a disadvantage that the number of power supply potentials is increased, but the period during which the non-selective potential is supplied can be kept constant, and the driving circuit can be simplified. Further, in the driving method of the present invention, when the common potential is inverted, a part of the data lines, more preferably all of them and the scanning lines are in a floating state. Accordingly, the capacitance of the common electrode can be further reduced, and the effect of the present invention is more remarkable. -11 - (9) 1286238 The liquid crystal display device of the present invention uses the above-described driving method. With the use of the above driving method, even a large-sized, high-definition panel can be used with a low withstand voltage IC, and an inexpensive device can be provided. Moreover, compared with the conventional driving method, the consumption current can be reduced. Further, in the drive circuit built-in type liquid crystal display device of the present invention, at least a part of the scanning line drive circuit is constituted by a thin film transistor formed on the active matrix substrate. According to this, the driving method can be changed, and the scanning line retracting wiring portion from the pixel portion to the scanning line driving circuit is shortened, and the fluctuation of the scanning line potential due to the fluctuation of the common potential due to the capacitance division of the portion of the capacitor is reduced. The phenomenon can be suppressed to a minimum while there is no need to change the external 1C. As described above, the inventions are more effective as the number of scanning lines increases and the size of the panel increases. Specifically, the present invention is applicable to a panel that satisfies the condition that the square of the number of scanning lines (=V) is multiplied by the size (=s (m)) of the diagonal direction of the image display area (=VxVxS) is greater than or equal to 30000. . Further, the portable electronic device of the present invention is equipped with a liquid crystal display device using the above-described driving method and driven by a battery. By providing a liquid crystal display device using the above-described driving method, it is possible to provide a display device having a larger size and higher definition at a lower cost, and it is possible to reduce the consumption current as compared with the conventional driving method, and the driving time of the battery becomes long. The portable electronic device here can be a notebook personal computer, a PDA, a digital camera, a video camera, a portable television, a mobile phone, a portable photoelectric display, a portable video player, a portable DVD player, and a portable type. Audio playback (10) 1286238 LCD and other liquid crystal display devices and electronic devices equipped with batteries. [Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the drawings. (Embodiment 1) FIG. 1 is a diagram showing a scanning line driving circuit of a first embodiment of a driving method for realizing the first, second, fifth, sixth, seventh, ninth, tenth, first, and sixth aspects of the patent application scope of the present invention. The structure of the Tibetan active matrix substrate. On the active matrix substrate (1 0 1 ), 48 0 scanning lines (201 - 1 to 480) and 1 920 data lines (2 0 2 - 1 to 1 9 2 0 ), 480 capacitors are orthogonally formed. The lines (2 0 3 - 1 to 4 8 0 ) are parallel and interactively arranged with the scan lines (201 - 1 to 480). The data line (2 02 — 1 to 1 92 0 ) is connected to the data line input terminal (3 02 — 1 to 1920 ). The capacitance lines (203 - 1 to 480) are short-circuited to each other and connected to the common potential input terminal (303). The pair of vias (304) are also connected to the common potential input terminal (3 03 ). Forming a pixel switching element (4 0 1 - η - m ) composed of an N-channel type field effect film transistor at each intersection of the scanning line (201 - η ) and the data line (202 - m ), the gate connection thereof On the scan line (2 0 1 - η ), the source/drain are connected to the data line (202 - m ) and the pixel electrode (402 - η - m), respectively. The pixel electrodes (402 - n - m) form a capacitance line (203 - η) and a supplementary capacitor, and when the liquid crystal display device is assembled, the liquid crystal element is sandwiched, and a capacitance is formed between the counter substrate electrodes (COM). The scanning lines (201 - 1 to 480) are connected to the scanning line driving circuit (3 Ο 1 ) formed by the -13-(11) 1286238 integrated polycrystalline silicon oxide transistor on the active matrix substrate to be supplied with a driving signal. The CLK signal terminal (601), the CLKX signal terminal (602), the XST signal terminal (603), the HENB terminal (604), the LENB terminal (605), and the LCHG terminal (606) are connected to the scanning line driving circuit (3 01 ). Also, a plurality of power supply potentials are connected to the scan line driving circuit. 2 is a detailed circuit configuration of the scan line driving circuit (301), the shift register circuit (350) is built in the scan line driving circuit (301), and the CLK signal terminal (601) is connected. CLKX signal terminal (602), XST signal terminal (603). The shift register is formed by a first clocked inverter (351-n), a second clocked inverter (352-n), and a first inverter (3 5 3 - η), all of which are formed by The 480-segment consists of 481 output terminals (504-1~481). The nth (=1~480) output terminal (504-n) and the n+1th output terminal (504-n+1) of the shift register circuit (350) are respectively connected to the IN AND circuit (505) — the input terminal of η), the output terminal of the IN AND circuit (505-η) is connected to one of the input terminals of the second inverter (506-n) and one of the input terminals of the fourth AND circuit (509-n), The output terminal of the second inverter (506 - η) is connected to one end of the input terminal of the second Ν AND circuit (507 - η) and one end of the input terminal of the 3N AND circuit (5 08 - η). Further, the other end of the input terminal of the second NAND circuit (5 07 - η ) is connected to the HENB terminal (604), and the other end of the input terminal of the third NAND circuit (5 0 8 - η ) is connected to the LENB terminal (6〇5), The other end of the input terminal of the 4NAND circuit (509-η) is connected to -14- (12) 1286238 to the LCHG terminal (606). The output terminals of the 3N AND circuit (508-n) and the output terminals of the 4th NAND circuit (509-n) are respectively connected to the input terminals of the 5th AND circuit (510-n). The output terminal of the second Ν AND circuit ( 5 07 - η) is connected to the gate terminal of the second transistor (512 - η ) of the P channel type thin film transistor, and the output terminal of the fifth Ν AND circuit (510 - η ) is connected to Ν The gate terminal of the first transistor (511-η) of the channel type thin film transistor. The source terminal of the first transistor (51 1 - η ) is connected to a power source having a potential of VG0FF, and the source terminal of the second transistor (5 1 2 - η ) is connected to a power source having a potential of VG0N. The 汲 terminal of the first transistor (5 1 1 - η ) and the 汲 terminal of the second transistor (5 1 2 - η ) are connected to the scanning line (20 1 - η ). a first clocked inverter (3 5 1 - η ), a second clocked inverter ( 3 52 - η ), a first inverter (353 - η), a first NAND circuit (50 5 - η), The second inverter (506 - η), the second Ν AND circuit (507 - η ), the third NAND circuit (508 - η), the fourth NAND circuit (509 - η), and the fifth Ν AND circuit (510 - η) are used as a power source It is connected to the VH potential terminal and the VL potential terminal. The specific driving method of Embodiment 1 will be described below with reference to Figs. 3, 4, and 5. 3, 4, and 5 are diagrams of odd frames, and the frames of the even frame start from the common low state ‘the same as the common low state. Therefore, the potential of the common electrode when the respective scanning lines are supplied with the selected potential is reversed. Fig. 3 is a timing chart showing signals supplied from an external signal system of odd frames of the first embodiment. VeQm (1) is a potential that is supplied to the common potential input terminal (3 03 ) and is reversely driven between 乂(3)(4) and VC0ML in a predetermined period. (13) 1286238

The hold period TCOMH of Vc〇MH (referred to as the common office state in this period) is equal to the hold period TC0ML of VCOML (referred to as the common low state in this period), and the 481-fold period of Tcomh is one frame period Tframe. Vclk (4) is a shift of the positive-phase clock signal for the shift register drive supplied to the CLK signal terminal (60 1 ), and is shifted only by the period of the inversion period of VeVm(1). The phase of TSH i FT is input to the signal driven inversion between VH and VL, and VCLKX ( 5 ) is the inverse phase clock signal potential for the shift register drive supplied to the CLKX signal terminal (602). VCLK reverse polarity signal. Vxst (6) is a pulse wave of the pulse length Tc 〇 MH and the period Tframe of the input potential of the shift register of the input XST signal terminal (603). VHENB (7) is a potential for expressing the timing of supplying the selection potential to the selected scanning line input to the shift register of the HENB terminal (604), and becomes VH when Vclk(4) is inverted. Period (Thenb<

After Tcomh) becomes VL. VLENB (8) is a potential for expressing the timing of supplying a non-selected potential to the selected scan line input to the shift register of the LENB terminal (605). When VHENB(7) changes to VL, it becomes VH almost simultaneously. During the high state, Vc^m ( 1 ) returns to VL before reversing, but after Vcom ( 1 ) is inverted in the common low state, the signal reverts to VL almost simultaneously with the reversal of VCLK. VLchg (9) is a timing for supplying a non-selected potential to a non-selected potential other than the selected scan line input to the shift register of the CHG terminal (605), that is, a potential for recharging the VG0FF recharge timing of the scan line, in a common high state. Zhongcheng-16- (14) 1286238 is a certain period (TLCHGC TC0MH), and other periods become pulse waves of VL. Fig. 4 is a timing chart showing an image signal supplied from an external driving circuit of an odd-numbered frame of the first embodiment, wherein a solid line indicates a state in which a potential is supplied from an external power source, and a broken line indicates a floating state in which each external power source is cut off by a high resistance. The following is based on the premise of the normal white mode. 1~1 920) is the image signal potential of the input data line input terminal (302-1~1 920), which is within the range of the highest potential VviDE〇H~lowest potential V v ϊ DE 〇L, and its detailed waveform is displayed. The images are different. In the embodiment, the waveforms of vsl, vs2, and Vsl92 are respectively set such that the pixel connected to the data line 1 (202-1) is a white (transmissive) display, and the pixel connected to the data line 2 (202-2) is Black (non-transmissive) display, the pixel connected to the data line 1920 (2 02 2) is gray (semi-transmissive) display, and the input pixel is selected after the pixel charging end/pixel switch element is set to the OFF state. The level signal is used as a precharge signal, and thereafter, the common inversion timing is set to a floating state. The output start/stop timing or precharge timing of the video signals of Vsl~192() (3 - 1~1 920) are different according to the order of the dot, the line order, the block order, and the like, but any case Next, the data line should be set to float in the common inversion timing. In the example of the present invention, the description is based on the premise that the line is driven. 5 is a timing chart of an output signal supplied to the scanning lines (201-1 to 480) by the scanning line driving circuit (3 〇j) in the odd frame of the first embodiment, and the solid line indicates the state in which the potential is supplied from the external power source, and the dotted line Indicates the floating state of each external power supply that is cut off with high resistance. Shift register circuit (3 5 〇) -17- (15) 1286238 Output VH only for a specific output terminal (5 04 - η) and its adjacent output terminal ( 5 04 - η + 1 ), at CLK Signal: VCLK (4) and CLKX signal: When VCLKX ( 5 ) is inverted, the output VH boost terminal is shifted by one. According to this, the potential of 乂〇1~„(2−1~2 - 480) is finally applied to the scanning line, that is, the scanning lines 1, 3, 5 · · · ( 2 - 1 , 2 ) such as odd frames —3, 2—5, · . . . . ) The selection potential V is supplied to the common-state state (the scan line of 3 ο N will become a floating state in the state of the common office), such as the scan lines 2 and 4 of the odd-numbered frame. 6··· (2—2, 2—4, 2-6, · · ·) The scan line to which the selection potential VG0N is supplied in the common low state is inverted by V e.m ( 1 ) through TS η IF After τ to V c LK ( 4 ), the inversion does not become a floating state. That is, the timing of the floating state is switched by the change of the write time of the non-selected potential. The non-selection potential is written during the TLCHG period during the period in which the common potential is high, but is set to the floating state before and after the inversion low state and the inversion timing of the common high state and the common low state. Moreover, the even frame system and the odd frame are the same. When the same scanning line is supplied with the selection potential VG0N, the polarity of the common potential is inverted, and the AC driving of the liquid crystal is performed. The reliability of the liquid crystal can be ensured. In the present embodiment, the power supply potentials are preferably set to VH 2 VG0N > V VIDEOH > V VIDEOL > Vg〇ff 2 VL, and V c Ο Μ Η $ V v ID Ε Ο Η〉

VviDEOL — Vc〇ML. Also, according to Vc〇MH — VviDEOH^VwHITE, the liquid crystal element and the grid gap are used to display the white (transmission) display voltage when the white mode is displayed, and VVideoh — VC0ML = Vblack is the same, and it is set to the normally white mode display. Black (non-transmission) shows the voltage. -18-(16) 1286238 As in the present embodiment, when the pixel switching element is a polycrystalline germanium film transistor, the threshold voltage error becomes large, and the secondary threshold region or the reverse bias leakage current cannot be ignored. When the screen reproduction rate is 60 Hz or less, if the leakage current is larger than lpA, a larger holding capacitance is required, and the aperture ratio is lowered to deteriorate the display quality. Figure 13 is a graph showing the leakage current of a pixel switching element using a polycrystalline germanium film transistor tested by the inventors. The horizontal axis is the gate/source potential (V), and the vertical axis is the source/drain leakage current (A). The test is to record the maximum leakage current. Curve 1 (9 5 ) is the data for the N-channel transistor, and curve 2 (96) is the data for the P-channel transistor. When the N-channel type transistor is used in this embodiment, it can be seen from the curve 1 (95) that the maximum leakage current of the pixel switching element is less than 1 PA, and the potential between the gate and the source falls at 〇--6 (V). Within the scope. In the driving of the present invention, when the gate potential is V〇OFF, the gate/source potential becomes between Vg 〇 FF — VViDE 〇 L 〜 Vg 〇 FF — Vvi DE OH, and therefore, by VvIDEOL^VgOFF^VvideOH — It is better to set the 6 (V) so that the potential between the gate and the source becomes 0 to 1 5 (V). Moreover, when the P-channel type transistor is used as the pixel switching element, it is known from the curve 2 (9 6 ) that the drain/source potential of the leakage current is less than 1 PA falls within the range of 0 to +6 (V). The range of Vvideoh$VgoffSVvideoh + 6 (V) is better. Further, in general, the influence of the liquid crystal element is preferably applied to the potential center of one circuit or element (i.e., the average value of the high potential and the low potential) at the common electrode potential. Consider the potential setting 値 in the present embodiment under the above conditions. For example, suppose you select soil Vwhite=〇*5 (V), Vblack — 4.0 (V), liquid Japanese material -19- (17) 1286238 material and bonding gap, as long as it is set to VH= 8.5 (V), VG0N= 7.5 (V ) , V c 〇μ η — 6.5 ( V ) Vvideoh — 6 ( V )

Vvideol2.5 (V), Vcoml2 (V), Vgoff = 1 (V), VL = 〇 (V). According to the above driving method, the total scanning line (480) is converted from the common low state to the inversion timing of the common low state, and the scanning line other than the scanning line is selected when the common high state is converted to the inversion timing of the common high state. (4 7 9) becomes a floating state, compared with the conventional driving method in which the entire scanning line is continuously written to the non-selected potential, the current flowing into the common potential input terminal (3 03 ) during the common inversion driving becomes extremely small, and the common potential is The change is also extremely fast. In other words, the reverse driving can be used in a large-scale, high-definition manner without deteriorating the display quality, and the 1C outputting the video signal can be used at a low cost and low withstand voltage 1C, and the power consumption is also reduced. Moreover, the timing at which the scanning line is set to the floating state is changed between the common high state and the common low state, so even if the non-selected potential of the scanning line is one, as shown in FIG. 5, VG1 to 48G (2- 1 to 4 8) As shown in 0), the scan line potential in the non-selected state fluctuates with the common potential, but the potential does not rise above VG0FF. In addition, re-writing of the non-selected potential is performed during each TC0MH+TC0ML 'so that even if the leakage current of the first transistor (511 - η) or the second transistor (5 1 2 - η) of Fig. 2 becomes large The scan line does not deviate from the non-selection potential during the hold period. In addition, the VG0FF can maintain a constant potential regardless of the common low state or the common high state. It is not necessary to invert the power supply potential or select one of the two potentials. The circuit configuration is simple, which can effectively reduce the cost and improve the yield. -20- (18) 1286238 In addition, since Vgoff is set to 値, the pixel switch element (401 - n - m) is not set in the non-selection period due to the source potential during the common inversion drive. In the case of the N-shape, the reverse bias applied to the pixel switching element (4 〇 1 - η - m ) can be suppressed to the minimum, and there is no fear of a decrease in reliability and an increase in leakage current of the pixel switching element. Fig. 6 is a perspective view (partially broken view) of a transmissive liquid crystal display device of the first embodiment of the liquid crystal display device of the invention of the invention. The active matrix substrate (101) and the counter substrate (901) which forms an ITO film on the color filter substrate to form a common electrode are bonded together by a package member (920), and the nematic liquid crystal is sealed therein. Material (9 i 〇). Although not shown, the active matrix substrate (1 01 ) and the counter substrate (9 〇i )' are coated with an alignment material composed of polyimine at the same time as the surface of the liquid crystal material (9 1 0 ). The rubbing treatment is applied in the direction of intersection. Further, a conduction member is disposed on the pair of via portions (3 04 ) of the active matrix substrate (1 0 1 ), and is short-circuited to the common electrode of the counter substrate (901). Data line input terminal (302-1~1920), common potential input terminal (303), CLK signal terminal (601), CLKX signal terminal (602), XST signal terminal (603), HENB terminal (604), LENB terminal ( 605), LCHG terminal (606) or various power terminals are connected to 1 to a plurality of external 1C (940) on the circuit substrate (93) via an FPC (930) mounted on the active matrix substrate (101). Supply necessary electrical signals and potentials. A polarizing plate (95 1 ) is disposed on the outer side of the counter substrate, and a lower polarizing plate (952 ) is disposed outside the active matrix plate, so that the polarizing directions are orthogonal to each other (19) 1286238. Further, the backlight (960) is mounted on the lower side of the lower polarizing plate (952). The backlight (960) may be a light guide unit in which a light guide plate or a diffusion plate is attached to the cold cathode tube, or may be an EL element. Although not shown, if necessary, a protective glass or an acrylic substrate may be attached to the periphery or to the upper side of the lower polarizing plate, and the optical compensation film may be adhered to improve the viewing angle. The common potential delay time constant (=r COM ) when the liquid crystal display device performs common inversion driving, and the average resistance (second Rcom ) of the common electrode and the common electrode relative to the fixed potential relative to the total capacitance of the other conductors ( The product of =Cc〇M) is proportional (l comxRcomxCcom). In general, Rcom is determined by the limitation of the sheet resistance of the counter electrode or the resistance of the via/mounting terminal, and is not affected by the panel size or fineness. Further, in the conventional common inversion driving method, as described above, the inter-scanning line capacitance is 80% or more of CC0M, and the medical [this CC0M and the total number of scanning lines (=V (bar)) are increased in a slight proportion. Further, the longer the length of the scanning line is, the larger the capacitance of one scanning line is. Therefore, CCOM also increases slightly in proportion to the diagonal direction size (=S ( m )) of the image display area. In addition, assuming that the regeneration rate is constant, the write time (=T 1 η ) of the scan line is inversely proportional to the total number of scan lines (two V (bars)). That is, in the conventional common inversion driving method, the ratio of the write-on time of the #-inversion time to the write time of one scan line (r + TiH) is roughly Γ cOM + TihxVxVxS 'the coefficient is too large to obtain sufficient The pixel write time may result in reduced display quality or reliability. Figure 14 is a graph of the square of the -22-(20) 1286238 scan line number (=v) multiplied by the diagonal dimension of the image display area (=S(m)) when using the active matrix process of a general glass substrate (=VxVxS) And a graph of the calculation result of the ratio of common inversion time (; com + T 1 η ) with a time. Further, the reproduction rate is set to 60 Hz, and the curve 1 (91) is a graph indicating (r C0M + T1H ), which is roughly proportional to VxVxS. The margin line i ( 92 ) is a margin line that is divided by the minimum time necessary to ensure the vertical pixel writing time. It can be seen that it is difficult to perform the 1H common inversion driving in the conventional driving method of the VxVxSg30000 or more. . Here, with the panel of the present embodiment which is suitable for satisfying the VXVXS 2 3 0 0 0 0 0, even a large-scale, high-definition panel which is impossible to drive in common reverse rotation of the conventional method can be used with a low-cost, low-withstand voltage 1C. Therefore, the module price can be manufactured cheaply, and the power consumption is also reduced. In the present embodiment, when the pixel number is 1920 x 480, the so-called VGA, and the diagonal angle is 152.4 mm (type 6), VxVxS = 35113 can be obtained, which satisfies the above conditions. Further, in the present embodiment, if the leakage current of the second transistor (512-1 to 489) is small, the period in which the VLCHG signal (9) becomes VH can be longer, and the LCHG terminal (606) is omitted and connected thereto. The line and the 4Nth AND circuit (509-n) of FIG. 2 may be replaced with an inverter circuit by replacing the 5Nth AND circuit (5 1 0 - 1 ). Accordingly, the input signal or circuit configuration can be simplified, and a cheaper liquid crystal display device can be manufactured. Further, the common electrode potential is described by taking two turns (VC0MH, VC0ML) as an example. However, it is also possible to set three or more turns in accordance with the driving method by adding a finer amplitude. In this case, any one of the average potential, the maximum potential, and the minimum potential of the common electrode in the common high state is replaced by VC Ο Μ Η, and the average potential, the maximum potential, and the minimum of the common electrode of the common low state (21) 1286238 are minimized. Any one of the potentials can be replaced by VC0M L. Further, the driving method of the gate selection potential or the non-selection potential may be set to be more. Further, instead of the shift register of the clocked inverter shown in Fig. 2, the flip-flop is configured to be a shift register of the flip-flop circuit or the transfer gate. Alternatively, instead of using a shift register, various sequential selection circuits may be used, and the logic circuit portion of Fig. 2 may be changed. Further, in the present embodiment, the scanning line driving circuit (301) is driven by the potential of VH (2 Vgon) and VL (SVgoff), but one of the portions may be driven at a lower potential difference. For example, the power supply of the shift register circuit (350) uses VH M ( < Vgon) and VL Μ ( > Vgoff ), and the signal amplitudes of VCLK (4), VCLKX (5), and VXST (6) are set to the same. From the output terminal (504 - η) to the first transistor (511 - η) • the second transistor (5 1 2 - η) is placed at any position between the shift register circuit, boosted to VH ~ VL The level may be either a shift register circuit (3 50 ) or a circuit configuration in which the first NAND circuit to the fifth singer circuit itself have an additional level shift function. With this configuration, the consumption current can be reduced. (Embodiment 2) Figs. 7, 8, and 9 are among the second embodiment of the driving method for realizing the first, second, sixth, seventh, ninth, tenth, first, third, and sixth aspects of the patent application scope of the present invention. Signal timing diagram for odd frames. In the figure, the solid line indicates the state in which the potential is supplied from the external power source, and the broken line indicates the floating state in which the external power source is cut off with high resistance. -24- (22) 1286238 FIG. 7 is a timing chart of each fe number supplied from an external signal system in the odd frame of the second embodiment, and the holding period tc〇ML of the VC0MH holding period tcomh and VC0ML of the VCQm(1) is TC〇MH> ;Tc〇ML' (Tc〇MH+Tc〇ML) X 240.5 becomes the frame period Tframe. That is, the even frame is started from the middle of the high common potential.

Vclk (4), Vclkx (5), Vxst (6), Vhenb (7), and VLchg (9) are the same waveform as in Embodiment 1, but VLENB (8) is in a period in which the common potential is high and the common potential is low. The length of the VH is the same, and VHENB (7) and VLENB (8) become reverse polarity waveforms. 8 is a timing chart of image signals supplied from an external driving circuit of the odd-numbered frame of the first embodiment, except that the common inversion timing is such that the source line is in a floating state, and the application time of the pixel electrode of the image signal is shortened. Both are the same as those of Fig. 4 of the first embodiment. Fig. 9 is a timing chart showing an output signal supplied from the scanning line driving circuit (301) to the scanning lines (201-1 to 480) in the odd frame in the second embodiment. VG1 ( 2 — 1 ), VG3 ( 2 - 3 ), _ · • The selection potential (VG0N) is applied after TSH ! F τ after the common inversion timing becomes the common high state, and becomes floating during the period in which the common potential is high. The state, VG2 ( 2 - 2 ), VG4 (2 - 4), · · · is the common inversion timing after the common inversion timing is applied, and the selection potential (VG0N) is applied to the common high state, and is output at the non-selection potential. In the present embodiment, the scanning line other than the scanning line to which the selection potential is supplied in the inversion timing in which the common high state is changed to the common low state (47 9) is in a floating state, and is low in common. The state in which the state is changed to the inversion timing of the common high state is -25 - (23) 1286238 The scanning line other than the scanning line (47 7) is in a floating state, and is the same as in the first embodiment, and is large and high-definition. In the case of the degree, the display quality is not degraded, and the common inversion drive can be used, and the 1C outputting the image signal can use the inexpensive, low withstand voltage 1C, and the power consumption can be reduced. In addition, in the case of the embodiment, the Vhenb (7) signal and the VLENB (8) signal are mutually inverted signals, wherein only one of the signals is supplied from the external 1C, and the other signal is from the inverter on the active matrix substrate. When the circuit is generated, it has the advantage of being able to simply reduce the number of input signals and wiring. Further, the configuration diagram of the active matrix substrate, the scanning line driving circuit, and the liquid crystal display device are the same as those of the first embodiment, and refer to Figs. 1, 2, and 6, respectively. Further, the setting of various power supply potentials is also the same as in the first embodiment. (Embodiment 3) Fig. 1 is a signal timing chart of odd frames of Embodiment 3 for realizing the driving method of the first, second, fifth, and sixth aspects of the invention. The solid line indicates the state in which the potential is supplied from the external power source, and the broken line indicates the floating state in which the external power source is cut off with high resistance. Fig. 1 is a timing chart of signals supplied from an external signal system in the odd frame of the second embodiment. In this embodiment, the hold period Tc〇mh of VC0MH (also referred to as the common high state in this period) is equal to the hold period TC0ML of VC0ML (also referred to as the common low state in this period), and the 481 times period of TC0MH becomes 1 Frame period Tframe. In addition, the Vhenb (7) signal and the Vlenb (8) signal do not change during the common high state period and the common low state period, and become a repetitive signal of the TCOMH period. The timing chart of the supplied video signal is the same as that of the example -26- (24) 1286238, and reference can be made to FIG. Fig. 11 is a timing chart showing an output signal supplied from the scanning line driving circuit (301) to the scanning lines (201-1 to 480) in the odd frame in the third embodiment. The non-selected potential is not constant, and is VG0FFH during the common high state period and VG0FF1 is applied to the scan line during the common low state period. Further, in the present embodiment, the signal is set to Vgoffh - Vgoffl = Vcomh - V COML °. According to the driving method of this embodiment, the common high state becomes a common low state, or the common low state becomes a common high. In the common potential inversion timing of the state, the full scan lines (480) are in a floating state, and the capacitance in the common inversion is the same as or less than that in the first embodiment or the second embodiment, even for a large-scale, high-definition liquid crystal display. The device can also use the common inversion drive without degrading the display quality. The IC that outputs the image signal can use the cheap, low withstand voltage 1C' to reduce the power consumption. In addition, compared with the first embodiment or the second embodiment, since the AC driving is performed while the VG 〇FF is inverted, the number of driving circuits is increased, or the consumption current is increased, and the number of power supply potentials is increased, but the waveform of the driving signal is simple. The composition of the external signal circuit is simple, and the leakage current or the ambiguity in the reverse bias of the pixel switch element can ensure that the VG 0 FF can be used frequently (including common The potential state is fixed to VG Ο FFL. In this case, the circuit configuration in the mounting becomes extremely simple. Moreover, the configuration diagrams of the active matrix substrate, the scanning line driving circuit, and the liquid crystal display device are the same as those of the first and second embodiments, and the reference -27-(25) 1286238 can refer to FIGS. And 6. (Industrial Applicability) The present invention is not limited to the above embodiment, and a liquid crystal display device of a fully driven built-in active matrix substrate using a built-in data line driving circuit can be applied, and a scan line is used by an external IC circuit. The driving circuit of the signal is not applicable to the liquid crystal display device of the active matrix substrate. Further, the configuration of the drive circuit is not limited to a complementary (CMOS) circuit, and a single-channel type drive circuit composed of only an N-channel type or a P-channel type can be realized. The pixel switching element can also use a P-type transistor or a complementary transfer gate. Non-polysilicon can also be used, and an amorphous germanium film transistor can be used. Further, a thin film transistor is not formed on the insulating substrate, and an active matrix substrate composed of a pixel switching element or a driving circuit may be formed on the crystalline germanium wafer. Further, the liquid crystal display device is not limited to the transmission type of the embodiment, and may be a reflective type or a semi-transmissive type, and is not limited to the direct view type, and may be a light valve for projection. Further, it is not limited to the normally white mode of the embodiment, and a normally black mode can also be used. In this case, the alignment mode of the liquid crystal can be set to the vertical alignment mode. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view showing the configuration of an active matrix substrate used in an embodiment of the present invention. Fig. 2 is a circuit diagram showing the scanning line driving circuit used in the embodiment of the present invention. Fig. 3 is a timing chart showing various driving signals supplied from an external signal system of the odd-numbered frames of the first embodiment. Fig. 4 is a timing chart of the image signals supplied from the external signal system -28-(26) 1286238 of the odd frames of the first embodiment and the third embodiment. Fig. 5 is a timing chart showing the scanning line signal output of the odd frame of the first embodiment. Fig. 6 is a perspective view (a partial sectional view) of a liquid crystal display device of an embodiment of the present invention. Fig. 7 is a timing chart showing various driving signals supplied from an external signal system of odd frames of the second embodiment. Fig. 8 is a timing chart of an image signal supplied from an external signal system of the odd frame of the second embodiment. Fig. 9 is a timing chart showing the scanning line signal output of the odd frame of the second embodiment. Fig. 1 is a timing chart of various driving signals supplied from an external signal system of odd frames of the third embodiment. Figure 3 Figure 3 The practice of the common road knows how to learn. One of the best. The sequence of the crystal sequence is output when the film is output. The thin letter of the letter is the line of the letter. The description of the P-scan method is driven by the frame and the number of the drive is reversed and the crystal Ϊ ίρτ thin film flow 8 ιρτ leakage element 4 : Guan 1 Open the element of the method of learning the plate surface crystal liquid visit ππιτν drive reverse. Through the search for the common test, the test can be used to illustrate the limit of the limit. [Signal description of the main components] 1 0 1 : Active matrix substrate 2 0 1 — 1~4 8 0 : Scan line 1~4 8 0 202 — 1~1920: Data line 1 to 1920 3 0 1 : Scan line drive circuit 3 03 : Common potential input terminal -29- (27) 1286238 3 04 : Pair of guides 3 5 0 : Shift register 3 5 1 - 1 to 4 8 0 : 1st clock inverter 352 - 1 to 480: 2nd clock inverter 353 - 1 to 480: 1st inverter 402 - 1 to 480 - 1 to 1920: Draw Prime electrode (1~480, 1~1 920)

505 - 1-480 : 1st NAND circuit 5 06 - 1 to 480 : 2nd inverter 507 - 1 to 480 : 2nd NAND circuit 508 - 1 to 480: 3rd NAND circuit 509 - 1 to 480: 4th NAND circuit 510 - 1 to 480: 5th NAND circuit 5 1 1 - 1 - 480: Μ 1 transistor 512 - 1 to 480: 2nd transistor

601 : CLK signal terminal 602 : CLKX signal terminal 6 0 3 : X S T signal terminal 604 : HENB terminal 605 : LENB terminal 606 : LCHG terminal 9 0 1 : opposite substrate -30-

Claims (1)

(1) 1286238 X. Patent Application No. 1 A driving method of a liquid crystal display device in which a liquid crystal layer is sealed between a pair of substrates, and one of the pair of substrates is included on the substrate a plurality of pixel switching elements, and a plurality of scanning lines connected to the plurality of pixel switching elements and an active matrix substrate connected to the pixel electrodes of the plurality of pixel switching elements The other substrate is a counter substrate formed by forming a common electrode on at least a portion of the surface bonded to the liquid crystal layer, and the scanning line driving circuit is connected to the plurality of scanning lines, and the scanning line driving circuit can be used for each The scan line sequentially outputs one or a plurality of selection potentials according to different timings for setting the pixel switching elements connected to the plurality of scanning lines to a low impedance state, and outputting one or a plurality of non-selective potentials for The pixel switching device is connected to the pixel switching element in a high impedance state. The scanning line driving circuit is connected to the A liquid crystal display device comprising a plurality of potential power supply lines, wherein the common electrode has a common high state in a relatively high potential state and a common low state in a state in which the potential of the common electrode is relatively low. When the states of the common electrode are alternately driven by inversion, that is, when the potential of the common electrode is changed from the common high state to the common low state, and when the common low state is switched to the common high state operation, The common inversion operation is such that at least a part of the plurality of scanning lines, more preferably all of the scanning lines or all of the scanning lines except one scanning line are set to be relatively high-resistance by all of the plurality of power supply lines The floating state of the electrical separation state. The method for driving a liquid crystal display device according to claim 1, wherein the pixel switching element is an N-channel type field effect transistor 'at a timing at which the scanning line becomes the floating state The scanning line potential is substantially equal to the non-selection potential, and the common current is extremely high. 3. The driving method of a liquid crystal display device according to claim 1, wherein the pixel switching element is a P channel type field effect transistor, wherein the scanning line potential is substantially equal to a timing at which the scanning line becomes the floating state. The non-selection potential is the same as the common low state. 4. The method of driving a liquid crystal display device according to claim 1, wherein the pixel switching element is formed by: a first switching transistor formed by an N-channel field effect transistor, and a P-channel field effect transistor. a complementary transfer gate formed by the second switching transistor; the scan line is composed of a first scan line connected to the first switch transistor and a second scan line connected to the second switch transistor The first scanning line potential is substantially equal to the non-selection potential when the first scanning line is in the floating state, and the common current is in the common high state, and the second scanning line is in the floating state. At the timing, the second scanning line potential is substantially equal to the non-selection potential, and the common current is extremely low. 5. The driving method of a liquid crystal display device according to any one of claims 1 to 4, wherein -32-(3) 1286238 each of the plurality of scanning lines respectively has: a power source connected to the selected potential is connected with a lower resistance a period during which the state is selected, a period of a non-selected state in which the power source of the non-selected potential is connected to the lower resistor, and a period of the floating state; and the length of the non-selected state period is not constant. The method of driving a liquid crystal display device according to any one of claims 1 to 4, wherein the plurality of scan lines have a plurality of the non-selections between the selected state and the second selected state. The state, in addition, has the above floating state between the plurality of non-selected states. 7. The method of driving a liquid crystal display device according to claim 6, wherein the pixel switching element is an N-channel type field effect transistor, and is present in a plurality of non-selected states between the selected states except The second or subsequent non-selected state other than the selected state is often performed when the common energization is in the common high state, and the common inversion operation is not generated in the second and subsequent non-selected states. 8. The driving method of a liquid crystal display device according to claim 6, wherein the pixel switching element is a p-channel type field effect transistor, and is present in a plurality of non-selected states between the selected states except The second or subsequent non-selected state other than the selected state is often performed when the common energization is substantially in the common low state, and the common inversion operation is not generated in the second and subsequent non-selected states. The method of driving a liquid crystal display device according to any one of claims 1 to 4, wherein the length of the period in which the common energization is extremely common high state (-Tc 〇 MH ) is not equal to the common low state The length of the period (=TC0ML), that is, TcOMH^TcOML 0 i 〇. The driving method of the liquid crystal display device of claim 9, wherein the pixel switching element is an N-channel field effect transistor, and the Tc〇 MH is greater than Tc〇ML' above, that is, Tc〇MH>Tc〇ML. The driving method of a liquid crystal display device according to claim 9, wherein the pixel switching element is a P channel type field effect transistor, and the Tc 〇 MH is smaller than the Tc 〇 ML', that is, Tc 〇 MH < Tc 〇ML. The driving method of the liquid crystal display device according to any one of claims 1 to 4, wherein the non-selection potential is not slightly deviated from the potential of the common electrode, and is substantially 疋 (= Vgoff). The driving method of the liquid crystal display device of claim 12, wherein the pixel switching element is an N-channel type field effect transistor, and the non-selective potential 値 (= Vg 〇 ff ) is The image applied on the data line {the lowest 曰 of the nickname potential (=\/\1£)]£01^) plus the threshold 値(=Vth) of the above pixel switching element is low, and is higher than the above image signal The lowest value of the potential is subtracted (the potential of the common electrode (^VcOM) obtained by subtracting the potential of the common electrode (the above-mentioned common low state) from the potential of the common electrode of the common high state -34-(5) 1286238 (= vC0MH) (= Vc〇MH_VCOML)) is high, that is, 'satisfying VviDEOL + Vth> Vg〇FF> VviDEOL—(Vc〇MH — Vc〇ML) is better to satisfy VvIDEOl2V〇〇fF>VvIDEOH — 6 volts value. The driving method of the liquid crystal display device of claim 12, wherein the pixel switching element is a P channel type field effect transistor, and the non-selective potential 二 (2 VG0FF) is compared with the above data line. The top of the applied image {the target potential (=VviDEOH) plus the threshold 値(=vth) of the above pixel switch element is high, and is higher than the highest level of the above image signal potential (the above common The enthalpy (= Vc 〇 MH - Vc 〇 ML) obtained by subtracting the applied potential (= Vc 〇 ML) of the common electrode in the common low state of the common electrode of the high state is 値 (= Vc 〇 MH - Vc 〇 ML) Low 'is also satisfied with VviDEOH + Vth < VGOFF < VviDEOH + ( Vc 〇 MH - Vc 〇 ML), and better meets VvIDEOhSVgOFfS Vvideol + 6 volts. The driving method of a liquid crystal display device according to any one of claims 1 to 4, wherein said non-selected potential is 値 (= VG0FFH ) of said common high state and said common low state (= VG0FFL The method of driving a liquid crystal display device according to any one of claims 1 to 4, wherein -35-(6) 1286238 is in the above common reversal In the operation, at least part of the plurality of data lines, and more preferably all of the plurality of data lines are in a floating state. A liquid crystal display device is a liquid crystal display device that displays an image using a driving method according to any one of claims 1 to 16. 18. The liquid crystal display device of claim 7, wherein the square of the number of scanning lines (:=V) is multiplied by a length of a diagonal direction of the image display portion in which the pixel electrodes are arranged in a matrix (= s ( melon) The resulting coefficient (=VxVxS ) is greater than or equal to 3 0000. The liquid crystal display device of claim 17 or claim 18, wherein at least a part of the scanning line driving circuit is a built-in liquid crystal of a driving circuit formed of a thin film transistor formed on the active matrix substrate. Display device. 2 0 - A portable electronic device having a function of displaying an image using a liquid crystal display device according to any one of claims 17 to 19, and being driven by a battery. _ -36 - 1286238 VII. Designated representative map: (1) The representative representative figure of this case is: (5) Figure (2), the representative symbol of the representative figure is a simple description: Vc〇m (1), Vc〇MH : Common potential of the cylinder state VC0MIj : Common low-level potential VG1 ~ n (2_l ~ 2-480): potential 8. If there is a chemical formula in this case, please disclose the chemical formula that best shows the characteristics of the invention: