JP2607719Y2 - Liquid crystal display - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device used for a liquid crystal projector, a liquid crystal television and the like, and more particularly, to a liquid crystal display device using an active matrix panel.

[0002]

2. Description of the Related Art An active matrix display (active m
In the atrix display method, extraneous signal interference is eliminated by arranging a non-linear active element in each pixel, and high image quality can be realized.

FIG. 3 is a view showing a TFT display section of a conventional active-matrix liquid crystal display device of the additional capacitance type. In FIG. 3, reference numerals 1 and 1 denote TFT elements used as active matrix elements, and reference numerals 2 and 3 denote Nth and N-1th gate lines connected to the TFT elements 1 and 1, respectively. TFT element 1 connected to gate line N-1
Is located at the intersection of the Nth gate line 2 and the Mth drain line 4, and is connected to the pixel ITO (pixel electrode) 5. The liquid crystal capacitor and the counter electrode are omitted.

In this active matrix display system,
A matrix electrode, a plurality of pixels ITO (pixel electrodes) 5, and a TFT element 1 as a switching element are arranged for each pixel ITO 5 on the inward surface of one of the electrode substrates, and the switching elements are driven in a matrix to form a TFT element 1. Are switched over through the pixel ITO5.

[0005]

Means for Solving the Problems The invention according to claim 1 is:
In order to achieve the above object, a liquid crystal display panel having a plurality of signal lines and a plurality of scanning lines and a plurality of scanning electrodes are provided.
A plurality of output terminals are provided, and the output terminals are on-level from the plurality of output terminals.
Scanning signals having a power level and an off level sequentially at predetermined intervals.
A liquid crystal display having a scan electrode drive circuit for outputting and sequentially scanning the scan electrodes, and a signal electrode drive circuit for outputting video signals to the plurality of signal electrodes, and displaying an image by AC driving the liquid crystal display panel In the display device, the scan electrode drive circuit outputs a scan signal to each scan electrode for each of the output terminals .
Each output at a predetermined timing after outputting the off level
Means are provided for bringing the force terminal into a high impedance state.

A feature of the active matrix type liquid crystal display device lies in a memory holding operation. That is, the TFT elements 1 and 1 as the active matrix elements are used as switches, and are closed for a certain short period to write necessary signals to the liquid crystal, and are opened during other periods to prevent unnecessary signals from leaking to the liquid crystal. Play the role of prevention. The liquid crystal is used here as a dynamic memory. Generally, the time constant of the liquid crystal is around 100 ms, so that refreshing at a shorter cycle can sufficiently retain a signal. Further, if a storage capacitor is added in parallel with the liquid crystal as needed, the storage characteristics are further improved.

The written signal voltage or control voltage slightly fluctuates under the influence of the capacitive coupling between the terminals of the active element. Since this fluctuation increases flicker and display non-uniformity, it is desirable to realize an active element having a small coupling capacitance and to suppress distortion. In addition, a driving method has been proposed in which the polarity of a display signal is inverted for each line, and image quality is averaged to reduce flicker.

[0008]

In the case of a TFT, when the gate pulse signal falls, there is a phenomenon that the voltage once charged in the pixel shifts to the negative side due to the influence of the parasitic capacitance caused by the overlap between the gate and the drain. . This phenomenon causes flicker and afterimages. To suppress this voltage drop, a capacitance component two to three times the pixel capacitance is added to the pixel I.
Add to TO5. Usually, it is formed of the same film as the gate line, and is wired in the panel in parallel with the gate line as an auxiliary capacitance line. In consideration of the yield and the like, as shown in FIG. Add ingredients.

That is, by superimposing the pixel ITO5,
There is a method of using additional capacity. In this additional capacitance type active matrix liquid crystal display device, when the common inversion method for inverting the counter electrode is combined, the gate-off level must be AC-inverted at the same timing as the common inversion timing.

FIG. 4 is an output waveform diagram of the gate signal and the counter electrode inversion signal. At this time, if the amplitude and timing of the AC inversion of the gate-off level are not optimized, there is a disadvantage that the image quality is reduced.

It is an object of the present invention to provide an active-matrix liquid crystal display device of high image quality by an additional capacitance system and a common inversion system.

[0012]

Means for Solving the Problems The invention according to claim 1 is:
To achieve the above object, a liquid crystal display panel having a plurality of signal electrodes and a plurality of scanning electrodes, a scanning electrode driving circuit for horizontally scanning the scanning electrodes, a signal electrode driving circuit for outputting a video signal to the signal electrodes, In the liquid crystal display device for displaying an image by AC driving the liquid crystal display panel, the scan electrode drive circuit is provided with means for setting a scan signal to an offset state at a predetermined timing.

[0013] The invention according to claim 2 is directed to the liquid according to claim 1.
In the crystal display device, the scan electrode driving circuit is configured to perform horizontal scanning.
The on level and off level are applied to each output terminal for each period.
Output, and each output terminal is in a high impedance state.
The off level is output for one horizontal scanning period.
It is characterized by the timing after the force is applied.

[0014] invention of claim 3 is provided with a liquid crystal display panel having a plurality of signal electrodes and a plurality of scan electrodes, a plurality of output terminals corresponding to the plurality of <br/> scanning electrodes, the scanning electrodes A liquid crystal display device comprising: a scan electrode drive circuit for sequentially scanning a plurality of pixels; and a signal electrode drive circuit for outputting a video signal to the plurality of signal electrodes. In the above, the scan electrode drive circuit is composed of a plurality of stages of flip-flops , and supplies a start signal to each stage.
A shift register for sequentially transferred to sequentially output scan signals to the plurality of scan electrodes flop, provided on the output side of the flip-flops of said shift register, on /
Contacting the output of the flip-flop of the plurality of stages by the off
A switch for connection / disconnection, the logic in which said plurality of stages ORs the output data of the adjacent stage flip-flop, and outputs a logical sum <br/> output as a control signal for controlling an on / off of the switch A gate, wherein the flip-flop comprises
The switch is turned off via the logic gate to cut off the shift output from the shift register in accordance with the timing when both outputs of the adjacent stages become low level,
The output terminal of the inspection electrode drive circuit is set to a high impedance state.

[0015]

According to the present invention, for example, a switch for turning on / off the output of the shift register and an output of the shift register are provided on the output side of the shift register for sequentially outputting the scanning signals to the plurality of scanning electrodes. Is provided, the switch is turned off according to the output of the logic gate, and the shift output from the shift register enters a high impedance state at a predetermined timing.

Therefore, the output of the off level of the gate signal is output.
Out each of the scan electrode driving circuit at a certain timing to force
By the force terminal is in a high impedance state, it will be varied while maintaining a constant potential at the common inversion even pixel capacitance, the additional capacitance, additional capacitance method and co
In the Mont inversion method, the common inversion signal can be used without forcibly inverting the gate off level externally.
The gate off level can be varied by
An active matrix liquid crystal display device with high image quality can be realized.

[0017]

An embodiment will be described below with reference to FIGS.

FIGS. 1 and 2 show an embodiment of the liquid display device.

FIG. 1 is a circuit diagram of a gate signal generation circuit of a liquid crystal display device. In this figure, a gate signal generation circuit 10 includes level shift units 11 and 12 and a shift register 1.
3, OR gates 14 and 15, switches 16 and 17, and a buffer 18. Gate signal generation circuit 10
Has a positive power supply voltage VDD, a negative power supply voltage VEE, and a ground VSS.
Is supplied.

The level shift unit 11 has a shift clock φ
x and * φx (* indicates an inverted output; the same applies hereinafter) is a circuit for level shifting a predetermined power supply level, and the level shift unit 12 is a circuit for level shifting the start clock Sv to a predetermined power supply level. .

The shift register 13 is composed of a plurality of flip-flops (FF) 1 to n and shifts the start clock Sv, which has been level-shifted to the positive power supply voltage VDD and the negative power supply voltage VEE by the level shift circuits 11 and 12, to a shift clock. Latched by φx and * φx, and sequentially shifted and output to the next stage shift register and buffer 18 side.

The OR gates 14 and 15 take the OR logic of the data shifted by the flip-flops (FF) 1 to n, and use the OR logic as an OR gate signal for the switches 16 and 15.
17 is output.

Each of the switches 16 and 17 is constituted by a transfer gate or an analog switch.
On / off according to the OR gate signal from 4, 15;
When turned on, the shift outputs of the flip-flops (FF) 1 to n are output to the buffer 18, and when turned off, they enter a high impedance state.

The buffer 18 raises the shift output of the shift register 13 output via the switches 16 and 17 to a predetermined voltage level, and outputs it as gate signal outputs x1 to xn.

That is, the gate signal generating circuit 10 is provided with switches 16 and 17 and OR gates 14 and 15 for controlling the switches 16 and 17 at the output of the shift register 13, and turns the switches 16 and 17 on and off. As control signals, the OR signals of the flip-flops (FF) 1 to n output and the flip-flops (FF) 1 to n output of the next stage are used, and the gate-on signal 2H (horizontal) is output by the OR gates 14 and 15 and the switches 16 and 17. After the period, the switches 16 and 17 are turned off to bring the signal into a high impedance state.

Next, the operation of this embodiment will be described.

As shown in FIG. 1, the gate signal generating circuit 1
The shift clocks φx and * φx and the start clock Sv are input to 0, and the input shift clocks φx and *
φx and the start clock Sv are supplied to the level shift unit 11,
12, the positive power supply voltage VDD 19 and the negative power supply voltage level VEE
21 and input to the shift register 13.

In the shift register 13, the start clock Sv, which has been level-shifted to the positive power supply voltage VDD and the negative power supply voltage VEE by the level shift circuits 11 and 12 by the plurality of flip-flops (FF) 1 to n, is shifted by the shift clock φx. And * φx are sequentially shifted and output to the shift register and buffer 18 side of the next stage.

The output of the shift register 13 is the switch 1
The switches 16 and 17 output the signals to flip-flops (FF) 1, 2,.
n-1 output and the next stage flip-flop (FF) 2,
At the timing of the OR gate signals of 3,..., N outputs (that is, periods A and B in FIG. 2), they are output through the buffer 18. Otherwise, switch 16,
17 is turned off and the output goes into a high impedance state.
For example, the OR gate 14 has a flip-flop (FF)
The output of 1) and the output of the next flip-flop (FF2) are input, and the OR gate 14 outputs a control signal to the switch 16 only when the outputs of these flip-flops (FF1) and (FF2) are present. Turn on the switch 16, otherwise turn off the switch 16 and output the gate signal
Put the terminal into high impedance state.

That is , when there is an output from the flip-flop (FF1) and once in the shift register 13,
Operation and there is no output of flip-flop (FF1)
And the output of the flip-flop (FF2)
Control signal is supplied to the switch 16 through the OR gate
And the switch 16 is turned on.
The output of the flip-flop (FF1) is
Connected. During this period, the gate output signal x1 is flipped.
It becomes a non-inverted signal of flip-flop (FF1), which will be described later.
Thus, a signal having an on-level period and an off-level period
Become. Similarly, the output of the flip-flop (FF2) is
And once in the shift register 13
As a result, the output of the flip-flop (FF2) disappears,
When there is an output of the lip flop (FF3),
A control signal is supplied to the switch 17 through the
Switch 17 is turned on and flips through switch 17.
The output of the flop (FF2) is connected to the buffer 18,
The gate output signal x2 is output from the flip-flop (FF2)
It becomes an inverted signal and has an on-level period and an off-level period.
Signal. That is, the gate output signals x1, x2,
, Xn each have a start clock Sv having two stages of flips.
For a period is shifted to the flop flip-flop (FF) 1, 2, ..., in a non-inverted signal of n, otherwise those gate signal output terminal in a high impedance state, sequentially shifts it to the next stage.

[0031] Here, the gate signal, as shown in FIG. 2, after the on-level generated corresponding to a state in which there is an output of the flip-flop (A period), the output of the flip-flop I
An off-level corresponding to the high state is generated (period B) , and then the gate signal output terminal is brought into a high impedance state.
Period (C period). This high impedance state is maintained until immediately before the ON signal generation (period A) to which the next data is applied. If in high impedance state
Pixel capacitance, since the constant potential to the additional capacitor is held, common inversion time also Figure 2 pixel capacitance as shown to the gate signal of the broken line, while the counter electrode reversed to maintain a constant potential to the additional capacitor
Since the off-level of the gate fluctuates according to the signal, the operation of the additional capacitance method can be realized even in the common inversion drive without forcibly inverting the off-level of the gate from the outside as shown in the conventional example.

As described above, the gate signal generating circuit 10 of the liquid crystal display device according to the present embodiment uses the shift clock φ
x, level shift units 11 and 12 for shifting the start clock Sv to a predetermined power supply level, a shift register 13 including a plurality of flip-flops (FF) 1 to n, and flip-flops (FF) 1 to n The OR gates 14 and 15 output the OR logic as an OR gate signal, and turn on / off according to the OR gate signal. When ON, the shift outputs of the flip-flops (FF) 1 to n are output. Switch 1 that outputs to buffer 18 and is in a high impedance state when off
6, 17 and a buffer 18 for raising the shift output to a predetermined voltage level and outputting the same as gate signal outputs x01 to x0x, and OR gates 14, 15 and switches 16,
17, the switches 16 and 17 are turned off after 2H (horizontal cycle) of the gate-on signal to bring the signals into a high-impedance state. Thus, an active matrix liquid crystal display device of high image quality can be realized by the additional capacitance method and the common inversion method without forcibly inverting the off level of the gate from the outside.

Further, since this function is provided in the gate signal generation circuit (gate driver) 10 itself, the present invention can be implemented without changing the specifications on the panel side.

In this embodiment, the gate-on signal 2
H gate turns off the switches 16 and 17 after (horizontal period)
The signal output terminal is set to a high impedance state, but any configuration provided with means for setting the scanning signal output terminal to a high impedance state at a predetermined timing for outputting the off level of the scanning signal is provided. Needless to say, timing may be used.

In this embodiment, the liquid crystal display device is applied to a TFT active matrix. However, the present invention is not limited to this, and the type, number, and arrangement of liquid crystal panels are arbitrary. Insulator Metal)
Active matrix drive LC using diode
It goes without saying that D can be similarly changed.

Further, it goes without saying that the circuits, matrices, the number of gates, and the types thereof constituting the gate signal generating circuit are not limited to the above-described embodiment.

[0037]

According to the first, second and third aspects of the present invention, the scan electrode driving circuit sets the scan signal output terminal to high impedance at a predetermined timing for outputting the off level of the scan signal.
It is provided with the means to scan state, high impedance
In this state, a fixed potential is held in the pixel capacitance and the additional capacitance.
Therefore, even during the common inversion , the gate is turned off in response to the counter electrode inversion signal while maintaining a constant potential in the pixel capacitance and the additional capacitance.
Fureberu can Rukoto varies the forces added without reversing the off level of the gate capacitance method and common inversion method on high-quality active-matrix liquid crystal display device can be realized from the outside.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a gate signal generating circuit of an embodiment of a liquid crystal display device according to the present invention.

FIG. 2 is a timing chart of a signal waveform of a voltage applied to a liquid crystal panel of the liquid crystal display device of the embodiment.

FIG. 3 is a diagram showing a TFT display portion of a conventional active-matrix liquid crystal display device of an additional capacitance type.

FIG. 4 is an output waveform diagram of a conventional gate signal and counter electrode inversion signal.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Gate signal generation circuit 11, 12 Level shift part 13 Shift register 14, 15 OR gate 16, 17 Switch 18 Buffer

Claims (3)

(57) [Scope of request for utility model registration] 1. A comprising a liquid crystal display panel having a plurality of signal lines and a plurality of scan lines, a plurality of output terminals corresponding to the plurality of scanning electrodes,
Has an on level and an off level from the plurality of output terminals
Scan signals are sequentially output at predetermined intervals to sequentially turn on the scan electrodes .
A liquid crystal display device having a scan electrode driving circuit for performing a next scan, and a signal electrode driving circuit for outputting a video signal to the plurality of signal electrodes, wherein the liquid crystal display panel is AC driven to display a video; The drive circuit controls each scan for each of the output terminals.
A liquid crystal display device comprising: means for setting each output terminal to a high impedance state at a predetermined timing after outputting the off level of a scanning signal to an electrode . 2. The scanning electrode driving circuit according to claim 1, wherein said scanning electrode driving circuit is provided for every horizontal scanning period
Output the on level and off level to each output terminal.
And put each output terminal into a high impedance state
As for the timing, the off level was output for one horizontal scanning period.
The liquid crystal display device according to claim 1 , wherein the timing is later . Comprising a liquid crystal display panel 3. A having a plurality of signal electrodes and a plurality of scan electrodes, a plurality of output terminals corresponding to the plurality of scanning electrodes,
A scanning electrode driving circuit for sequentially scanning the scanning electrodes, and a signal electrode driving circuit for outputting an image signal to the plurality of signal electrodes, the liquid crystal display device for displaying an image by AC driving the liquid crystal display panel The scan electrode driving circuit includes a plurality of stages of flip-flops, and supplies a start signal to each stage of flip-flops.
A shift register for sequentially transferring and sequentially outputting scan signals to the plurality of scan electrodes; and a shift register provided on an output side of each flip-flop of the shift register, for connecting / disconnecting outputs of the plurality of flip-flops by turning on / off. a switch for the ORs the output data of the adjacent stage flip-flop of the plurality of stages comprises a logic gate for outputting a logical sum output as a control signal for controlling an on / off of the switch, the flip-flop Output of both adjacent stages is low level
The flip of the shift register off the switch via the logic gates in accordance with the timing to be
The output of the scan electrode drive circuit is disconnected from the output terminal of the scan electrode drive circuit.
The liquid crystal display device which is characterized in that so as to children in a high impedance state.