JPH11249633A - Display driving device, and driving method for display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display driving device capable of displaying a picture on a display device while suppressing power consumption. SOLUTION: This display driving device (signal driver) samples and holds the RGB inverted signal to be supplied from an inversion amlifier by switching a switch 21 and a switch 22 alternately on/off. The device turns a switch 23 on only at the time the switch 21 is turned off (a holding state) to make an amplifier 33 operate and amplifies the picture signal held on a capacitor 31 and outputs it to a signal line DL while turning a switch 25 on. On the other hand, the device turns a switch 24 on only at the time the switch 22 is turned off (a holding state) to make an amplifier 34 operate and amplifies the picture signal held on a capacitor 32 and outputs it to the signal line DL while turning a switch 26 on.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display driving device capable of displaying an image on a display device with reduced power consumption and a driving method of the display device.

[0002]

2. Description of the Related Art A driving circuit for a TFT-LCD (thin film transistor / liquid crystal display) comprises a scanning driver for sequentially scanning the gate lines of the LCD and a signal driver for driving the signal lines of the LCD.

The scanning driver sequentially selects the gate lines of the LCD and applies a predetermined gate pulse to the selected gate lines.

The signal driver has two systems of sample / hold circuits connected to each signal line of the LCD, and alternately samples and holds an image signal, which is an input of a display image, in units of one horizontal scanning period for each system. I do.
The sample / hold circuit includes an amplifier circuit, holds an image signal sampled in a certain horizontal scanning period, amplifies the held image signal in the next horizontal scanning period by an amplifier circuit, and performs one line (one horizontal scan). Output to the signal line in parallel in units.

FIG. 8 shows the configuration of one signal line of a signal driver. This circuit includes two systems of sample / hold circuits and two systems of amplifiers.
5, capacitors 111 and 112, and amplifier (amplifier)
121 and 122. One system includes a switch 101, a capacitor 111, an amplifier 121, and a switch 103. The other system includes a switch 102, a capacitor 112, an amplifier 122, and a switch 104. Note that the switch 105
2 shows a switch for precharging a signal line.

The signal driver includes switches 101 and 10
2 are alternately turned on, the image signals are alternately sampled in each system, and the sampled image signals are
1 and 112 are held. Switch 1
03 and 104 are alternately turned on, and the image signals stored in the capacitors 111 and 112 are amplified by the amplifiers 121 and 12.
2 and output to the signal line.

[0007]

The amplifier 12 shown in FIG.
Nos. 1 and 122 were always in operation during the period when the connected sample / hold circuit was sampling the image signal, even though they were not substantially functioning.
That is, since the signal driver always supplies the bias current to the amplifiers 121 and 122, the bias current supplied during the period when the connected sample / hold circuit is sampling the image signal is wasted.

The present invention has been made in view of the above circumstances, and has as its object to provide a display driving device and a driving method of a display device capable of displaying an image on a display device with reduced power consumption.

[0009]

In order to achieve the above object, a display driving apparatus according to a first aspect of the present invention comprises an image signal input means for inputting an image signal, and n (n is a natural number of 2 or more). A sample-and-hold circuit for sampling and holding an image signal input by the image signal input unit in a predetermined order in units of a system, and a one-to-one correspondence with the n sample-and-hold circuits. And amplifying output means for amplifying and holding the image signal held by the sample-and-hold means and outputting the amplified image signal. Means for operating only the amplifier corresponding to the sample and hold circuit of the system holding the signal. To.

According to the present invention, the amplification output means substantially operates only the amplifier corresponding to the sample-hold circuit of the system in the holding state, and amplifies and outputs the held image signal. As a result, an amplifier that does not need to perform an amplification operation at each timing is turned off, and an image can be displayed on the display device with reduced power consumption.

The amplification output means may be operated by supplying an operating voltage only to the amplifier corresponding to a sample-hold circuit of a system holding an image signal. In this case, since it is not necessary to always supply the operating voltage to the amplifier, an image can be displayed on the display device with reduced power consumption.

The amplification output means may be operated by supplying a current only to the amplifier corresponding to a sample-hold circuit of a system holding an image signal. In this case, since it is not necessary to constantly supply a bias current or the like to the amplifier, an image can be displayed on the display device with reduced power consumption.

In order to achieve the above object, a display driving apparatus according to a second aspect of the present invention comprises an image signal input means for inputting an image signal, and an n (n is a natural number of 2 or more) system sample and hold circuit. Sample and hold means for sampling and holding the image signal input by the image signal input means in a predetermined order in a system unit; and n system amplifiers corresponding to the n system sample and hold circuits on a one-to-one basis. And amplifying output means for amplifying and holding the image signal held by the sample and hold means, and wherein the amplification and output means is configured so that the sample and hold circuit corresponding to the amplifier has an image. The operation of the amplifier is stopped at the timing when the signal is being sampled, and the corresponding sample is stopped. Hold circuit to operate the amplifier at a timing that holding an image signal, characterized in that.

According to this invention, the amplification output means stops the operation of the amplifier corresponding to the sample-hold circuit of the system in the sampling state, and operates the amplifier corresponding to the sample-hold circuit of the system in the hold state.
The held image signal is amplified and output. As a result, an image can be displayed on the display device with reduced power consumption.

The amplification output means stops supply of an operating voltage to the amplifier at a timing when the sample and hold circuit corresponding to the amplifier is sampling an image signal, and the corresponding sample and hold circuit outputs the image signal to the amplifier. An operating voltage may be supplied to the amplifier at a timing when the signal is held. In this case, since it is not necessary to always supply the operating voltage to the amplifier, an image can be displayed on the display device with reduced power consumption.

The amplification output means stops supplying current to the amplifier at a timing when the sample and hold circuit corresponding to the amplifier samples an image signal, and the corresponding sample and hold circuit holds the image signal. A current may be supplied to the amplifier at the same timing. As a result, an image can be displayed on the display device with reduced power consumption.

In order to achieve the above object, a display device driving method according to a third aspect of the present invention includes an image signal inputting step of inputting an image signal, and n (n) (n is a natural number of 2 or more) sample-and-hold steps for sampling and holding in a predetermined order on a system-by-system basis using two or more sample-and-hold circuits, and n systems corresponding to the n sample-and-hold circuits on a one-to-one basis An amplification output step of amplifying and outputting the image signal held by the sample-and-hold step by using the amplifier of (1), wherein the amplification output step includes holding the image signal. Only the amplifier corresponding to the sample and hold circuit of the That, characterized in that.

According to the present invention, the amplification output step includes:
Using the n-system amplifiers used in the sample-and-hold step, only the amplifier corresponding to the sample-and-hold circuit of the system in which the image signal is held in the sample-and-hold step is operated to amplify and output the held image signal. As a result, an image can be displayed on the display device with reduced power consumption.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A display driving device according to an embodiment of the present invention will be described below with reference to the drawings. FIG.
1 is a block diagram showing an example of a display driving device (signal driver) and peripheral circuits according to an embodiment of the present invention.
These circuits include an RGB decoder 1 and an inverting amplifier 2
, Scan driver 3, LCD 4, amplifier 6, LC
It comprises a D controller 7 and a signal driver 5.

The RGB decoder 1 receives a video signal supplied from a video reproducing unit or the like, separates the video signal into a color signal and a composite synchronization signal, generates an RGB signal from the separated color signal, and outputs a horizontal synchronization signal from the composite synchronization signal. H and the vertical synchronization signal V are generated. The RGB decoder 1 supplies the generated RGB signals to the inverting amplifier 2, and supplies the horizontal synchronization signal H and the vertical synchronization signal V to the LCD controller 7.

The inverting amplifier 2 receives signals from the RGB decoder 1
The RGB signal is input, an RGB inverted signal in which the polarity of the RGB signal is inverted for each frame is generated, and supplied to the signal driver 5.

The LCD 4 is composed of a TFT liquid crystal display element, and has pixel electrodes and TFTs (Thin Film Transformers) arranged in a matrix of i columns × j rows (i and j are natural numbers of 2 or more).
istor) and a common electrode opposed to the pixel electrode via the liquid crystal. Each pixel electrode is connected to the corresponding signal line DL via the current of the corresponding TFT. The gates of the TFTs in each column are connected to a common gate line G.
L. The LCD 4 displays an image by controlling the orientation of the liquid crystal by charging the capacitance (pixel capacitance C _LC ) formed by the pixel electrode, the common electrode, and the liquid crystal through the gate line GL and the signal line DL. .

The amplifier 6 inverts the polarity of the common voltage signal Vcom every field and every horizontal period (line) in accordance with the field line inversion signal FRP supplied from the LCD controller 7 and supplies the same to the LCD 4.

The LCD controller 7 receives the horizontal synchronizing signal H and the vertical synchronizing signal V from the RGB decoder 1 and controls the operation of the signal driver 5 and the vertical control signal for controlling the operation of the scanning driver 3. A control signal and a field line inversion signal FRP whose polarity is inverted for each field line are generated. LCD controller 7
Supplies the generated horizontal control signal to the signal driver 5,
The vertical control signal is supplied to the scan driver 3, and the field line inversion signal FRP is supplied to the inversion amplifiers 2 and 6. The horizontal control signal is the basic clock signal MCL.
K, data line start signal SRT, system selection signal L
OE, a clear signal CLR, an output enable signal OE, and the like. Details of each signal will be described later.

The scanning driver 3 includes an LCD controller 7
The gate lines GL of the LCD 4 are sequentially selected in accordance with the vertical control signal supplied from the
Is applied with a gate pulse.

The signal driver 5 includes an LCD controller 7
Sampling and holding the RGB inversion signal (image signal) supplied from the inversion amplifier 2 for one line (for one horizontal scan) in accordance with the horizontal control signal supplied from the
One line of held image signal (one horizontal scan)
The data is output to the signal line DL in parallel in units. The signal driver 5 includes a CK generation / delay circuit 11 as shown in FIG.
, A shift register 12, a level shifter 13, a sample / hold group 14, an amplifier group 15, and a bias circuit 16.

The CK generation / delay circuit 11 has a cycle corresponding to a selection period of each dot (pixel) on one line (one horizontal scan) from the basic clock signal MCLK supplied from the LCD controller 7 as shown in FIG. The sampling clock CK shown in (a) is generated and supplied to the shift register 12. Further, the CK generation / delay circuit 11 generates a start pulse ST shown in FIG. 3B indicating the start timing of the shift operation according to the data line start signal SRT supplied from the LCD controller 7 and supplies the start pulse ST to the shift register 12. I do.

The shift register 12 is an i-bit shift register corresponding to the number i of each signal line DL of the LCD 4. The shift register 12 captures the start pulse ST shown in FIG. 3B and sequentially shifts it according to the sampling clock CK shown in FIG. 3A, and sequentially shifts the start pulse ST shown in FIG. The sampling pulses SP (1) to SP (i) shown in FIG.
3 is output in parallel.

Returning to FIG. 2, the level shifter 13 outputs the sampling pulse SP supplied from the shift register 12.
(1) to SP (i) are shifted from the voltage level of the logic circuit system to the voltage level of the drive circuit system and supplied to the sample / hold group 14.

The sample / hold group 14 is composed of i sample / hold circuits corresponding to each signal line DL of the LCD 4. Each sample / hold circuit has 2
A system circuit, which alternately operates according to a system selection signal LOE, samples an RGB inversion signal (image signal) according to sampling pulses SP (1) to SP (i) supplied via a level shifter 13, and outputs a sampled signal. Holding.

The amplifier group 15 includes the sample / hold group 1
4 and i amplifiers (amplifiers) corresponding one to one. Each amplifier circuit has two systems, and is connected to the output terminal of each system of each sample / hold circuit. One of the amplifier circuits operates according to the output enable signal OE, and amplifies the image signal held by the sample / hold circuit and outputs the amplified image signal to the signal line DL of the LCD 4.

The bias circuit 16 supplies a bias current to each amplifier circuit of the amplifier group 15.

FIG. 4 shows a configuration of a sample / hold circuit and an amplifier circuit for one signal line DL (hereinafter, driver circuit). This driver circuit includes two systems of sample / hold circuits and two systems of amplifier circuits, and includes switches 21 to 27, capacitors 31, 32, an amplifier 33,
34. The first system is a switch 21,
It comprises a capacitor 31, a switch 23, an amplifier 33 and a switch 25. The second system includes a switch 22, a capacitor 32, a switch 24, an amplifier 34, and a switch 26.
Consists of The switch 27 is a switch for precharging the signal line DL.

The switches 21 to 27 are connected to the system selection signal LO
E, the clear signal CLR, the output enable signal OE, and the sampling pulse SP are turned on only when each of them is in the state shown in FIG. For example, the switch 21 of the first system is turned on only when the system selection signal LOE is at a low level (L) and the sampling pulse SP is at a high level (H).

In FIG. 4, the first system capacitor 3
1 samples the RGB inversion signal (image signal) supplied from the inversion amplifier when the switch 21 is on,
When the switch 21 is off, the sampled image signal is held. Similarly, the capacitor 32 of the second system samples the RGB inversion signal (image signal) when the switch 22 is on, and holds the sampled image signal when the switch 22 is off. Note that VSS in the figure indicates the ground of the logic circuit system.

The first system amplifier 33 includes a switch 23
Is turned on, is connected to a power supply line, and is supplied with an operation voltage and a bias current to operate. When the switch 23 is turned off, the first system amplifier 33 does not operate because no operating voltage and bias current are supplied. The amplifier 33 has the switch 23 turned on and the switch 25
When is turned on, the image signal held in the capacitor 31 is amplified and output to the signal line DL. Similarly, the amplifier 34 of the second system operates when the switch 24 is on and amplifies the image signal held in the capacitor 32 when the switch 26 is on, and outputs the amplified image signal to the signal line DL. . Note that VDDA in the drawing indicates a power supply line of a drive circuit system.

Further, VDDC in FIG. 4 indicates a power line for precharging, and when the switch 27 is turned on, the signal line DL of the connected LCD 4 is precharged.

The LCD controller 7 supplies a horizontal control signal (system selection signal LOE, output enable signal OE, etc.) to the signal driver 5, ie, the above-described driver circuit.
The switches 21 and 22 are turned on alternately to alternately sample the image signals in each system, and hold the sampled image signals on the capacitors 31 and 32. Also, the capacitor 31 holding the image signal
And 32 are turned on to selectively operate the amplifiers 33 and 34 to amplify the image signal and to turn on the corresponding switches 25 and 26 so that the amplified image signal is turned on. Output to the signal line DL. Therefore, the operating voltage is changed to the amplifiers 33 and 34.
It is not necessary to constantly supply power to the power supply, and power consumption can be suppressed.

Hereinafter, the driving operation performed by the display driving device (signal driver) according to this embodiment will be described.
The RGB decoder 1 performs Y / C separation (luminance / color separation) on a video signal supplied from a video playback unit (not shown) to separate it into a composite synchronization signal and a chroma signal. Further, the RGB decoder 1 converts the separated chroma signal into an RGB signal.
Generate a B signal. An RGB decoder 1 supplies an RGB signal to an inverting amplifier 2 and outputs a composite synchronization signal to an LCD.
It is supplied to the controller 7.

The LCD controller 7 receives a composite signal from the RGB decoder 1 and generates a horizontal control signal, a vertical control signal, and a field line inversion signal FRP. The horizontal control signal generated by the LCD controller 7 includes a basic clock signal MCLK, a data line start signal SRT, a system selection signal LOE, and a clear signal CL.
R, an output enable signal OE, and the like.

The LCD controller 7 supplies the generated vertical control signal to the scanning driver 3. Scan driver 3
Applies a gate pulse to the gate line GL of the LCD 4 in order according to the supplied vertical control signal.

The LCD controller 7 supplies the generated field line inversion signal FRP to the inversion amplifiers 2 and 6. The amplifier 6 inverts the polarity of the common voltage Vcom for each field and for each line in accordance with the supplied field line inversion signal FRP, and supplies the LCD 4 with the same. The inverting amplifier 2 inverts the polarity of the RGB signal input from the RGB decoder 1 for each field according to the supplied field line inversion signal FRP.
A GB inverted signal is generated and supplied to the sample / hold group 14 of the signal driver 5.

The LCD controller 7 supplies the generated horizontal control signal to the signal driver 5. That is, LC
When each horizontal scanning period H starts, the D controller 7
The basic clock signal MCK and the data line start signal SRT are supplied to the CK generation / delay circuit 11. Furthermore,
As shown in FIG. 6A, a clear signal CLR which has been set to a high level for a certain period is supplied to the amplifier group 15, and
As shown in (c), the system selection signal L whose polarity has been inverted
OE is supplied to the sample / hold group 14 and the amplifier group 15, respectively. Also, immediately before the end of each horizontal scanning period,
The LCD controller 7 supplies the amplifier group 15 with an output enable signal OE that has been at a low level for a certain period.

The CK generation / delay circuit 11 receives the supplied basic clock signal MCK and data line start signal SCK.
A sampling clock CK shown in FIG. 3A is generated from the RT, and a start pulse ST is generated at the start of each horizontal scanning period and supplied to the shift register 12 as shown in FIG.

The shift register 12 generates sampling pulses SP (1) to SP (i) indicating the sampling timing of the image signal for each display dot (pixel) from the sampling clock CK and the start pulse ST in FIG.
The signal is generated as shown in (c) and supplied to the sample / hold group 14 via the level shifter 13.

As described above, the LCD controller 7 (shift register 12) sends the system selection signal LOE and the sampling pulses SP (1) to the sample / hold group 14 to the sample / hold group 14.
SP (i). Also, the LCD controller 7
Supplies the amplifier group 15 with the clear signal CLR and the output enable signal OE. Hereinafter, the operations of the sample / hold group 14 and the amplifier group 15 will be described in detail with reference to a driver circuit for one signal line DL shown in FIG. 4 and a timing chart shown in FIG.

Immediately before the start of the first horizontal scanning period shown in FIG. 6, since the output enable signal OE shown in FIG. 6B goes low, the switches 25 and 26 are turned off.
The signal line DL of CD4 is electrically disconnected (timing T1).

In the meantime, as shown in FIG. 6A, the clear signal CLR becomes high level, the switch 27 is turned on, and the signal line DL is precharged (power supply voltage VDDC).
(Preliminary charge) (timing T2).

As shown in FIG. 6C, the switch 23 is turned off because the system selection signal LOE goes low, and the supply of the operating voltage to the first system amplifier 33 is stopped. Then, the operation is stopped (timing T3).

On the other hand, from the shift register 12, FIG.
As shown in (d), the sampling pulses SP (1) to
SP (i) is sequentially supplied, and the switch 21 of each sampling circuit is turned on when the corresponding sampling pulse SP (N) becomes a high level. While the switch 21 is on, the first system capacitor 31 samples the RGB inversion signal supplied from the inversion amplifier 2.
When the sampling signal SP (N) becomes low level, the switch 21 is also turned off, and the capacitor 31 holds the sampled image signal (timing T4).
That is, the circuit of the first system of the sample / hold group 14 samples and holds the RGB inversion signal (image signal) for one line in the first horizontal scanning period.

Next, at the end of the first horizontal scanning period, FIG.
The output enable signal OE shown in (b) goes low, the switches 25 and 26 are turned off, and the amplifiers 33 and 34 are electrically disconnected from the signal line DL of the LCD 4.

When the second horizontal scanning period starts, FIG.
The clear signal CLR shown in (a) becomes high level, the switch 27 is turned on, and the data line DL of the LCD 4 is precharged.

Further, as shown in FIG. 6C, the switch 23 is turned on because the system selection signal LOE is at a high level, and the operating voltage is supplied to the first system amplifier 33. The operation of amplifying the image signal held in the capacitor 31 during the first horizontal scanning period is started. On the other hand, the switch 24 is turned off, the supply of the operating voltage to the amplifier 34 of the second system is stopped, and the operation is stopped (timing T5).

After that, when the clear signal CLR becomes low level and precharge is completed and the output enable signal OE becomes high level, the switch 25 is turned on and the amplifier 3 is turned on.
The image signal amplified to 3 is output to the signal line DL (timing T6). That is, during the timing T6, each amplifier 33 outputs a total of 1 during the first horizontal scanning period.
The image signal for the line is amplified and output to the signal line DL for one line.

In substantially synchronization with the timing at which the switch 25 is turned on, the scanning driver 3 applies the corresponding gate line G
The gate pulse is applied to the L, TFL in the corresponding row are turned on, it is charged to the corresponding pixel capacitance C _LC.

On the other hand, sampling pulses SP (1) -S
P (i) are sequentially supplied, and the switch 22 of each sampling circuit is turned on only while the corresponding sampling pulse SP (N) is at a high level. When the switch 22 is turned on, the second system capacitor 32 samples the RGB inversion signal supplied from the inversion amplifier 2, and when the switch 22 is turned off, holds the sampled image signal (timing T7). That is, sample /
The second system circuit of the hold group 14 samples and holds RGB inversion signals (image signals) for one line in the second horizontal scanning period.

Next, at the end of the second horizontal scanning period, the output enable signal OE goes low, and the switch 2
5 and 26 are turned off, and the amplifiers 33 and 34 are electrically disconnected from the signal line DL of the LCD 4.

When the third horizontal scanning period starts, the clear signal CLR becomes high level, the switch 27 turns on,
The data line DL is precharged.

Further, since the system selection signal LOE becomes low level, the switch 23 is turned off, the supply of the operating voltage to the amplifier 33 of the first system is stopped, and the operation is stopped. On the other hand, the switch 24 is turned on, an operating voltage is supplied to the amplifier 34 of the second system, and the amplification operation of the image signal held in the capacitor 32 during the second horizontal scanning period is started. The supply of operating voltage stops,
Stop operation.

Thereafter, when the precharge is completed, the output enable signal OE goes high, and the switch 26
Turns on, the image signal amplified by the amplifier 34 is output to the signal line DL, and the scanning driver 3 applies a gate pulse to the corresponding gate line GL.

On the other hand, sampling pulses SP (1) -S
When P (i) is sequentially supplied and the switch 21 is turned on, the capacitor 31 of the first system samples the RGB inverted signal supplied from the inverting amplifier 2, and when the switch 21 is turned off, the sampled image signal is output. Holding. That is, the circuit of the first system of the sample / hold group 14 has one line of R for the third horizontal scanning period.
The GB inverted signal (image signal) is sampled and held.

By repeating such an operation, L
CD4 image signal is sequentially written to each pixel capacitance C _LC of
Thereby, an image defined by the video signal is displayed. In addition, since the signal driver 5 operates by supplying the power supply voltage only to the amplifier of the system in which the image signal is held, the power consumption of the amplifier 15 can be suppressed.

In the above embodiment, the two systems of the amplifiers are operated alternately by controlling the supply of the operating power supply voltage. However, the supply of the operating current to the amplifiers is controlled and the two systems of the amplifiers are controlled. May be operated. For example,
As shown in FIG. 7, the first system amplifier 33 is connected to the bias circuit 16 via the switch 23, and the second system amplifier 34 is connected to the bias circuit 1 via the switch 24.
6 and switches 23 and 24 are connected to the system selection signal LOE.
And turning them on alternately, the amplifier 33,
34 may be operated alternately.

In the above-described embodiment, in the driver circuit for one signal line, the capacitors 31 and 32 are connected to the ground (VSS) of the logic circuit system. However, as shown in FIG. The configuration may be such that 31, 31 are connected to a power supply line (VDD) of a logic circuit system.

In the above embodiment, in the driver circuit for one signal line, the switch 27 is connected to the power line (VDDC) for precharging, and the signal line D
Although L was precharged, as shown in FIG. 7, the switch 27 was connected to a precharge ground (VSS),
The signal line DL may be discharged.

In the above embodiment, only one of the amplifiers 33 and 34 is turned on alternately. However, the amplifiers 33 and 34 may be turned on simultaneously for a short time. Although two lines of sample-hold circuits and amplifiers were arranged, three or more lines of sample-hold circuits and amplifiers were arranged so that the sample-hold operation and the amplification / output operation were performed in order while switching the systems. You may.

In the above embodiment, the signal driver 5
Has driven the LCD 4 in accordance with a horizontal control signal including a basic clock signal MCLK, a data line start signal SRT, a system selection signal LOE, a clear signal CLR, and an output enable signal OE supplied from the LCD controller 7. It is not limited to these signals. For example, instead of the basic clock signal MCLK, the signal driver 5 operates according to the dot clock signal DCK or the like.
D4 may be driven. The timing of the change of the high level / low level of each horizontal control signal is also arbitrary.

In the above embodiment, the display device to be driven is a TFT type LCD, but the display device driven by the display drive device (signal driver) of the present invention is arbitrary.
LCD using MIM may be used. In addition to the active matrix type LCD, a simple matrix type LC
It can also be used to drive D. The display device to be driven is not limited to the LCD, but may be a matrix-type plasma display, FLC, or the like, and may be used for various devices having two systems of drivers.

[0069]

As described above, the display driving device has:
An image can be displayed on a display device with appropriately reduced power consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a display driving device (signal driver) according to an embodiment of the present invention and its peripheral circuits.

FIG. 2 is a block diagram illustrating a configuration of a display driving device (signal driver) according to the embodiment of the present invention;

FIG. 3 is a timing chart showing a generation timing of a sampling pulse SP generated by a shift register 12.

FIG. 4 is a circuit diagram showing a driver circuit for one signal line according to the embodiment of the present invention;

FIG. 5 is a logic diagram showing timings when switches 21 to 27 shown in FIG. 4 are turned on.

FIG. 6 is a diagram showing a system selection signal L according to the embodiment of the present invention;
5 is a timing chart showing states of an OE, a clear signal CLR, an output enable signal OE, and a sampling pulse SP.

FIG. 7 is a circuit diagram showing a driver circuit for one signal line according to a modification of the embodiment of the present invention.

FIG. 8 is a circuit diagram showing a conventional driver circuit for one signal line.

[Explanation of symbols]

1 ... RGB decoder, 2 ... inverting amplifier, 3 ... scan driver, 4 ... LCD, 5 ... signal driver, 6 ... amplifier, 7 ... LCD controller, 11 ... CK generation / delay circuit, 12 shift register, 13 level shifter,
14: sample / hold group, 15: amplifier group, 16
... Bias circuit, 21-27 ... Switch, 31, 32
... capacitors, 33, 34 ... amplifiers, 101 to 105
... Switch, 111, 112 ... Capacitor, 121,
122 ··· Amplifier

Claims (7)

[Claims] 1. An image signal input means for inputting an image signal, and n (n is a natural number of 2 or more) sample-and-hold circuits, wherein the image signal input by the image signal input means is predetermined for each system. Sample-and-hold means for sampling and holding in accordance with the order given, and n-system amplifiers corresponding to the n-system sample-and-hold circuits on a one-to-one basis, and an amplified output for amplifying and outputting an image signal held by the sample-and-hold means. And a means for operating the amplifier corresponding to only a sample-and-hold circuit of a system holding an image signal. Display driving device. 2. The apparatus according to claim 1, wherein said amplification output means operates by supplying an operating voltage only to said amplifier corresponding to a sample and hold circuit of a system holding an image signal. Display drive. 3. The display according to claim 1, wherein the amplification output means operates by supplying current only to the amplifier corresponding to a sample-hold circuit of a system holding an image signal. Drive. 4. An image signal input means for inputting an image signal; and n (n is a natural number of 2 or more) sample-and-hold circuits, wherein the image signal input by the image signal input means is predetermined for each system. Sample-and-hold means for sampling and holding in accordance with the order given, and n-system amplifiers corresponding to the n-system sample-and-hold circuits on a one-to-one basis, and an amplified output for amplifying and outputting an image signal held by the sample-and-hold means. Means, the amplification output means stops the operation of the amplifier at a timing when the sample and hold circuit corresponding to the amplifier is sampling an image signal, At the timing when the sample and hold circuit is holding the image signal Operating the amplifier, a display driving apparatus, characterized in that. 5. The amplification and output means stops supply of an operating voltage to the amplifier at a timing when the sample and hold circuit corresponding to the amplifier is sampling an image signal, and outputs the corresponding sample and hold circuit. 5. The display driving device according to claim 4, wherein an operation voltage is supplied to the amplifier at a timing when the image signal is held. 6. 6. The amplification output means stops supply of current to the amplifier at a timing when the sample and hold circuit corresponding to the amplifier samples an image signal, and the corresponding sample and hold circuit outputs the image signal. The display driving device according to claim 4, wherein a current is supplied to the amplifier at a timing when holding is performed. 7. An image signal inputting step of inputting an image signal, and the image signal input in the image signal inputting step is represented by n
(N is a natural number of 2 or more) sample-and-hold steps of sampling and holding using a system of sample-and-hold circuits in a system-unit predetermined order, and n corresponding to the n-system sample-and-hold circuits on a one-to-one basis. An amplification output step of amplifying and outputting the image signal held by the sample-and-hold step using a system amplifier, and a driving method of the display device, wherein the amplification output step includes: A method of driving a display device, comprising substantially operating only the amplifier corresponding to a held system sample-hold circuit.