JP2006113143A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device with which levels of the voltages used in the circuits are reduced, the circuits are simplified and the size, power consumption and heat to be generated by the panel are reduced. <P>SOLUTION: Low power consumption can be achieved by making shift registers 231 be the same power supply condition of input signals in a horizontal scanner 23. When the input signals are received, pulses are transferred by the shift registers while the voltage levels of the pulses are made equal to the voltage levels of the input signals. In spite of the low voltages used in the circuits, pulse resistance to noise can be achieved by making a channel length L of the transistors to be shorter than the blocks used in the power supply of V2 in a level shifter group 233 and a sampling switch group 234 so as to realize normal operations. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a display device and a driving method thereof, and more particularly, to an active matrix display device of a dot sequential driving method employing a so-called clock drive method.

  In a display device, for example, an active matrix type liquid crystal display device using a liquid crystal cell as a pixel display element (electro-optical element), a dot sequential driving method is adopted for a horizontal driving circuit (horizontal scanner unit).

  FIG. 1 is a circuit diagram showing a configuration of an active matrix liquid crystal display device adopting a general dot sequential driving method (see, for example, Patent Document 1).

As shown in FIG. 1, the liquid crystal display device (LCD panel) 10 includes an effective pixel portion (PXLP) 11, vertical drive circuits (vertical scanner: VSCN) 12, 13, horizontal scanner (HSCN) 14, and signal lines. A precharge circuit (PRCG) 15 is included as a main component.
A clock generation circuit 16 is arranged outside the LCD panel 10.

The pixel unit 11 includes a plurality of pixels PXL arranged in a matrix of n rows and m columns. Here, in order to simplify the drawing, a case of a pixel array of 4 rows and 4 columns is shown as an example.
Each of the pixels PXL arranged in a matrix includes a thin film transistor (TFT) that is a pixel transistor, a liquid crystal cell in which the pixel electrode is connected to the drain electrode of the TFT, and one electrode on the drain electrode of the TFT. And a storage capacitor connected thereto.
For each of these pixels PXL, signal lines SGNL1 to SGNLn are wired along the pixel arrangement direction for each column, and gate lines GTL1 to GTLm are wired along the pixel arrangement direction for each row.
In each pixel PXL, the source electrode (or drain electrode) of the TFT is connected to the corresponding signal line SGNL1 to SGNLn. The gate electrodes of the TFTs are connected to the gate lines GTL1 to GTLm, respectively. The counter electrode of the liquid crystal cell and the other electrode of the storage capacitor are connected to the Cs line in common between the pixels. A predetermined DC voltage is applied as a common voltage Vcom to the Cs line.
In the pixel unit 11, one end of each of the gate lines GTL <b> 1 to GTLm is connected to an output end of each row of the vertical scanners 12 and 13 disposed on the left side of the pixel unit 11 in the drawing, for example.

The vertical scanner 12 (13) performs a process of sequentially selecting each pixel PXL connected to the gate lines GTL1 to GTLm by scanning in the vertical direction (row direction) every 1H (H is a horizontal scanning period). .
That is, when the scanning pulse SP1 is applied from the vertical scanner 12 to the gate line GTL1, the pixels in each column of the first row are selected, and when the scanning pulse SP2 is applied to the gate line GTL2, the second row. A pixel in each column is selected. Similarly, scanning pulses SP3 to SPm are sequentially applied to the gate lines GTL3 to GTLm.

For example, a horizontal scanner 14 is disposed above the pixel unit 11 in the drawing.
The horizontal scanner 14 sequentially samples the input video signal VDO1 in units of units in synchronization with the clock HCK, and performs processing of writing to each pixel PXL selected in units of rows by the vertical scanner 12.

  As shown in FIG. 2, the horizontal scanner 14 employs a clock drive system, and includes level shifters 141-1 to 141-5, clock buffers 142-1 to 142-5, a shift register group 143, and a clock extraction switch group 144. And a sampling switch group 145.

  The level shifters 141-1 to 141-5 are, for example, a 3.3V or 5V level horizontal start pulse HST generated by the external clock generation circuit 16, horizontal clocks HCK and HCKX having opposite phases, and a phase having the same period. Second clocks DCK and DCKX having different levels are shifted to about 13V to 15V, and horizontal start pulses HST of 13V to 15V level and horizontal clocks HCK and HCKX having opposite phases are shifted through clock buffers 142-1 to 142-3. The voltage is supplied to the register group 143 and the second clocks DCK and DCKX having a level of 13V to 15V are propagated to the supply lines DKL1 and DKXL1.

  The shift register group 143 includes n shift stages (S / R stages) 143-1 to 143-n corresponding to the pixel columns (n columns in this example) of the pixel unit 11, and the horizontal level after the level shift. When the start pulse HST is given, a shift operation is performed in synchronization with the horizontal clocks HCK and HCKX having opposite phases. Thus, shift pulses SFTP1 to SFTPn having the same pulse width as the cycles of the horizontal clocks HCK and HCKX are sequentially output from the shift stages 143-1 to 143-n of the shift register group 143.

The clock extraction switch group 144 includes n switches 144-1 to 144-n corresponding to the pixel columns of the pixel unit 11, and one end of each of the switches 144-1 to 144-n is a level-shifted first switch. The clock lines DKXL1 and DKL1 that transmit the two clocks DCKX and DCK are alternately connected.
Shift pulses SFTP1 to SFTPn sequentially output from the shift stages 143-1 to 143-n of the shift register group 143 are applied to the switches 144-1 to 144-n of the clock extraction switch group 144, respectively.
When the shift pulses SFTP1 to SFTPn are given from the shift stages 143-1 to 143-n of the shift register group 143, the switches 144-1 to 144-n of the clock extraction switch group 144 are supplied to the shift pulses SFTP1 to SFTPn, respectively. By sequentially turning on in response, the second clocks DCK and DCKX having the same cycle and different phases are alternately extracted.

The sampling switch group 145 includes four sampling switches 145-1 to 145-n corresponding to the pixel columns of the pixel unit 11, and one end of each of the sampling switches 145-1 to 145-n receives the video signal VDO. It is connected to the input video line VDL1. By the way, in the image display device of the dot sequential drive method, when the video signal VDO is input in one system, when the number of pixels in the horizontal direction increases especially with the increase in definition, all the pixels are limited within a limited scanning period. It becomes difficult to secure a sufficient sampling time for sampling in order.
Therefore, in order to ensure a sufficient sampling time per pixel, video signals are input in parallel in M systems (M is an integer of 2 or more), while M samplings corresponding to M pixels in the horizontal direction are input. An M-phase driving method is employed in which writing is performed sequentially in units of M pixels by simultaneously driving M sampling switches in one unit with one sampling pulse in units of switches.
Here, the system of the video signal is not particularly limited, and generally there are 6 systems, 12 systems, and the like, which are determined according to the resolution and the scanning speed.
The sampling switches 145-1 to 145-n are supplied with the clocks DCK and DCKX extracted by the switches 144-1 to 144-n of the clock extraction switch group 144 as sample hold pulses SHP1 to SHPn.
The sampling switches 145-1 to 145-n of the sampling switch group 145 are sequentially turned on in response to the sample hold pulses SHP1 to SHPn when the sample hold pulses SHP1 to SHPn are given, so that the video line VDL1 The video signal VDO1 of M systems (for example, 6 or 12 systems) input through is sampled and supplied to the signal lines SGNL1 to SGNLn of the pixel unit 11.

The clock generation circuit 16 also includes a vertical start pulse VST for instructing the start of vertical scanning, vertical clocks VCK and VCKX having opposite phases as a reference for vertical scanning, a horizontal start pulse HST for instructing the start of horizontal scanning, and horizontal scanning. The horizontal clocks HCK and HCKX having opposite phases to each other are generated, the vertical start pulse VST and the vertical clocks VCK and VCKX are supplied to the vertical scanners 12 and 13, and the horizontal clocks HCK and HCKX are supplied to the horizontal scanner 14. .
Further, the clock generation circuit 16 generates second clocks DCK and DCKX based on the generated horizontal clocks (first clocks) HCK and HCKX, and supplies the second clocks DCK and DCKX to the horizontal scanner 14. The clock generation circuit 16 includes a scanning direction switching clock (not shown), a left / right inversion control signal RGT, a vertical inversion control signal DWN, and the like. These also include level shifters and buffers as well as signals such as HCK and HST.

In the horizontal scanner 13 described above, as shown in FIGS. 3A to 3E, for example, a horizontal start pulse HST of 3.3V or 5V level generated by an external clock generation circuit 16 and a horizontal clock having phases opposite to each other. HCK and HCKX and the second clocks DCK and DCKX are level-shifted to about 13V to 15V as shown in FIGS.
Instead of using the shift pulses SFTP1 to SFTPn sequentially output from the shift register group 143 as sample hold pulses, the second clocks DCXK and DCK are alternately extracted in synchronization with the shift pulses SFTP1 to SFTPn. DCK and DCKX are used as sample and hold pulses SHP1 to SHPn as shown in FIGS. Thereby, the dispersion | variation in the sample hold pulses SHP1 to SHPn can be suppressed. As a result, ghosts caused by variations in the sample hold pulses SHP1 to SHPn can be removed.
JP 2002-72987 A

By the way, a recent active matrix type liquid crystal display device is represented by a low-temperature polysilicon liquid crystal as well as switching a liquid crystal by forming a thin film element such as a TFT in a pixel by progress of design technology and process technology. As described above, the circuit for driving the liquid crystal is integrated in the peripheral portion of the pixel, and the cost reduction is achieved by making the drive circuit monolithic.
In addition, these liquid crystal display devices have begun to be mounted on mobile phones and mobile terminals due to miniaturization and high definition, and there is a demand for further lower power consumption of the panel.
In addition, due to higher integration and higher resolution of transistors formed in the panel due to higher definition and higher resolution, an increase in transistor size and an increase in driving frequency, the problem of heat generated in the panel cannot be ignored.

However, in the conventional circuit configuration, the threshold voltage of the liquid crystal is as high as ± 5 V, so that a voltage of 10 V or more is required for the drive circuit, and this voltage is used as a power source in the drive circuit. In addition, the characteristics of the thin film transistor may be poor, and it is necessary to absorb variations in the characteristics of the transistor due to a high voltage.
Therefore, in the conventional apparatus, the voltage of the signal input into the panel is a low voltage such as 3.3 V or 5 V, for example, but the level of these input signals is shifted to the high voltage described above.
Further, in the conventional circuit configuration, as the panel becomes higher in definition and resolution, a load such as parasitic capacitance and wiring resistance in the panel becomes larger, and thus a huge buffer is required after the level shift.
For this reason, a large current flows through the buffer, and the power consumption greatly increases as the drive frequency increases. At the same time, there is a high demand for display quality, and there is a panel that realizes a circuit configuration with more variations by increasing the number of input terminals so as not to cause image quality defects due to variations in signals within the drive circuit.
In addition, in the conventional circuit, a voltage of 10 V or more is required only for a driving circuit that applies a video signal to the liquid crystal, and other driving circuit parts such as transfer pulses can be driven at a low voltage. First, as described above, all external clocks are boosted.
Naturally, as the number of terminals increases, the number of transistors increases, and as the size increases, power consumption and heat increase. High-definition, high-resolution, and improved display quality required for panels, the generation of power consumption and heat is serious due to higher integration of the panels, increase in the number of transistors, increase in size, and drive speed. It is becoming.

  An object of the present invention is to provide a display device that can reduce the voltage of a circuit, simplify the circuit, and reduce the size, reduce power consumption, and reduce heat generated in a panel. .

  In order to achieve the above object, a display device according to an aspect of the present invention drives a pixel portion in which a plurality of pixels are arranged in a matrix and a drive line is wired for each pixel column or row, and the pixel portion. A shift circuit that sequentially outputs shift pulses from each shift stage in synchronization with a clock signal serving as a reference for scanning at the first power supply level, and a shift pulse generated by the shift register. And a level shifter group that generates a signal of a second power supply level higher than the first power supply level, and drives each corresponding drive line of the pixel portion based on the signal after the level shift.

  Preferably, the drive line includes a signal line wired for each pixel column, the drive circuit includes a horizontal scan, and the horizontal scanner is a reference for the horizontal scan of the first power supply level. A shift register that sequentially outputs a shift pulse from each shift stage in synchronization with a reverse-phase clock signal and an inverted clock signal, and the clock signal and the clock signal in response to the shift pulse output from the corresponding shift stage of the shift register A first switch group that alternately extracts inverted clock signals and outputs them as sample hold pulses, and a sample hold pulse generated by the first switch group is level-shifted to a second power supply level that is higher than the first power supply level. Level shifter group and the video signal in response to the sample hold pulse by the level shifter group Sampled and including, a second switch group supplies to the corresponding signal lines of the pixel portion.

  Preferably, the horizontal scanner is supplied with two second clock signals having the same period and different phases based on the clock signal and the inverted clock signal, and each of the first switch groups of the horizontal scanner is provided. The switch extracts one of the two second clock signals, and the level shifter group shifts the level of the extracted second clock signal.

  Preferably, the drive line includes a gate line wired for each pixel row, the drive circuit includes a vertical scan, and the vertical scanner transmits a shift pulse of the shift register to the first power supply level. The level is shifted to a higher second power supply level, and the level-shifted signal is sequentially output to the corresponding gate lines of the pixel portion.

  Preferably, the drive line includes a signal line wired for each pixel column, the drive circuit includes a precharge circuit, and the precharge circuit responds to a pulse from the level shifter group with a precharge signal. A switch group that sequentially samples and supplies the signal lines to the corresponding signal lines of the pixel portion.

  Preferably, the shift register is driven under substantially the same power supply condition as the input clock.

  Preferably, the shift register includes a transistor having a first channel length, the level shifter group includes a transistor having a second channel length, and the first channel length is set to be shorter than the second channel length. Yes.

  Preferably, the shift register includes a first channel length transistor, the level shifter group and the second switch group include a second channel length transistor, and the first channel length is the second channel length. It is set shorter than the length.

  Preferably, the display element of the pixel is a liquid crystal cell.

According to the present invention, for example, an external circuit generates a clock signal and an inverted clock signal which are opposite in phase to each other as a reference for horizontal scanning, and supplies them to a horizontal scanner.
In the horizontal scanner, a horizontal start pulse is supplied to the first shift stage in the shift register group.
In the horizontal scanner, a shift pulse is sequentially output from each shift stage to each corresponding switch of the first switch group in synchronization with the clock signal and the inverted clock signal.
In the first switch group, the clock signal and the inverted clock signal are alternately extracted sequentially in response to the shift pulse output from the corresponding shift stage. The extracted signal is level-shifted (boosted) and output as a sample-and-hold pulse to each corresponding switch in the second switch group.
In the second switch group, the input video signals are sequentially sampled in response to sample and hold pulses by the respective switches of the first switch group, and are supplied to the corresponding signal lines of the pixel portion.

  According to the present invention, it is possible to drive at a low voltage with respect to an input signal of a clock or a control signal, and to provide a level shifter individually in a circuit unit to be driven, and a huge buffer is not required, so only power consumption is reduced. It is possible to reduce the generation of heat. These low-voltage drives, reduction of level shifters, and downsizing of huge buffers are effective in each driver circuit block such as horizontal scan drive circuit, vertical scan drive circuit, precharge drive circuit, etc. Reduction of heat generation and heat generation.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 4 is a circuit diagram showing a configuration example of a dot sequential drive type active matrix liquid crystal display device according to an embodiment of the present invention using, for example, a liquid crystal cell as a pixel display element (electro-optic element).

As shown in FIG. 4, the liquid crystal display device 20 includes an effective pixel portion (PXLP) 21, a vertical scanner (VSCN) 22, a horizontal scanner (HSCN) 23, and a clock generation circuit (GEN) 24 as main components. is doing.
As shown in FIG. 5, the vertical scanner may be arranged not only on one side (left side in the figure) of the pixel unit 21 but also on both sides (left side and right side in the figure). In addition, a signal line precharge circuit (PRCG) 25 is provided.
The effective pixel portion (PXLP) 21, vertical scanner (VSCN) 22 (22-1 and 22-2), horizontal scanner (HSCN) 23, and precharge circuit 25 are provided on the display panel (LCD panel, TFT substrate) 30. Implemented.

In the pixel unit 21, a plurality of pixels PXL are arranged in a matrix of n rows and m columns. Here, in order to simplify the drawing, a case of a pixel array of 4 rows and 4 columns is shown as an example.
Each of the pixels PXL arranged in a matrix form a thin film transistor (TFT) 21 that is a pixel transistor, a liquid crystal cell LC 21 having a pixel electrode connected to the drain electrode of the TFT 21, and a drain electrode of the TFT 21. And a storage capacitor Cs 21 to which the electrodes are connected.
For each of these pixels PXL, signal lines SGNL21 to SGNL24 are wired along the pixel arrangement direction for each column, and gate lines GTL21 to GTL24 are wired along the pixel arrangement direction for each row.
In each pixel PXL, the source electrode (or drain electrode) of the TFT 21 is connected to the corresponding signal lines SGNL21 to SGNL24. The gate electrode of the TFT 21 is connected to each of the gate lines GTL21 to GTL24. The counter electrode of the liquid crystal cell LC21 and the other electrode of the storage capacitor Cs21 are connected to the Cs line CsL21 in common among the pixels. A predetermined DC voltage is applied as a common voltage Vcom to the Cs line Cs L21.
In the pixel unit 21, one end of each of the gate lines GTL <b> 21 to GTL <b> 24 is connected to the output end of each row of the vertical scanner 22 disposed on the left side of the pixel unit 21 in the drawing, for example.

The vertical scanner 22 performs a process of scanning in the vertical direction (row direction) every 1H period and sequentially selecting each pixel PXL connected to the gate lines GTL21 to GTL24 in units of rows.
That is, when the scanning pulse SP21 is applied from the vertical scanner 22 to the gate line GTL21, the pixel PXL in each column of the first row is selected, and when the scanning pulse SP22 is applied to the gate line GTL22, the second row. The pixels PXL in each column are selected. Similarly, scanning pulses SP23 and SP24 are sequentially applied to the gate lines GTL23 and GTL24.

  For example, a horizontal scanner 23 is disposed above the pixel unit 21 in the drawing.

The horizontal scanner 23 sequentially samples the input video signal VDO1 in units of units in synchronization with the clock HCK, and performs a process of writing to each pixel PXL selected in units of rows by the vertical scanner 22.
As shown in FIG. 4, the horizontal scanner 23 employs a clock drive method, and includes a shift register 231, a clock extraction switch group 232, a level shifter group 233, and a sampling switch group 234.

The shift register 231 includes four shift stages (S / R stages) 231-1 to 231-4 corresponding to the pixel columns (four columns in this example) of the pixel unit 21, for example, an external clock generation circuit When the horizontal start pulse HST is applied to the first (first stage) shift stage 231-1 (or the fourth (final) shift stage 231-4) by 24, for example, the horizontal clock HCK and the inverted horizontal clock HCKX (hereinafter referred to as opposite phases) Both of them perform a shift operation in synchronization with a horizontal clock).
Thus, shift pulses SFTP231 to SFTP234 having the same pulse width as the cycles of the horizontal clocks HCK and HCKX are sequentially output from the shift stages 231-1 to 231-4 of the shift register 231.

The clock extraction switch group 232 includes four switches 232-1 to 232-4 corresponding to the pixel columns of the pixel unit 21, and one end of each of the switches 232-1 to 232-4 is formed by the clock generation circuit 25. The second clocks DCK21 and DKXL21 are alternately connected to the clock lines DKL21 and DKXL21 that transmit the second clock DCKX having the same cycle and the same phase as the second clock DCK.
That is, one end of each of the switches 232-1 and 232-3 corresponding to the odd columns of the pixel columns of the pixel unit 21 is connected to the clock line DKXL21, and the switches 232-2 and 232 corresponding to the even columns of the pixel columns of the pixel unit 21 are connected. Each end of 4 is connected to the clock line DKL21.
Shift pulses SFTP231 to SFTP234 that are sequentially output from the shift stages 231-1 to 231-4 of the shift register 231 are applied to the switches 232-1 to 232-4 of the clock extraction switch group 232, respectively.
The switches 232-1 to 232-4 of the clock extraction switch group 232 respond to the shift pulses SFT23P1 to SFTP234 when the shift pulses SFTP231 to SFTP234 are given from the shift stages 231-1 to 231-4 of the shift register 231. Then, the clocks DCKX and DCK are alternately extracted by sequentially turning on.

  The level shifter group 233 includes four level shifters (LS) 233-1 to 233-4 corresponding to the pixel columns of the pixel unit 21, and each level shifter 233-1 to 233-4 has each switch of the clock extraction switch group 232. The voltage levels of the clocks DCKX and DCK extracted at 232-1 to 232-4 are level-shifted (boosted) from the 3-7V level to the HVDD level of about 10V to 12V, for example, and then the corresponding sampling switch group 234 Supply to sampling switch.

  FIG. 6 is a circuit diagram illustrating a specific configuration example of the level shifter 233 (−1 to −4).

The level shifter 233 in FIG. 6 includes p-channel MOS (PMOS) transistors PT21 to PT24, n-channel MOS (NMOS) transistors NT21 and NT22, and an inverter INV21.
The sources of the PMOS transistors PT21 and PT22 are connected to the boosting power supply HVDD (for example, 10V to 12V), and the sources of the NMOS transistors NT21 and NT22 are connected to the ground potential GND (0V).
The drain of the PMOS transistor PT21 is connected to the source of the PMOS transistor PT23, and the drain of the PMOS transistor PT22 is connected to the source of the PMOS transistor PT24.
The drain of the PMOS transistor PT23 is connected to the drain of the NMOS transistor NT21, and a node ND21 is configured by the connection point. Further, the drain of the PMOS transistor PT24 is connected to the drain of the NMOS transistor NT22, and an output node ND22 is configured by the connection point.
The gate of the PMOS transistor PT21 is connected to the output node ND22, and the gate of the PMOS transistor PT22 is connected to the node ND21.
The gate of the PMOS transistor PT23 and the gate of the NMOS transistor NT21 are connected to the clock input line of the clock DCK or DCKX extracted by the switches 232-1 to 232-4 of the clock extraction switch group 232.
The gate of the PMOS transistor PT24 and the gate of the NMOS transistor NT22 are connected to the clock input line of the clock DCK or DCKX extracted by the switches 232-1 to 232-4 of the clock extraction switch group 232 via the inverter INV21. .

In this level shifter 233, when a high level (for example, 7V) clock is input, the PMOS transistor PT23 is turned off and the NMOS transistor NT21 is turned on. The level of the clock is inverted by the inverter INV21 and the PMOS transistor PT24 is turned on. In this state, the NMOS transistor NT22 is turned off.
As the NMOS transistor NT21 is turned on, the node ND21 changes to the ground potential level. As a result, the PMOS transistor PT22 is turned on. Since the PMOS transistors PT21 and PT24 are in the on state and the NMOS transistor NT22 is in the off state, the output node ND22 is charged from the boosting power supply HVDD, and the input level 7V is 10V as shown in FIG. The voltage is boosted to an HVDD level of ˜12 V and supplied to the next stage.
As the output node ND22 is boosted to the HVDD level, the PMOS transistor PT21 is stably held in the off state.

In this level shifter 233, when a low level (for example, 0V) clock is input, the PMOS transistor PT23 is turned on, the NMOS transistor NT21 is turned off, and the level of the clock is inverted by the inverter INV21 so that the PMOS transistor PT24 is turned off. In this state, the NMOS transistor NT22 is turned on.
As NMOS transistor NT22 is turned on, output node ND22 transitions to the ground potential level. As a result, the PMOS transistor PT21 is switched on, and as shown in FIG. 7, the input level 0V remains at the 0V level and is supplied to the next stage.
As the output node ND21 is at the ground potential level, the PMOS transistor PT21 is stably held in the ON state, and as a result, the node ND21 is charged with electric power from the boosting power supply HVDD. As the output node ND21 is boosted to the HVDD level, the PMOS transistor PT22 is stably held in the off state.

The sampling switch group 234 includes four sampling switches 234-1 to 234-4 corresponding to the pixel columns of the pixel unit 21, and one end of each of these sampling switches 234-1 to 234-4 is an image from the outside. It is connected to a video line VDL21 for inputting the signal VDO1.
In this embodiment, in order to ensure a sufficient sampling time per pixel, video signals are input in parallel in M systems (M is an integer of 2 or more, for example, 6 systems), while M signals in the horizontal direction are input. The M-phase drive method is adopted in which M sampling switches corresponding to each pixel are used as a unit, and M sampling switches in one unit are driven simultaneously by one sampling pulse, thereby sequentially writing in units of M pixels. is doing.
The sampling switches 234-1 to 234-4 receive the clocks DCKX and DCK extracted by the switches 232-1 to 232-4 of the clock extraction switch group 232 and level-shifted by the level shifter group 233. Provided as SHP234.
When the sample hold pulses SHP231 to SHP234 are given, the sampling switches 234-1 to 234-4 of the sampling switch group 234 are sequentially turned on in response to the sample hold pulses SHP231 to SHP234, whereby the video line VDL21. The M system video signals VDO1 input through are sampled sequentially and supplied to the signal lines SGNL21 to SGNL24 of the pixel unit 21.

The clock generation circuit 24 has a vertical start pulse VST for instructing the start of vertical scanning, vertical clocks VCK and VCKX having opposite phases as a reference for vertical scanning, a vertical start pulse VST for instructing the start of horizontal scanning, and a reference for horizontal scanning. The horizontal clocks HCK and HCKX having opposite phases to each other are generated, the vertical start pulse VST and the vertical clocks VCK and VCKX are supplied to the vertical scanner 22, and the horizontal clocks HCK and HCKX are supplied to the horizontal scanner 23.
The clock generation circuit 24 generates a horizontal start pulse HST and supplies it to the first shift stage 231-1 of the shift register 231 of the horizontal scanner 23.
The clock generation circuit 24 generates second clocks DCK and DCKX having the same period (T1 = T2) and different phases based on the generated horizontal clocks (first clocks) HCK and HCKX, and a clock line DKL21. , DKXL21 to supply to the horizontal scanner 23.

As described above, in this embodiment, the main power supply conditions used in the drive circuit, for example, the horizontal scanner 23 are the following conditions. V = V1 V1 <V2. This indicates that the voltage of the input signal is equal to the power source used in the shift register. Specifically, 3.3V or 5.0V is used as the input signal. Of course, an input signal having a higher voltage may be used.
That is, the power consumption is reduced by setting the shift register 231 to the same power supply condition as that of the input signal. A pulse is transferred by a shift register in response to an input signal, and the voltage of the pulse is equal to the voltage of the input signal.
In the present embodiment, in order to prevent pulse noise due to low voltage and to realize normal operation, the channel length L of the transistor is made smaller than the block used by the power source of V2 in the level shifter group 233 and the sampling switch group 234. Resolve.
Of course, it is necessary to obtain an optimum channel width W of the transistor. In general, the transistor capacity is a factor that can be controlled on the design side. The transistor size is determined by W / L which is a size ratio. However, in order to stabilize transistor characteristics, the channel length L is rarely changed for each transistor, and the channel length L is generally fixed and the channel width W is changed. However, when the driving voltage is reduced, the driving current tends not to increase no matter how much the W of the transistor is increased, and when the channel width W is increased unnecessarily, the layout area also increases. Therefore, the effect of the short channel length L is great for driving at a low voltage.

In this embodiment, in the block (shift register 231 and extraction switch group 232) used under the power supply condition of V1, a transistor having a first channel length L shorter than that of the block of the power supply condition of V2 is used. Realizes voltage drive.
When the channel length L is shortened, the withstand voltage of the transistor becomes a problem. However, since the voltage of the transistor used under the power supply condition of V1 is low, the withstand voltage problem is avoided. However, as the channel length L becomes shorter, it is a fact that the variation of the transistors becomes larger, but due to the recent improvement in process technology, the variation is reduced and the length L can be shortened.
Further, since the pulse generated by the shift register 231 is a transfer pulse, and this pulse is not a pulse for sampling the video signal, a certain degree of variation can be allowed. As the power supply condition, V = V1 is desirable, but the condition of V <V1 with a margin for driving is more stable, so the condition of V <V1 may be used.

As described above, in this embodiment, the shift register 231 is driven at a low voltage. However, the power supply condition after this requires a voltage equal to or higher than the threshold voltage of the liquid crystal. If the threshold voltage of the liquid crystal is ± 5V, the driving voltage needs to be at least 10V. Of course, the threshold voltage varies depending on the liquid crystal material, but the voltage is higher than the voltage used in the shift register 231 and the like, so a voltage level shift is necessary. Here, the level of the sampling pulse is shifted from V1 to V2 (HVDD).
In general, V1 <V2. The level-shifted sampling pulse samples, for example, a buffer block and a sampling block, samples a video signal, and sends it to a pixel TFT. In the present embodiment, the drive voltage is changed by the transfer block and sampling, so that the voltage can be lowered and the generation of heat can be reduced.

As described above, in this embodiment, the level shift of each input terminal is not necessary. Pulse transfer is performed with the voltage of the input signal. In addition, a signal having a sufficiently high driving capability can be obtained by the output buffer from the IC and LSI outside the panel load as well as the low voltage with respect to the delay of each input signal.
For example, since terminals such as DCK were conventionally driven by a collective level shifter and buffer, a huge buffer was required. However, in the circuit configuration of this embodiment, a level shifter is provided at each stage after the shift register 231. Therefore, since only the load after that stage is applied to each level shifter, the load is much lower than in the case of the conventional batch, and it is possible to design a small size, which also reduces power consumption and generates heat. Contributes to reduction.

  Next, the normal scan operation with the above configuration will be described with reference to the timing charts of FIGS.

In the clock generation circuit 24, a horizontal start pulse HST as shown in FIG. 8A is generated and supplied to the first shift stage 231-1 of the shift register 231 in the horizontal scanner 23.
Also, in the clock generation circuit 24, horizontal clocks HCK and HCKX having opposite phases are generated as shown in FIGS. 8B and 8C, and the first shift stage 231 of the shift register 231 in the horizontal scanner 23 is generated. -1 to the fourth shift stage 231-4.
Further, in the clock generation circuit 24, as shown in FIGS. 8D and 8E, second clocks DCK and DCKX having the same period and different phases are generated based on the generated horizontal clocks HCK and HCKX. And supplied to the horizontal scanner 23 through the clock lines DKL21 and DKXL21.

  In the clock generation circuit 24, a vertical start pulse VST for instructing the start of vertical scanning, vertical clocks VCK and VCKX having opposite phases as a reference for vertical scanning, and a vertical start pulse VST for instructing the start of horizontal scanning are generated. Supplied to the vertical scanner 22.

Then, in the shift register 231 of the horizontal scanner 23, the first shift stage 231-1 to which the horizontal start pulse HST is supplied by the external clock generation circuit 24 is synchronized with the reverse-phase horizontal clocks HCK and HCKX in FIG. As shown in (F), the NA shift pulse SFTP 231 is output to the extraction switch 232-1. Further, the shift pulse SFTP 231 is shifted in from the first shift stage 231-1 to the second shift stage 231-2.
The extraction switch 232-1 corresponding to the first shift stage 231-1 is turned on in response to the shift pulse SFTP231, and the clock DCKX output to the clock line DKXL21 is extracted as shown in FIG. As shown in FIG. 8J, the level shifter 233-1 is level-shifted (boosted) and then supplied to the sampling switch 234-1 as the sample hold pulse SHP231.
As a result, the sampling switch 234-1 is turned on in response to the sample hold pulse SHP231, and as shown in FIG. 8 (L), the M video signals VDO1 input through the video line VDL21 are sampled. The signal is supplied to the signal line SGNL21 of the unit 21.

Next, in the second shift stage 231-2 in which the shift pulse SFTP 231 is shifted in from the first shift stage 231-1, as shown in FIG. 8G in synchronization with the reverse phase horizontal clocks HCK and HCKX. , The shift pulse SFTP232 is output to the extraction switch 232-2. Further, the shift pulse SFTP232 is shifted in from the second shift stage 231-2 to the third shift stage 231-3.
The extraction switch 232-2 corresponding to the second shift stage 231-2 is turned on in response to the shift pulse SFTP232, and the clock DCK output to the clock line DKL21 is extracted as shown in FIG. As shown in FIG. 8K, the level shifter 233-2 level-shifts (boosts) and then supplies the sample-hold pulse SHP232 to the sampling switch 234-2.
As a result, the sampling switch 234-2 is turned on in response to the sample hold pulse SHP232, and as shown in FIG. 8L, the M video signals VDO1 input through the video line VDL21 are sampled, The signal is supplied to the signal line SGNL22 of the unit 21.

Next, in the third shift stage 231-3 in which the shift pulse SFTP232 is shifted in from the second shift stage 231-2, the shift pulse SFTP233 is extracted in synchronization with the reverse phase horizontal clocks HCK and HCKX. Is output. Further, the shift pulse SFTP233 is shifted in from the third shift stage 231-3 to the fourth shift stage 231-4.
The extraction switch 232-3 corresponding to the third shift stage 231-3 is turned on in response to the shift pulse SFTP233, and the clock DCKX output to the clock line DKXL21 is extracted, and the level shifter 233-3 performs level shift (step-up) ) And then supplied to the sampling switch 234-3 as a sample hold pulse SHP233.
As a result, the sampling switch 234-3 is turned on in response to the sample hold pulse SHP233, and the M video signals VDO1 inputted through the video line VDL21 are sampled and supplied to the signal line SGNL23 of the pixel unit 21. .

Next, in the fourth shift stage 231-4 in which the shift pulse SFTP233 is shifted in from the third shift stage 231-3, the shift pulse SFTP234 is extracted in synchronization with the reverse-phase horizontal clocks HCK and HCKX. Is output.
The extraction switch 232-4 corresponding to the fourth shift stage 231-4 is turned on in response to the shift pulse SFTP234, the clock DCK output to the clock line DKL21 is extracted, and the level shifter 233-4 performs level shift (step-up). ) And then supplied to the sampling switch 234-4 as a sample hold pulse SHP234.
As a result, the sampling switch 234-4 is turned on in response to the sample hold pulse SHP234, and the M system video signal VDO1 input through the video line VDL21 is sampled and supplied to the signal line SGNL24 of the pixel unit 21. .

As described above, in the horizontal scanner 23, when the shift pulses SFTP 231 to SFTP 234 are given from the shift stages 231-1 to 231-4 of the shift register 231 by the switches 232-1 to 232-4 of the clock extraction switch group 232. In response to the shift pulses SFTP231 to SFTP234, the clocks DCKX and DCK are alternately extracted, and the clocks DCKX and DCK level-shifted (boosted) by the level shifter are provided as sample hold pulses SHP231 to SHP234. It is done.
When the sample hold pulses SHP231 to SHP234 are given to the sampling switches 234-1 to 234-4 of the sampling switch group 234, the sampling switches 234-1 to 234-4 are turned on in order in response to the sample hold pulses SHP231 to SHP234, and pass through the video line VDL21. The input M video signals VDO1 are sequentially sampled and supplied to the signal lines SGNL21 to SGNL24 of the pixel unit 21.

As described above, according to the present embodiment, in the horizontal scanner 23, the switches 232-1 to 232-4 of the clock sampling switch group 232 are connected to the shift stages 231-1 to 231-4 of the shift register 231. When the shift pulses SFTP231 to SFTP234 are given, they are sequentially turned on in response to the shift pulses SFTP231 to SFTP234, so that clocks DCKX and DCK having opposite phases are alternately extracted, and the level shifter group 233 performs level shift (boost). The obtained clocks DCKX and DCK are supplied to the sampling switches 234-1 to 234-4 of the sampling switch group 234 as sample hold pulses SHP231 to SHP234, and in response to the sample hold pulses SHP231 to SHP234. Since the M video signals VDO1 input through the video line VDL21 are sequentially sampled and supplied to the signal lines SGNL21 to SGNL24 of the pixel unit 21, the panel drive voltage is partially driven at a low voltage. This makes it possible to reduce power consumption.
As a method for realizing this, the channel length L of the transistors in the shift register and the scanning direction switching block is made shorter than that of a high voltage driving circuit unit such as a buffer unit, thereby driving at the same voltage as the input voltage. (Or slightly higher voltage).
This eliminates the need for a level shifter for the clock and control signal input signals, and also eliminates the need for a huge buffer, resulting in the effect of reducing heat generation as well as power consumption.
These low-voltage drives, reduction of level shifters, and downsizing of huge buffers are effective in each driver circuit block such as horizontal scan drive circuit, vertical scan drive circuit, precharge drive circuit, etc. There is an advantage that reduction of heat generation and reduction of heat generation can be obtained.

  The horizontal scanner 23 does not use the shift pulses SFTP231 to SFTP234 sequentially output from the shift register 231 as sample hold pulses, but alternately uses the second clocks DCKX and DCK in synchronization with the shift pulses SFTP231 to SFTP234. These clocks DCKX and DCK are level-shifted (boosted) and used as sample hold pulses SHP231 to SHP234. Thereby, the dispersion | variation in the sample hold pulses SHP231-SHP234 can be suppressed. As a result, ghosts caused by variations in the sample hold pulses SHP231 to SHP234 can be removed.

  In addition, in the horizontal scanner 23, the horizontal clocks HCKX and HCK that are the reference of the shift operation of the shift register 231 are not extracted and used as the sample hold pulse, but have the same period and different phases based on the horizontal clocks HCKX and HCK. Clocks DCKX and DCK are separately generated, and these clocks DCKX and DCK are extracted and used as sample hold pulses SHP231 to SHP234, so that complete non-overlapping sampling between sampling pulses is realized during horizontal driving. As a result, the occurrence of vertical stripes due to overlap sampling can be suppressed.

In the above-described embodiment, the horizontal scanner (horizontal scanning drive circuit) has been described. However, the present invention can also be applied to vertical scanning (vertical scanning drive circuit).
The vertical scanner is a drive circuit that outputs a transistor selection pulse to the gate line of the pixel TFT. The configuration of sequentially shifting the pulses is the same as that of the horizontal scanner, and can be realized by a configuration using a shift register. In addition, in the case of having the upside down function, it is the same function as the horizontal scanner of the horizontal scanner, and this is also the same as the horizontal scanner.
Therefore, in the vertical scanner as well as the horizontal scanner, both the shift register and the scanning direction switching block can be driven with a low voltage.

FIG. 9 is a circuit diagram showing a specific configuration example of the vertical scanner according to the present embodiment.
FIG. 10 is a timing chart of the vertical scanner of FIG.

  The vertical scanner 22 in FIG. 9 includes a shift register 221, a first buffer group 222, a second buffer group 223, and a level shifter group 224.

Shift register 221 includes a number of shift stages (SW / R stages) corresponding to the gate lines, and vertical start pulse 2VST is applied to, for example, first (first stage) shift stage 221-1 by external clock generation circuit 24, for example. Then, the shift operation is performed in synchronization with the vertical clock 2VCK and the inverted vertical clock 2VCKX (hereinafter, both referred to as vertical clocks) having opposite phases.
As a result, as shown in FIGS. 10G and 10H, the shift stages 221-1, 221-2,... Of the shift register 221 have the same pulse width as the cycle of the vertical clocks 2VCK and 2VCKX. Shift pulses SFTP 221, SFTP 222,... That are sequentially output to the first buffer unit 222.

The first buffer group 222 enables the shift pulses SFTP221, SFTP222,... Output from the shift stages 221-1, 221-2,... Of the shift register 221 as shown in FIG. The signal ENB is received and amplified, and the signals BPLS221, BPLS222,... As shown in FIGS. Output to the second buffer group.
As shown in FIG. 9, each buffer stage 222-1, 222-2,... Is configured by a series circuit of a NAND gate and an inverter INV.

The second buffer group 223 shows signals BPLS 221, BPLS 222,... From the respective buffer stages 222-1, 222-2,. Are received by the vertical clocks half2VCK and half2VCKX, and signals BPLS2211, BPLS2212, BPLS2221 as shown in FIGS. 10K to 10N are obtained from the buffer stages 223-1, 223-2,. , BPLS 2222,... Are output to the shift register group 224 in the next stage.
Each buffer stage 223-1, 223-2,... Is configured by a series circuit of a NAND gate and an inverter INV, as shown in FIG.

  The level shifter group 224 boosts the signals BPLS 2211, BPLS 2212, BPLS 2221, BPLS 2222,... Output from each buffer stage of the second buffer group 223 as shown in FIGS. 21, level shifters 224-1 to 224-4 that sequentially apply 21, SP 22, SP 23, and SP 24 to the corresponding gate lines GTL 21 to GTL 24.

Thus, after transferring the shift pulse, the vertical scanner 22 provides a buffer unit to amplify the buffer so that it has sufficient drive capability with respect to the panel load. Since this selection pulse is a control signal for writing a video signal to the pixel, if the pixel TFT is composed of an n-channel transistor, the drive voltage needs to have a margin more than the maximum potential of the video signal. In the case of a p-channel transistor, it is necessary to have a potential lower than the minimum potential of the video signal.
In addition, a high potential that sufficiently turns off the pixel TFT is required. Therefore, the gate pulse must be level-shifted to a voltage having a sufficient driving capability for the liquid crystal threshold voltage ± 5V.
Therefore, a level shifter circuit is introduced in front of the buffer to shift the level of the pulse. In the vertical scanning drive circuit, with respect to the input signal V, the shift register and the scanning direction switching block drive the driving voltage V1 at the same potential as V or a low voltage with a slight margin. The buffer unit level-shifts the pulse, and the drive voltage V2 is driven with V1 <V2.

Further, in addition to the horizontal scanner and the vertical scanner, there is a precharge circuit 25 as a peripheral circuit. The precharge circuit 25 includes a batch precharge method and a dot sequential precharge method as typical methods. Here, a circuit block of the dot sequential precharge method will be described.
The batch precharge method includes a signal for controlling a sampling switch and a precharge potential as signals, and the circuit configuration is only a switch.
Since the dot sequential precharge is precharged in a dot sequential manner as the name suggests, the circuit configuration is basically the same as that of the horizontal scanner 23.

FIG. 11 is a circuit diagram showing a specific configuration example of the precharge circuit according to the present embodiment.
FIG. 12 is a timing chart of the precharge circuit of FIG.

  The precharge circuit 25 in FIG. 11 includes a shift register 251, a buffer group 252, a level shifter group 253, and a sampling switch group 254.

Shift register 251 includes a number of shift stages (SW / R stages) corresponding to the signal lines, and precharge start pulse PST is applied to, for example, first (first stage) shift stage 251-1 by an external clock generation circuit, for example. Then, a shift operation is performed in synchronization with a precharge clock PCK and an inverted precharge clock PCKX (hereinafter both referred to as a precharge clock) having opposite phases.
Thus, as shown in FIGS. 12D and 12E, each shift stage 251-1, 251-2,... Of the shift register 251 has the same pulse width as the cycle of the precharge clocks PCK and PCKX. Are sequentially output to the buffer unit 252. The shift pulses SFTP251, SFTP252,.

The buffer group 252 amplifies the shift pulses SFTP251, SFTP252,... Output from the shift stages 251-1, 251-2,... Of the shift register 251, and the buffer stages 252-1, 252-2. ,..., Signals BPLS 251, BPLS 252,..., As shown in FIGS.
Each buffer stage 252-1, 252-2,... Is configured by a series circuit of a NAND gate and an inverter INV, as shown in FIG.

  The level shifter group 253 boosts the signals BPLS 251, BPLS 252,... Output from each buffer stage of the buffer group 252, as shown in FIGS. 10 (F) to (I), and the sample hold pulses SHP251, SHP252,. .. Are applied to the sampling switches 254-1, 254-2,... Of the corresponding sampling switch group 254.

  The sampling switches 254-1, 254-2,... Of the sampling switch group 254 respond to the sample hold pulses SHP251, SHP252,... When given the sample hold pulses SHP251, SHP252,. The precharge signal PSIG given from the outside is sequentially sampled and supplied to the signal lines SGNL21, SGNL22,.

  The precharge circuit 25 also requires a shift register for transferring pulses and a circuit block for determining left-right inversion, and these blocks are driven at a low voltage as in the horizontal scanner. A short L length of the transistor is also implemented as a circuit configuration for that purpose.

In the present embodiment, an analog video signal is input, and this is sampled and applied to a liquid crystal display device equipped with an analog interface driving circuit that drives each pixel in a dot-sequential manner. Can be applied to a liquid crystal display device equipped with a digital interface drive circuit that takes the input and latches it, converts it into an analog video signal, samples the analog video signal, and drives each pixel in a dot sequence It is.
In the present embodiment, the case where the present invention is applied to an active matrix liquid crystal display device using a liquid crystal cell as a display element (electro-optical element) of each pixel has been described as an example. It is not limited, but an active matrix display using a dot sequential drive system that employs a clock drive system in a horizontal drive circuit, such as an active matrix EL display device using an electroluminescence (EL) element as a display element of each pixel. Applicable to all devices.

  In addition to the well-known 1H inversion driving method and the dot inversion driving method, the dot sequential driving method has the same polarity in the pixel arrangement after the video signal is written, and the left and right pixels adjacent to each other. There is a so-called dot line inversion driving method in which video signals having opposite polarities are simultaneously written in two rows separated by odd numbers between adjacent pixel columns, for example, pixels in two upper and lower rows so that the pixels have opposite polarities.

It is a figure which shows the structure of the active matrix type liquid crystal display device which employ | adopted the general point sequential drive system. It is a figure for demonstrating the specific structure of the horizontal scanner of FIG. 3 is a timing chart for explaining the operation of the circuit of FIG. 1. 1 is a circuit diagram illustrating a configuration example of an active matrix liquid crystal display device of a dot sequential driving method according to an embodiment of the present invention. FIG. 5 is a block diagram illustrating a configuration example of a display panel of the active matrix liquid crystal display device of FIG. 4. It is a circuit diagram which shows the specific structural example of the level shifter which concerns on this invention. FIG. 7 is a waveform diagram for explaining the level shifter of FIG. 6. 5 is a timing chart for explaining the operation of the circuit of FIG. 4. It is a circuit diagram which shows the specific structural example of the vertical scanner which concerns on this embodiment. 10 is a timing chart of the vertical scanner of FIG. 9. It is a circuit diagram which shows the specific structural example of the precharge circuit which concerns on this embodiment. 12 is a timing chart of the precharge circuit in FIG. 11.

Explanation of symbols

DESCRIPTION OF SYMBOLS 20 ... Liquid crystal display device, 21 ... Effective pixel part (PXLP), 22 ... Vertical scanner (VSCN), 23 ... Horizontal scanner (HSCN), 231 ... Shift register, 232 ... Extraction switch group, 233 ... Level shifter group, 234 ... Sampling Switch group, 24: clock generation circuit (GEN), 25: precharge circuit (PRCG), 30 ... display panel.

Claims (9)

A plurality of pixels arranged in a matrix, and a pixel portion in which a drive line is wired for each pixel column or row;
A driving circuit for driving the pixel portion,
The drive circuit is
A shift register that sequentially outputs shift pulses from each shift stage in synchronization with a clock signal serving as a reference for scanning of the first power supply level;
A level shifter group that generates a signal of a second power supply level higher than the first power supply level based on a shift pulse by the shift register;
A display device that drives each corresponding drive line of the pixel portion based on a signal after the level shift. The drive line includes a signal line wired for each pixel column,
The drive circuit includes a horizontal scan,
The horizontal scanner
A shift register that sequentially outputs a shift pulse from each shift stage in synchronization with a clock signal and an inverted clock signal that are opposite in phase to be a reference for horizontal scanning of the first power supply level;
A first switch group that alternately and sequentially extracts the clock signal and the inverted clock signal in response to the shift pulse output from the corresponding shift stage of the shift register, and outputs the sample signal as a sample hold pulse;
A level shifter group for level-shifting the sample hold pulse by the first switch group to a second power supply level higher than the first power supply level;
The display device according to claim 1, further comprising: a second switch group that sequentially samples a video signal in response to a sample hold pulse by the level shifter group and supplies the video signal to each corresponding signal line of the pixel unit. The horizontal scanner is supplied with two second clock signals having the same period and different phases based on the clock signal and the inverted clock signal,
Each switch of the first switch group of the horizontal scanner and either one of the two second clock signals are extracted,
The display device according to claim 2, wherein the level shifter group shifts the level of the extracted second clock signal. The drive line includes a gate line wired for each pixel row,
The drive circuit includes a vertical scan,
The vertical scanner
2. The shift pulse of the shift register is level-shifted to a second power supply level higher than the first power supply level, and the level-shifted signal is sequentially output to each corresponding gate line of the pixel portion. Display device. The drive line includes a signal line wired for each pixel column,
The drive circuit includes a precharge circuit,
The precharge circuit is
The display device according to claim 1, further comprising a switch group that sequentially samples a precharge signal in response to a pulse from the level shifter group and supplies the precharge signal to each corresponding signal line of the pixel unit. The display device according to claim 1, wherein the shift register is driven under substantially the same power supply condition as the input clock. The shift register includes a first channel length transistor, and the level shifter group includes a second channel length transistor;
The display device according to claim 1, wherein the first channel length is set shorter than the second channel length. The shift register includes a transistor with a first channel length, the level shifter group and the second switch group include a transistor with a second channel length,
The display device according to claim 2, wherein the first channel length is set shorter than the second channel length. The display device according to claim 1, wherein the display element of the pixel is a liquid crystal cell.

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