JPH0731321B2 - Capacitive load scanning method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scanning method, and more particularly to a scanning method suitable for an active matrice type display using a display body such as a liquid crystal and having a built-in drive circuit.

[Conventional technology]

A so-called active matrix display in which a thin film active element, for example, a switching element such as a diode or a thin film transistor (hereinafter simply referred to as TFT) is formed on a plate such as glass and combined with a substance having an electro-optical effect such as liquid crystal, It has the feature that it can form a large-area, high-definition, high-quality display. In addition to this, TFT
In the case of using a TFT, a drive circuit is formed by a TFT to reduce the number of connection lines from the outside, reduce the number of external drive circuits, and achieve cost reduction, as well as reliability due to defective connections. It is possible to prevent deterioration of sex. In this way, for displays with built-in drive circuits,
I E E Proceeding 59 (1971
Year) Page 1566 (Proceedings of IEEE, 59, P1566 (1971)
Since then, circuits such as those described in JP-A-56-92573 or JP-A-57-100467 have been proposed. With these circuit configurations, the signal voltage applied to the signal side (data side) wiring can be configured with a few TFT elements per line, but there is room for improvement in the following points. First, the voltage applied to the signal electrode (data line) of the display section is applied to the signal electrode through the TFT element when the TFT element at the output stage of the drive circuit is on, and then the TFT element is turned off. ,
The voltage is held by the capacitance Cl attached to the signal electrode. These operations are performed within a period in which one scan line is selected and a scan voltage is applied to the scan electrode so that the TFT element of the display section is turned on. Therefore, the voltage applied to the signal electrode within this period needs to be held until the end of the scanning period of one line,
If the insulation resistance between the signal electrode and the other part is not sufficient, the voltage applied to the signal electrode capacitance is discharged by the end of the scanning period, and the voltage applied to the TFT of the pixel part decreases,
Since the applied voltage is constantly low in each pixel connected to the signal electrode, uneven brightness occurs in each signal electrode. In order to prevent this, it is necessary to keep the TFT element at the output stage of the driving circuit in the ON state until the scanning period of one line is completed, and supply the current as much as the voltage is discharged from the signal electrode.

Next, it is necessary to consider the problems of the ON characteristics of the TFT element in the display section and the ON characteristics of the TFT element in the output stage. That is, as the display has a larger capacity, that is, a larger area and a larger number of scanning lines, the scanning period of one line becomes shorter, and
The pixel scanning period also becomes short. On the contrary, since the capacitance per line becomes large, the signal lines are sequentially scanned one signal line at a time during one scanning period. So-called dot sequential scanning or a scanning method of sequentially scanning a plurality of signal lines (herein, a plurality of lines scanned at one time is defined as one block and called block sequential scanning) is a relatively large electrostatic capacitance load in a short period of time. Must be charged, and the TFT element at the output stage of the drive circuit must have a large drain transconductance gm. Also, with the above-described scanning method for the TFT element of the display section, the ON voltage of the TFT element is shortened, so that the applied voltage to the liquid crystal is not sufficiently applied and the display contrast ratio is lowered. For this reason, the channel width W of these TFT elements is increased to increase the mutual conductance gm.
Therefore, the area of the circuit is increased, the ratio of the display electrodes in the display section is decreased, and the display characteristics are deteriorated. In order to avoid this, as a driving method, a so-called line-sequential scanning method in which a TFT element of a display unit is turned on and a signal voltage is applied during almost the entire address period of one scanning line Is desirable.

Next, with respect to the configuration of the built-in drive circuit, particularly the drive circuit on the signal side (data voltage generation side), high-speed operation is required, and therefore attention must be paid to the circuit design.
For example, if the number of pixels in the display section is N (the number of pixels in the vertical direction) × M (the number of pixels in the horizontal direction) and the frequency at which one screen is rewritten (hereinafter referred to as the frame frequency) is f _F (Hz), The maximum frequency f _max of the input signal voltage is calculated as f _max = N × M × f _F. For example, the number of pixels of the display unit is N = 400, M = 640 × 3 (× 3 is R,
Assuming three-color display of G and B) and f _F = 60 Hz, f _max = 46.
It is a very high frequency value of 08 × 10 ⁶ Hz = 46.08 MHz.
Since it is very difficult to configure a circuit that operates in such a frequency band from a TFT that uses amorphous silicon or polycrystalline silicon, for example, it is necessary to apply a circuit configuration or signal that matches the characteristics to the TFT element. Improved methods are needed. The above-mentioned publicly known example is a circuit configuration in which input data is applied in parallel and the maximum frequency f _max is lowered by the number of input data, but a portion for inputting a signal from the outside,
The TFT element in the input section uses the same TFT element for applying the input signal to the display section or has a voltage distribution type circuit configuration with electrostatic capacitance using the TFT element as a transfer gate. It is necessary to drive a large capacitance load, and it is difficult to respond to a high frequency input signal.

Further, in the above-mentioned conventional example, the TF for processing the input data signal is used.
The timing for applying a drive voltage such as a scan pulse for operating the T element, or the circuit configuration for generating the drive voltage is such that the selection period of one scan line is divided by the number of blocks with a plurality of signal lines as one block. As the screen becomes large and the resolution becomes high, the width of the scanning pulse becomes short, and therefore, the circuit for generating the scanning pulse is required to operate at high speed.

[Problems to be solved by the invention]

In the conventional technology as described above, in the internal signal drive circuit using the TFT, high-speed input data is efficiently processed,
The point of application to the display section is not taken into consideration, and there is a problem in the operating speed of the circuit and also a problem in the display characteristic of the display section.

The object of the present invention is to improve the speed of input data,
An object of the present invention is to provide a high-speed scanning method capable of utilizing a semiconductor device that switches at a relatively low speed.

[Means for solving problems]

A feature of the present invention that achieves the above object is that one main electrode to which an input signal is applied, the other main electrode to which a capacitive load is connected, and a first potential level and a first potential level. Has a control electrode to which a control signal is applied to alternately shift between different second potential levels at a predetermined cycle, and when the potential applied to the control electrode is at the first potential level, A semiconductor switch element in which a transmission state is established between the electrode and the other main electrode, and a non-transmission state is established between one main electrode and the other main electrode when the potential applied to the control electrode is at the second potential level. A plurality of switch units each including at least one of the switch units, the control signals having the same phase are applied to the semiconductor switch elements belonging to the switch units, and the semiconductor switch elements are sequentially transferred from the transmission state or the non-transmission state to the non-transmission state or the transmission state. Transfer In the scanning method in which the capacitive load is scanned, the semiconductor switch elements belonging to two adjacent switch units are out of phase with each other and the periods in which the first potential level or the second potential level overlaps each other are controlled. It is in a scanning method in which a signal is applied.

[Action]

In order to reduce the frequency of scanning, the scanning signals to be scanned are provided so as to overlap each other. As a result, the period in which the scanning signals change becomes long, so that the frequency can be reduced.

〔Example〕

The principle of the present invention will be described with reference to FIGS. 18 and 19.
FIG. 18 is a configuration diagram for explaining the principle of the present invention,
FIG. 19 is a time chart of FIG.

In FIG. 18, 101 to 104 are four (K = 4) n-channel MOS transistors which are an example of semiconductor switches, and are preferably thin film transistors (hereinafter referred to as TFTs) on a glass substrate.
Called)). A continuous input signal Vin such as an analog or digital image signal is commonly applied to one of the main electrodes of the TFTs 101 to 104. Capacitive loads 201 to 204 are connected to the other main electrodes of the TFTs 101 to 104, respectively.
The capacitive loads 201 to 204 are preferably liquid crystal, wiring capacitance, input gate capacitance of the MOS transistor in the next stage, and the like. TFT10
The control electrodes 1 to 104 have a first potential as a control signal for controlling an ON state in which the input signal Vin is transmitted from one main electrode to the other main electrode and an OFF state in which the input signal Vin is not transmitted. Scan pulses φ ₁ , φ ₂ , φ ₃ , and φ ₄ composed of the level V ₁ and the second potential level V ₂ are applied, respectively. Here, V ₁ is, for example, the ground potential (OV), and V ₂ is the power supply potential (Vcc = 5V).

In FIG. 19, at time t ₁ , φ ₁ changes from V ₁ to V ₂ , and the TFT
104 transitions from the off state to the on state, as the voltage V ₂₀₁ volumes load 201, the volumetric load 201 input signal Vin is applied.

At time t _2, φ ₁ is without change, of V ₂ as it is, TFT10
1 keeps on. Here, φ ₂ changes from V ₁ to V ₂ , the TFT 102 shifts from the off state to the on state, and the input signal Vi to the volume load 202 is the same as the voltage V ₂₀₂ of the volume load 202.
n is applied.

At time t ₃ , φ ₁ changes from V ₂ to V ₁ , the TFT 101 shifts from the ON state to the OFF state, and the capacitive load 201 changes to the previous TFT.
The value of the input signal Vin when 101 is turned on is held for a predetermined period. At this time, this value may slightly decrease due to the presence of the leakage resistance. Φ ₂ remains unchanged at V ₂ and the TFT10
2 remains on. That is, in the period of time t ₂ or time t ₃ , the adjacent scans φ ₁ and φ ₂ are V ₂ and two (L = 2)
Both the TFTs 101 and 102 are in the ON state, the input signal Vin is applied to both, and φ ₃ and φ ₄ are V ₁ , and the TFTs 103 and 104 are both in the OFF state. Also, at time t ₃ , φ ₃ changes from V ₁ to V ₂ and the TFT
The input signal Vin is applied to the volumetric load 203 like the voltage V ₂₀₃ of the volumetric load 203 when the state 103 is turned on.

At time t ₄ , φ ₁ remains V ₁ and does not change, and the TFT 101 holds from the off state. φ ₂ changes from V ₂ to V ₁
Changes from the ON state to the OFF state, and the capacitive load 202 is
The value of the input signal immediately before the TFT 102 is turned on is held for a predetermined period. φ ₃ remains V ₂ and does not change, and the TFT 103 maintains the ON state. φ ₄ changes from V ₁ to V ₂ , the TFT 104 transitions from the OFF state to the ON state, and the input signal Vin is applied to the volumetric load 204 as the voltage V ₂₀₄ of the volumetric load 204.

That is, in the period from time t ₃ to time t ₄ , φ ₂ and φ ₃ are V ₂ , and two (L = 2) scans adjacent to each other are in the ON state, and the TFTs 102 and 103 are both in the ON state, and scans are adjacent to _{each other} . Both φ ₄ are V ₁ and TFT101,1
Both 04 are off.

At time t ₅ , φ ₁ changes from V ₁ to V ₂ as at time t ₁ . In the period from time t ₄ to time t ₅ , the scans are adjacent φ
₁ and φ ₂ are V ₁ , two TFTs 101 and 102 (L = 2) are both off, and φ ₃ and φ ₄ are both V ₂ , and two TFTs 103 and 104 are both on. Below, the time t _6, t ₇ ... is repeated in the same manner as the.

The period from time t ₁ to t ₅ is one cycle, and in this cycle,
The scanning signals φ _{1 to} φ ₄ sequentially change from V ₁ to V ₂ , and the TFT 101 to
104 sequentially shifts from the off state to the off state. Further, in this one cycle, the scanning signals φ _{1 to} φ ₄ sequentially change from V ₂ to V ₁ , and the TFTs 101 to 104 sequentially shift from the off state to the on state. Incidentally, in FIG. 19, the period from time t ₁ to t ₂ , from t ₂ to t ₃
, The period from t ₃ to t ₄ , the period from t ₄ to t ₅ , etc. are substantially equal, but may be unequal.

In this way, since the scanning signals φ _{1 to} φ ₄ overlap and overlap each other, the substantial frequency of each of φ _{1 to} φ ₄ is reduced, and the TFTs 101 to 104 have the switching characteristics of such high speed. Alternatively, the scanning signal can be obtained. In other words, a high-speed scanning signal can be obtained without changing the switch characteristics of the TFTs 101 to 104.

In FIG. 19, K = 4, L = 2, and K = 2L. However, when K is an odd number, it is preferable to set K = 2L-1 or K = 2L + 1. .

A specific embodiment of the present invention will be described with reference to FIG.

Figure 1 shows a transparent insulating substrate made of glass, plastic, etc.
TFT element formed on 16 and a large number of pixels 1
8 is a flat-type display including eight, a plurality of scanning electrodes 15 and a plurality of signal electrodes 12 for driving each pixel, a scanning circuit 14 and a signal circuit having a configuration described below.
Each pixel 18 is composed of a TFT element 18-1 and a display body such as a liquid crystal between electrodes driven by the TFT element 18-1.

As the configuration of the signal circuit, a signal input wiring 1 and a drain electrode for supplying a data signal for display including a video signal for displaying a television etc. (here, the TFT element has an n-channel configuration and an input side is used). One main power source is called the drain, and the other main electrode on the output side is called the source.In the structure of the TFT element, the source and drain electrodes can be formed in a completely symmetrical manner. Is connected for convenience of description.) Connect at least two or more gate electrodes (three (M = 3) control gate electrodes in FIG. 1) of TFT elements connected to The gate 4 of each of the K blocks is connected to a scanning voltage generating circuit 3 for generating scanning voltage signals φ ₁ , φ ₂ , φ ₃ , ... For scanning each block. The drain electrode of the TFT element 6 for data sampling is connected to the source electrode of each TFT element in the block, and the gate electrode of the TFT 6 for data sampling is connected to the wiring group 5 for data sampling. To the source electrode of the data sampling TFT, the data holding capacitance 7 and the data transfer TFT element 10 drain electrode are connected. In this embodiment, the data sampling TFT 6 corresponds to the TFT 101 or the like in FIG. 18, and the data holding capacitance 7 corresponds to the capacitive load 201 or the like in FIG. TFT
A buffer amplifier 11 is connected to the source electrode of the element 10, and the output of the buffer amplifier 11 drives the signal electrode group 12 of the display section.

If the configuration of this signal circuit is classified according to its operation, the TFT
The element 2 and the TFT element 6 and a signal system associated with each of them serve as a sampling circuit for signal input, the TFT element 6 and the electrostatic capacitance 7 are hold circuits, the TFT 10 is a data transfer circuit, and the buffer circuit 11 is a drive circuit of the display section. Has become.

The circuit 3 and the circuit 14 are circuits for generating a scanning voltage for sequentially scanning one block or one line, centering on a shift register circuit, and if necessary,
Insert a level exchange circuit and a buffer circuit in the output stage. The buffer circuit 11 is a circuit for amplifying or impedance-converting the voltage applied to the electrostatic capacitance existing in the input stage and applying the voltage to the display unit. A circuit is possible.

FIG. 2 is a modification of the circuit of FIG. The signal V ₂ applied to the signal input wiring 1 is switched by one TFT element 2 for each block and applied to the TFT element 6. It is possible to reduce the number of TFT elements, which leads to improved reliability.

FIG. 3 shows the characteristic of the output voltage Vout with respect to the input voltage Vin of the inverter circuit. This characteristic is the case where the TFT element is a TFT using polycrystalline silicon and the inverter circuit configuration is a so-called E / E type inverter using two enhancement type TFTs.
There is a region where out changes almost linearly, and this part is used as the operating region of the buffer. That is, in the region of the input voltage Vin ₁ and Vin 2 in FIG. ₂ , the output voltage Vout ₁
And the voltage Vout ₂ change linearly. The slope of this part and the bias voltage value with respect to the input voltage value change depending on the circuit design constants such as the characteristics of the TFT element and the inverter ratio, but drive conditions should be determined so that the part where the linear region appears is set as the operating region. Good.

Generally, the TFT element is a MOS structure element, and the gate input impedance is sufficiently high. Therefore, using the inverter circuit as shown in FIG. Since there is no discharge through the input part of the circuit 11, the retention characteristics of the signal sent from the transfer gate 10 are good.

FIG. 4 shows drive voltage waveforms applied to the respective parts of FIG.
The scan voltages Vsc ₁ , Vsc ₂ , Vsc ₃ ... Applied to the scan electrodes, the video input signal Vv applied to the pixels of each scan electrode, and each TFT
Voltage signals φ ₁ , φ ₂ , φ for sequentially scanning block 2
₃ , ..., Clock pulse CP ₁ applied to the gate of the TFT element 6 for sampling the data in each block,
It is composed of CP ₂ and CP ₃ and a voltage Vst for transferring the data voltage held in the capacitance 7 for data storage to the buffer section. Video signal Vv is φ ₁ , φ ₂ , φ ₃ , ... And CP ₁ , CP ₂ , C
Capacitance 7 is sampled at the time when TFT 2 and TFT 6 are turned on by applying both P ₃ and when either TFT 2 or TFT 6 is turned off. Voltage is maintained. In the combination of the scanning voltage φ and the clock pulse CP, both the TFT2 and the TFT6 are turned on only once in one scanning line period, so that the video signal Vv is on the left side of FIG. Is sequentially accumulated in the capacitance of. It goes without saying that Vv can be accumulated from the capacitance on the right side by reversing the application direction of the scanning voltage φ and the application order of CP. At this time, TFT2 and TFT6
In the characteristic of, the off resistance is determined so that the on resistance charges the capacitor 7 during the on period of each of CP ₁ , CP ₂ , and CP ₃ and holds the voltage of the capacitor 7 during the off period. The maximum value of the off period is the leftmost signal line in the case of FIG. 1, and the period is almost equal to one scanning period. The ratio of the ON period to the OFF period is approximately equal to the value of M in the display having M pixels in the horizontal direction. Since M is about 2000 pixels,
The on / off ratio of the TFT element is sufficient for charging and holding. Next, the voltage applied to the input portion of the buffer circuit 11 is determined by the capacitance division between the capacitance 7 and the input capacitance of the buffer circuit 11, but the capacitance 7 may be set larger than the input capacitance of the buffer circuit. In the conventional example in which the buffer circuit does not exist, the capacitance 7 larger than the capacitance attached to the signal electrode is used.
It was difficult to charge the capacitor 7 at a high speed with TFT2 and TFT6 because it had to be made. In contrast,
In this embodiment, the capacitance 7 does not have such a large value, so that the TFT 2 and the TFT 6 can be charged at high speed.

The output of the buffer circuit is almost 1 except for the blanking period.
It is possible to apply a voltage to the signal electrode during the scanning period of the horizontal line, and if the insulation resistance between the signal electrode and the scanning electrode varies, or if the insulation resistance of the gate insulating film of the TFT element in the display section is Even if there are variations, the current can be supplied by the buffer circuit, so that it is easy to keep the voltage of the signal electrode constant, and uneven display can be prevented.

Further, the operating speed of the circuit for generating the scanning voltages φ ₁ , φ ₂ , φ ₃ , ... Can be reduced by the number of TFTs 2 in one block as compared with the case of the dot sequential scanning. Figure 1,
The example shown in FIG. 2 is configured to use three TFT elements in one block, but by increasing the number, the operating frequency of the circuit 3 can be lowered, and the TFT elements facilitate the circuit operation. Can be built in.

Further, in the present embodiment, the analog signal of the input signal is applied through one input terminal, so that it is not necessary to perform complicated signal processing such as serial-parallel conversion on the outside of the input signal, and an external circuit configuration is provided. Can be simplified.

FIG. 5 is a modification of the drive waveform of FIG. A DC voltage is applied to Vv, and a video signal voltage is applied to the common wiring 8 of the electrostatic capacitance 7. The voltage of capacitance 7 is
Since it is determined by the difference voltage between the source electrode of the sampling TFT 6 and the wiring 8, it is possible to apply the same voltage as that in FIG. 3 (however, the polarity is inverted) to the capacitor 7.

FIG. 6 is a modification of FIGS. 4 and 5. When driving a liquid crystal such as a TN liquid crystal, the driving voltage becomes an alternating current, and it is necessary to apply a waveform with a small direct current component. In a display using a TFT, the voltage applied to each pixel needs to be a voltage with positive and negative inversion applied for each frame. As the inversion method, a method of inverting the signal polarity for each screen,
Inversion methods such as a method of inverting the polarity of the signal for each scanning line have been proposed. In any case, it is necessary to generate a signal voltage whose polarity is inverted around a certain level, but in FIG. 6, the voltage applied to Vv and Vb is switched for each scanning line, and the capacitance 7 is changed. Differential voltage Vc (Vc = Vv−V
b) is an example in which a waveform that inverts every scan line is generated. Switching between Vv and Vb may be performed for each screen, and in this case, a voltage whose polarity is inverted can be generated for each screen.

As described above, the circuit configuration of this embodiment has a feature that a signal voltage obtained by inverting the input voltage can be easily created.

FIG. 7 shows a configuration in which the number of signal lines in one block is doubled to six (M = 6) as compared with the configuration of FIG. 1 or 2. The block scanning voltages φ ₁ , φ ₂ , ... φ _k can be reduced to half the frequency (pulse width is doubled) as compared with the configuration of FIG. 1 or 2. That is, the larger the number of signal lines in one block, the lower the frequency of the block scanning voltages φ ₁ , φ ₂ ,.

Next, FIG. 8 shows waveforms of CP ₁ , CP ₂ , ..., CP ₆ corresponding to the sampling voltages CP ₁ , CP ₂ , CP ₃ of FIG. 4 in the configuration of FIG. 7. In the embodiment shown in FIG. 8, CP ₁ and CP ₂ , CP ₂ and CP ₃ ,
Or ... The feature is that a period of overlapping adjacent pulses of CP ₅ and CP ₆ is provided. Voltage held in the capacitor 7 with the output of the TFT6 sampling voltage CP _1, CP ₂ ... for (preferably ground potential = 0) CP ₃ is V ₃ remains the level immediately before the, previous period sampling voltage It does not matter even if V ₄ (preferably the power supply potential Vcc = 5V) is applied. That is, the pulse width of the sampling voltage becomes longer by making the configuration shown in FIG. 8 (a) to FIG. 8 (b) and further as shown in FIG. 8 (c). Since the operation speed of the data sampling voltage generating circuit 13 is very loosely limited, the circuit design becomes easy and the TFT element characteristics have a margin.

FIG. 9 shows an example of a circuit configuration for generating the waveform shown in FIG. FIG. 9A shows the configuration of a normal shift register circuit. 6 sampling voltages CP ₁ , CP ₂ ,
…, 6-stage shift register is used to generate CP ₆ . In order to lengthen the output pulse in the configuration of FIG. 9 (a), the input voltage Vst may be lengthened. FIG. 9 (b) shows a configuration using two systems of shift registers. Vst ₁ and Vs
By offsetting t ₂ from each other by half a pulse and operating each shift register at a frequency of 1/2 in FIG. 9 (a), overlapping sampling voltages CP ₁ , CP ₂ , ... CP
You get ₆ . Further, FIG. 9 (c) shows a configuration using shift registers of three systems. It can be operated at 1/3 the frequency of (a).

Although FIG. 9 shows a configuration using a shift register, it goes without saying that a similar waveform can be obtained by using a circuit such as a flip-flop.

Since the sampling voltage can be lowered in frequency by the above-described driving method and circuit configuration, the circuit can be easily configured using the TFT.

On the other hand, the pulse widths of the block scanning voltages φ ₁ , φ ₂ , ... Can be lengthened as shown in FIGS. 8A, 8B and 8C by the same method as described above. In FIG. 10, the operating frequency of the shift register can be lowered by adopting a configuration (b) in which two systems of shift registers are provided, in contrast to the conventional configuration (a) of one system of shift registers. FIG. 20 shows an example of a circuit configuration for realizing FIG. 9 (b). By providing two stages of shift registers that operate with a two-phase clock and making each clock pulse in opposite phase, CP ₁ , C
Waveforms in which the phases of P ₂ and CP ₃ and CP ₄ are shifted by half a phase can be output.

FIG. 21 (a) has the same circuit configuration as FIG. 20, but has a common clock line and power supply line.

The operation waveforms of these circuits are shown in FIG. 21 (b). CP ₁
To obtain the output to CP ₄ from 2-phase clock 1 and clock 2 and a half-phase by the phase-shifted input signal Vin and Vi
Use n '. The operating frequency of the shift register can be halved compared to the case where only one column of shift register is used to obtain the outputs from CP ₁ to CP ₄ .

Figure 22 (a), a (b) uses the four phase clock, the circuit personality and its time chart to obtain an output V ₀₁ ~V ₀₄ whose phases are shifted 1/4. In this case, it is possible to reduce the frequency to 1/4 as compared with the case of one shift register column.

FIG. 23 (a) shows the outputs ₁ and _{2 of the} scanning voltage generating circuit 3 '.
Is obtained by combining the multi-phase clock wiring 5'and the switch circuit 2'to obtain the scanning voltages φ ₁ , φ ₂ , φ ₃ . As an example of the switch circuit 2 ', as shown in FIG. 23 (b), it is conceivable that two TFT elements are used to obtain the output voltage c by the two-phase clocks a and b.

The drive waveform is shown in FIG. 23 (c). ₁ is switched by 4-phase clock pulse CP ₁ ′, CP ₂ ′, CP ₃ ′, CP ₄ ′, φ
We obtained ₁ , φ ₂ , φ ₃ , and φ ₄ .

FIG. 11 is a modification of the circuit configuration diagram of FIG. In this system, a buffer circuit 19 is provided at the output stage of the TFT element 2 to amplify the voltage. In this way, it is possible to insert a buffer circuit for the purpose of voltage amplification, level silt, or the like.

FIG. 12 shows a configuration in which the sampling TFT 6 is connected to the signal input wiring, and the scanning wiring 4 and the TFT 2 are connected to the output stage of the TFT 6. The operation of the circuit is the same as the circuit of Fig. 1, but TF
If the voltage held by the capacitance connected to the output stage of the T element 2 is affected by the voltage applied to the gate voltage by the gate-source capacitance of the TFT element, CP ₁ , CP ₂ ,
CP ₃ has a higher frequency than φ ₁ , φ ₂ , ..., It is more likely to affect the voltage of the electrostatic capacitance, and the configuration of FIG. 7 has the advantage that the influence of the gate voltage is smaller. It goes without saying that the driving method shown in FIGS. 4, 5, and 6 can be applied to the embodiment shown in FIG.

FIG. 13 shows the circuit of FIG. 1 with three colored input signal wirings 1.
It is a configuration example in the case of supporting. Supports three-color display
With respect to the video signals of Vvr, Vvg, and Vvb, nine TFT elements are set as one block and sampling is performed with three-phase clock voltages CP ₁ , CP ₂ , and CP ₃ . Connected to the same clock wiring,
If the TFT element to which the same control signal is applied is a switch unit, in this embodiment, each switch unit has three color displays R, G ,.
Corresponding to B, three TFT elements are included. With this configuration, it is possible to drive 9 pixels (3 dots, where 3 colors of R, G, and B are 1 dot). By changing the order of applying Vvr, Vvg, and Vvb for each line, it is possible to display the color arrangement of the mosaic structure.

FIG. 14 shows an example of a circuit configuration using a p- and n-channel CMOS configuration switch and its drive waveform. Since the polarity of the signal voltage is inverted every line or every frame, it is necessary to pass the voltage of both positive and negative polarities p,
The operation speed can be improved by configuring the switch using the TFT elements of both n channels.

FIG. 15 shows a method of preventing the gate voltage from being weighted to the source by capacitive coupling due to the gate-source capacitance of the TFT element. Instead of each TFT described so far, two TFT elements are used respectively, and one of the two TFT elements applies a voltage whose logic is inverted to the gate to cancel the capacitive coupling from the gate. .

FIG. 16 shows an example of a method of forming an electrostatic capacitance which becomes a capacitive load. Normally, the capacitance is formed by two layers of metal electrode and one layer of insulating film, but here, a transparent electrode on the glass substrate facing the TFT substrate is formed like the electrode 21, and electrostatic capacitance on the TFT substrate is formed. The electrode 20 is also formed in a portion requiring a capacitance.
By encapsulating liquid crystal when forming a display, a capacitance having good characteristics can be formed between these two electrodes. In addition to this, if these two sets of electrodes are formed of transparent electrodes, liquid crystal operates because voltage is applied during circuit operation,
It is also possible to inspect the operation of the circuit.

In addition to Fig. 16, except for the case where the counter glass electrode as shown in Fig. 12 is used as an electrode for forming electrostatic capacitance, etc., in order to perform the circuit operation described above stably, FIG. 17 shows an example in which the transparent electrode on the counter substrate on the circuit forming portion is removed. Transparent electrode area 29 on the opposite glass substrate 24
Are formed only on the display unit 25, and the scanning circuit 22 and the signal circuit 23 are formed.
The above is the removed configuration. As a result, the speed of the circuit can be increased by reducing the capacitive coupling between each part of the circuit and the counter glass substrate.

In the above embodiments, line sequential scanning has been described as an example, but it goes without saying that the scanning method of the present invention can be applied to point sequential scanning.

〔The invention's effect〕

 According to the present invention, a high-speed scanning method can be obtained.

[Brief description of drawings]

Fig. 1, Fig. 2, Fig. 7, Fig. 9, Fig. 10, Fig. 11, Fig.
Figure 12, Figure 13, Figure 14, Figure 15, Figure 16, Figure 17, Figure 18
FIG. 20, FIG. 21, FIG. 21, FIG. 22, and FIG. 23 are circuit configuration diagrams of an embodiment of the present invention, FIG. 3 is an inverter circuit diagram and characteristic diagrams, FIG. 4, FIG. 5, FIG. FIG. 8, FIG. 8 and FIG. 19 are drive waveform diagrams. 1 ... Signal input wiring, 2,6,10 ... TFT element, 3 ... scanning voltage generating circuit, 5 ... clock wiring, 7 ... electrostatic capacity, 11
...... Buffer circuit, 16 …… TFT substrate, 17 …… Input pad, 13 …… Clock generator circuit, 18 …… Display section.

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Masayoshi Suzuki 4026 Kuji Town, Hitachi City, Ibaraki Prefecture Hitate Works Ltd., Hitachi Research Laboratory (72) Inventor Masaru Takahata 4026 Kuji Town, Hitachi City, Ibaraki Prefecture Nitate Works Co., Ltd. Hitachi Research Laboratory (72) Inventor Keiji Nagae 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Hitachi Research Laboratory, Hitachi Co., Ltd. (56) Reference JP-A-49-74438 (JP, A)

Claims (2)

[Claims] 1. A main electrode to which an input signal is applied, another main electrode to which a capacitive load is connected, and a first potential level and a second potential level different from the first potential level. And a control electrode to which a control signal is alternately applied at a predetermined cycle between the control electrode and the first main electrode and the other main electrode when the potential applied to the control electrode is the first potential level. At least a semiconductor switch element that is in a transmission state with the electrodes and is in a non-transmission state between the one main electrode and the other main electrode when the potential applied to the control electrode is at the second potential level. A plurality of switch units including one are provided, and control signals of the same phase are applied to the semiconductor switch elements belonging to the switch units, and the semiconductor switch elements are sequentially transferred from the non-transmission state to the non-transmission state or the transmission state. In the scanning method of shifting and scanning the capacitive load, the semiconductor switch elements belonging to two adjacent switch units have phases that are out of phase with each other and are at the first potential level or the second potential level. A scanning method, wherein control signals overlapping each other are applied. 2. When the number of semiconductor switching elements belonging to the switch unit is plural, the different input signals are applied to one of the main electrodes of the semiconductor switching elements. A scanning method characterized by: