TWI277162B - Semiconductor device package utilizing proud interconnect material - Google Patents

Semiconductor device package utilizing proud interconnect material Download PDF

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Publication number
TWI277162B
TWI277162B TW093132201A TW93132201A TWI277162B TW I277162 B TWI277162 B TW I277162B TW 093132201 A TW093132201 A TW 093132201A TW 93132201 A TW93132201 A TW 93132201A TW I277162 B TWI277162 B TW I277162B
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Taiwan
Prior art keywords
semiconductor package
solder
conductive
semiconductor
conductive particles
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Application number
TW093132201A
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English (en)
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TW200520125A (en
Inventor
Martin Standing
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Int Rectifier Corp
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Application filed by Int Rectifier Corp filed Critical Int Rectifier Corp
Publication of TW200520125A publication Critical patent/TW200520125A/zh
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Publication of TWI277162B publication Critical patent/TWI277162B/zh

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    • H—ELECTRICITY
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    • H01L23/4825—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body for devices consisting of semiconductor layers on insulating or semi-insulating substrates, e.g. silicon on sapphire devices, i.e. SOS
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
    • B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
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    • B23K35/262—Sn as the principal constituent
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  • Engineering & Computer Science (AREA)
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  • Geometry (AREA)
  • Chemical & Material Sciences (AREA)
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  • Lead Frames For Integrated Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
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1277162 九、發明說明： 相關申請 本申請案係以美國臨時申請案第60/514,095號案(2003 年10月24日申請’發明名稱焊料及焊接方法及無流動/回流 5互連）及美國專利臨時中請案第60/555,794號案(2004年3月 24曰申請，發明名稱利用隆起互連材料之半導體元件封裝 置）為基礎，且請求其優先權。 【韻^明所屬之^技彳衧領域】 發明領域 10 本發明係有關於半導體封裝，且更特別地係有關於一 種互連結構及用以形成此互連結構之糊料。 t先前技術3 發明背景 焊料係一種傳統已知之用以使半導體元件連接至電路 15板上之導性塾之材料。依據已知技術，焊料凸塊可於電路 板之導性墊上形成，諸如半導體晶片之組件可被置於其 上，然後，焊料回流以便使此組件與導性塾連接。另外， 焊料凸塊可於半導體組件上形成，此組件可被置於導性墊 上’且纟干料回流而使此組件與導性墊連接。 20 參考例示用之第1圖，為於電路板10之導性墊14上形成 焊料凸塊，首先，焊料糊料15被沈積於導性墊14之一部份 上。如第1圖所示，為界定用以容納焊料糊料15之區域，焊 料罩12可被施用於電路板1〇之上表面，其包含一位於導性 墊14上之開口。 1277162 茶考第2圖，於使焊料糊料15沈積於導性塾处之後， T料糊料15藉由施熱而回流；即，藉由使焊料糊料至其回 =溫度㈣成紐。於㈣被冷卻後，料凸糾於導 14上形成。需注意焊料凸肋具有彎❹卜表_。f 5曲外表面19係由於焊料回流時之表面張力之故，且於焊料 體積增加時變得更彎曲。因此，為使用此間所述之傳統技 術使組件與電路板上之導耗結合，電純(或組件)上之焊 料刻版需嚴格依循某些容限，其使製造變複雜。 【發明内容】 10 發明概要 依據本發明，糊料被用以形成用以使組件彼此或與電 路板上之導性墊等電連接。 依據本發明之糊料係黏合劑顆粒及填料顆粒及，若需 要，材料之混合物。依據本發明，餐合綱粒係於班 之個別比例係使當黏合劑顆粒溶融時沈殿時糊料形狀未重 大變化但足以使填料顆粒於黏合劑液體冷卻後彼此膠黏形 成結構物。因而形成之結構物可作為互連物。因此，依據 本發明之糊料可用以於表面上形成互連結構，諸如，半導 20體組件之電極或電路板上之導性墊。 ，據本U之互連物係覆蓋，例如，動力半導體元件 之電極上之大面積。再者’此—互連物可作成隆起狀，即， 立處於高於不可谭接周圍區域，其係有利的，因為·· υ使知料圓㈣不重要，此意指基材及職設計以設 1277162 計及容限而言較不重要，因為替代於二平表面間形成焊料 接合（其間，可焊接區域係以焊料罩内之窗界定），”隆起互 連”能使圓角形成包含焊料互連之端緣。 2)使厚互連基本地形成於晶片表面上意指晶片表面及 5 端緣可以環氧樹脂或任何其它適當鈍化材料覆蓋，其因下 列理由而係有利的： a) 鈍化能使晶片上之不同電勢間產生絕緣，容許更高 電壓及更極端之設計。 b) 可導致以某些封裝型式防護晶片所需之處理步驟之 10 降低。 c) 會產生更堅固之元件。 d) 提供較佳之環境防護。 e) 會降低臨界製造容限，因此使此元件更易製造。 本發明之其它特徵及優點可由參考附圖之本發明下列 15 描述而變明顯。 圖式簡單說明 第1及2圖例示依據習知技藝形成焊料凸塊互連之技 術。 第3圖例示以依據本發明之糊料形成之互連之主體之 20 一部份。 第4及5圖例示用以形成依據本發明之互連之技術。 第6圖顯示依據習知技藝之封裝體之截面圖。 第7圖顯示被改質包含依據本發明之互連之封裝體之 第一施例之截面圖。 1277162 第8圖顯示包含依據本發明之互連之封裝體之第二實 施例之側面圖。 第9圖顯示包含依據本發明之互連之封裝體之第三實 施例之側面圖。 5 第10圖顯示被改質包含位於其電極上之互連之半導體 晶片之頂平面圖。 第11圖顯示第10圖所示半導體晶片以箭頭11-11方向 所見之側平面圖。 第12圖顯示以包含依據本發明形成之互連之半導體晶 10 片形成之封裝體之第一變體之透視圖。 第13圖顯示以包含依據本發明形成之互連之半導體晶 片形成之封裝體之第二變體之透視圖。 第14圖顯示第13圖所示封裝體沿14-14線以箭頭方向 所見之截面圖。 15 第15圖顯示依據習知技藝之封裝體之截面圖。 第16圖顯示包含依據本發明形成之互連之覆晶半導體 元件。 第17圖例示含有製得具有依據本發明之互連之晶片之 晶圓。 20 第18 A圖例示依據習知技藝之封裝體與電路板連接時 之截面圖。 第18B圖例示依據本發明之封裝物與電路板連接時之 截面圖。 L實施方式3 1277162 發明詳細說明 之、、曰人物w ^㈣合劑顆粒及填料顆粒 付口且邮之她實施财，料麵粒係焊料 5 10 15 5。較佳實施例進-步包含焊料助炫材料。 粒比:ί發明—方面，相對於填料顆粒比例之黏合劑顆 =例錢當黏合__融時具有足_合舰 顆拉’即，使填料顆粒，，膠黏，，在 係使當Μ彻心Ρ X，侧之部份 ^顆㈣_沈積之糊料形狀無重大變化。 即互連貫質上具有與糊料被沈積時相同之形狀。 用於依據本發明糊料内之填料顆粒較佳係球狀，即使 a形狀(諸如，立抑及平行六面料 意實施本發明時，顆粒形狀無需於幾何形狀上為完美::。 例如，於本發明内，此間所指之球狀僅需為-般之球狀， 7非完吳之球狀。因此’此間所述之顆粒形狀需瞭解不使 本發明限制於完美幾何形狀。 於較佳貫施例中，黏合劑具有高溶融溫度。自95術 及顧（以重量計）之混合物，或95 5%sn、3购及 7 % C u (以重計)找合物形成之焊料係適於作為依據本 發明糊料内之黏合劑材料之焊料例子。 ,用以形成填料之適當材料係銅。肖以形成填料之其它 適當材料係鎳及錫-銀。 〃 、參考第3圖，填料顆粒Μ可由一材料5形成且以另一材 料7塗覆L球狀之銅顆粒當作為導性填料時，可以錄 20 1277162 p早土物书鍍且以錫或銀鈍化。與球狀銅顆粒使用之適當黏 合劑係錫·銀焊料、高糾料，或錫·糾料。 " 球狀鎳顆粒當作為導性填料時，可以錫或銀純化。用 於溶融球狀鎳顆粒之適當黏合劑可為如上列示焊料之任一 5 者。 與錫-銀填料雜使用之適t黏合劑可祕娜料。 10 15 於較佳組成物中，填料可為球形或似球狀，且可構成 混合物總重量之5·4()% ’且黏合劑可為粉末形式之焊料，且 構成混合物總重量之5G_85%。於此較佳實施例，總重量之 約10%可為焊料助熔劑，其可為具溫和純化之樹脂。較户 地，填料顆粒可於15um_65um間之任意者，且焊料黏合齊^ 之顆粒尺寸可為25 um-45 um間之任意者。 依據本發明之糊料之—特別例子包含31.5%(以重量計) 之以銀塗覆之制粒，58·5%(以重量計）之作為黏合劑之 SAC(錫-錫-銅）或SA(錫_銀）合金。sac組成物可為 95.5%Sn ’ 3.8%Ag ’及〇.7%Cu(以重量計），而从組成物係 96%Sn及4%Ag(以重量計）。於此例子中，總重量之_可 為助熔材料。 另-例子可為具抗将塌性質之先前例子之高流動衍生 物。此-焊料糊可包含5%(重量計)之以銀塗覆之錄球，娜 之SAC或SA ’及10%(重量％)之助熔劑。 依據本發明之糊料係特別有用於在表面上形成相對較 平之大面積互連，諸如，基材上之導性墊，或半導體晶片 之電極。依據本發明之糊料之有利特性係當形成_形狀 20 1277162 時，其於施熱使黏合劑回流（即溶融)後係實質上維持· 狀。 7 現蒼考第3、4及5圖，一種製造依據本發明之互連之方 法包含於表面上沈積—含量之依據本發明之糊料。特別 例士所欲里之依據本發明之糊料可被沈積於電路板 10上之導丨生墊4上。電路板1〇可具有置於其上之焊料罩12， 其係圍繞導性墊14。依據本發明之糊料(其包含球形或似球 狀之填料娜I6及導電性齡船8之雜）被沈積於導性 墊14上，且延伸於焊料罩12上。糊料亦可被沈積具有如第* 10圖所不之相對較平之頂部。於較佳實施例，依據本發明之 補可使用刻版或印刷方法沈積，即使其它沈積方法於本 發明内可被考量。 於/尤積糊料後，施加熱造成黏合劑顆粒職融。因此， 若焊料被作為黏合劑，係加熱至使焊料回流為止，即，焊 15料至其回流之溫度。因為黏合劑顆粒18具有遠低於填料顆 粒6之,皿度’填料顆粒16維持固態。但是，黏合劑顆粒μ 熔融且使填料顆粒16變濕。—旦溫度低於黏合劑顆粒之炼 融溫度，填料顆粒16彼此，，膠黏”，藉此，形成如第3及5圖 所示之整體結構。 20 ❻據本發明之一方面，點合劑顆粒之比例被選擇以使 /、達不足以流動之液體，但係、足以使填料顆粒师黏在一 起形成適於作為互連之整體結構之液體。 有利地，已發現依據本發明之糊料於黏合劑溶融及固 化後係貝質上維持其於沈積時之形狀。因此，依據本發明 I277l62 =糊料對於形成用於與外部元件電連接之具有降低曲率及 或降低熱掛塌性質之外表面之互連係理想的，其係互連之 所欲特性。 5 財考第6圖，依據習知技藝之封裝體包含第-電路板 5 20、第二電路板22、半導體晶片24，其被沈積於第一及第 二電路板20’22之間，且藉由焊料辦電連接至每一電路板 〇’22上之個w導性墊21。如第6圖所示之封裝體亦包含互 連28 ’其可為銅屬，其係經由焊料26等之個別層使第一及 第二電路板2G，22互連。依據第6圖之封裝體之更詳細描述 1〇係顯示於公告美國專利申請案第2004/0119148A1號案，其 係讓渡給本發明之受讓人，且其標的在此被併入以供參考。 依據本發明另一方面，互連28可依據本發明形成。特 別地，翏考第7圖，互連結構η可被使用，以替代依據第G 圖之封裝體中之互連28。 15 現芩考第8圖，於另一實施例，互連19可用於外部廷 接。特別地，互連19可依據本發明方法形成具有連接表面 21。連接表面21係呈自由，以使其能連接至外部表面（諸 如，電路板上之導性墊）。注意於第8圖所示之例子中，第 一半導體組件30及第二半導體組件32亦藉由一層焊料26連 20接至電路板20上之個別導性墊21。半導體組件30,32亦包含 自由連接表面31，33，其較佳係與互連19之連接表面21共平 面。相似於連接表面21，半導體組件30,32之自由連接表面 31，33可用於直接連接電路板之導性墊。例如，自由表面 31，33可製成可焊接。 12 1277162 半導體組件30,32可為動力MOSFET、二極體、IGBT， 或任何其它半導體元件，諸如，控制1C等，且電路板20可 為熱導性電路板，諸如，絕緣金屬基材(1]^3)。需注意於藉 由第8圖所示之實施例，絕緣34可於半導體組件扣，％間及 5半導體組份及互連19間之間隙中形成。絕緣34可由，例如， 來醯亞胺、BCB、以環氧樹脂為主之介電矽聚酯，或有機 聚石夕氧院。 現麥考第9圖，於另一實施例，其相似於第6及7圖所示 之實施例，封裝體可包含於第一電路板2〇上依據本發明形 成之互連19，且第二電路板22可設有可焊接之自由表面 36。可焊接之自由表面36可電連接至半導體組件3〇,32，且 作為用以使半導體組件3〇,32電連接至個別外部元件（諸 如，電路板上之個別導性墊)之外部連接表面。可焊接之自 由表面36可經由傳統上所知之電路板22中之孔洞（未示出） 15等電連接至半導體組件3〇,32。較佳地，可焊接之自由表面 36及互連19之自由連接表面21係共平面，以促進依據第9圖 之封裝體之表面置放。 現參考10及11圖，依據本發明之互連19可於諸如動力 MOSFET 40之半導體元件之電極上形成。特別地，例如， 20互連19可於動_〇SFET4〇之源極42及閘電極料上形成。 依據本發明一方面，數個MOSFET 40可於晶圓形成， 依據本發明糊料可於在晶圓内之動力M〇SFET 4〇之個別電 極上形成，然後，接受加熱而形成互連19。其後，動力 MOSFET 40可藉由，例如，据開或其它傳統方法切單，獲 13 1277162 得個別之動力MODFET，諸如，第10及11圖所示者。因此， 互連19可於動力MOSFET 40封裝前於晶圓水平形成。 其次參考第12圖，動力MOSFET 40依據本發明可依據 另一實施例封裝於導性罐48内。特別地，動力MOSFET 40 5之漏極可電連接至罐48之内表面，形成相似於美國專利第 6,624,522號案（其揭不内容在此被併入以供參考）所揭示之 習知技藝封裝體之新穎之晶片規格之封裝體。 於第一變體中，MOSFET 40包含於MOSFET 40之源極 42上依據本發明形成之互連19,，及無任何鈍化於mosfET 10 40之閘電極44上之互連19”。因此，於動力MOSFET 40之自 由表面（未受互連19’，19”覆蓋之表面）上無鈍化，且如第12 圖所見般’於動力MOSFET 40之端緣與罐48之周圍壁49間 具間隙。需注意MOSFET 40可製成比罐牝之深度更薄，因 為互連19，19之而度可被設計成確保與罐仙之外連接表面 15 51共平面，其被用以使罐48與，例如，·電路板上之導性墊 電連接。降低MOSFET 40之厚度之選擇係有利的，因為其 可降低其ON電阻。 現翏考第13圖，於第二變體中，純化結構观於動力 MOSFET 40之自由表面上形成，其較佳係延伸覆蓋動力 2〇 MOSFET 4〇之端緣及罐48之周圍壁的間之間隙。純化結構 50較佳係自料機聚合物材料形成，諸如，辦氧化物或 石夕/聚醋，其係屬於有機聚魏家族。此等材料之使用因其 高耐溫及财濕性而係有利的。較佳材料係石夕氧環化物、石夕 聚西旨、丙烯酸醋、熱催化劑及紫外線單體部份催化劑之混 14 1277162 合物。自矽環氧化物或矽聚酯形成之鈍化係較佳，因為其 對溶劑及其它化學品之高耐性，且於極少厚度(例如，數微 米）時提供高度之環境及介電防護。 參考第14圖，需瞭解當鈍化結構50形成時，追蹤距離 5 10 15 20 52變成互連19，與鱸仙之最近壁的間之距離。因此，與習知 技蟄封裝體（見第15圖）相比，追蹤矩離52較寬，因為於習知 技蟄封裝體中，追蹤距離52係動力MOSFET之端緣與置於
曰曰片表面上之電極間之距離。追綜距離52之寬度增加能使 罐48與两於χ00v電壓等級之動力M〇SFET(當小罐被使用 日守）及於其它型式之罐時與甚至300V或更高之動力 ET使用。再者，如第12及13圖所示之配置能於低電 裝凡件上容許較大之墊材，其於封裝體被安裝時改良封裝 體之熱特性及QN電阻，且降低焊點之電流密度。
:父佳實施例，於依據第12及13圖之封裝體中之石 系自以作為黏合劑之無錯焊料，及作為填料顆教 乂銀主设之球形或似球狀之鎳顆粒配製之糊料形成。彰 之無錯焊料合金可由麵η、4%α§、π·(以重量計 組成。此外，於較佳實施例，球形鎳顆粒可具有45微雄 千均餘。需注意雖_雛於形狀上係球形，但銀涂 物可使其外表面變不規則。 至少因下 鑛銀之鎳球及以錫·銀為主之焊料之混合物 列原因而係較佳： 以銀塗覆之鎳顆粒獲得 。組成改變造成焊料之 1·焊料合金於回流處理期間自 額外之銀，其改變焊料合金之組成 15 1277162 升高的完全液態溫度，此係有利的，因其係意指焊料於互 連之第二焊接期間不會變成完全液態。因此，互連於藉由 焊料層結合至導性墊後維持其形狀。 2.鎳顆農非常硬且可形成用於強化界面之有效障壁。 5依據本發明之糊料有效地形成聚集物，且因此比基本焊料 (即’黏合劑材料）更能耐彎褶及變形。即，比基本焊料更強。 但是，其易比基本焊料更易脆化，且當推出其彈性範圍外 時會使其主體内之微小破壞增殖。雖然傳統之無鉛焊料易 使應力供應至焊料界面層内，但依據本發明之互連吸收其 10主體内之應力。因此，於許多情況，依據本發明之互連係 作為與其結合之表面之半犧牲層。 依據第12及13圖所示變體之封裝體係先藉由於使動力 MOSFET置於罐48之内表面上前於動力M〇SFET 4〇之個別 電極上形成互連19’，19”而形成。明確地，首先，數個動力 I5 MOSFET 40係於晶圓上形成。其後，互連19,於動力 MOSFET4G之源極42上形成，且互連19，，係於動力m〇SFET 4〇之閘電極44上形成。較佳地，為形成互連，依據 本發明之糊料係經由刻版個別沈積kM〇sfet 4〇之源極42 及閘電極44上。使關版係_種於製造印刷電路板之已知 2〇方法且亦廣泛於在傳統覆晶型元件上形成焊料球。另 外，用以形成依據本發明之互連19,，19，，之糊料可使用能於 $積期間使糊料成形之任何其它方法沈積，諸如，焊料之 ~造或模製。 較佳地，依據本發明處理之晶圓不包含超出一般用於 16 1277162 晶片上之任何鈍化結構圖。但是，此方法不排除已以所有 見7適合之用於製造動力半導體元件之純化作用處理過之 晶圓。 於沈積糊㈣’晶_受_使齡如流。較佳地， 5晶圓於對流回流爐内加熱，其係典型上用於印刷電路板組 件之方法。較佳地’對流爐會進行階段式回流曲線，此使 焊料糊料達完全回流之溫度。此操作可於空氣或氮氣之環 境下實行。 於回流後’會有焊料助溶劑殘質留於晶圓上。狹後， Π)助熔劑殘質較佳係使用超音板清理機移除。用以移除焊料 助溶劑殘質之較佳機器係使用於機器之一側係於液體槽内 且於機器之另-側係維持蒸氣相之適當溶劑。較佳地，焊 料助熔劑殘質之主要部份係於液體槽内移除，且最後清理 係於蒸氣相完成。此方法確保晶圓於清理後具有極少之殘 15留於其上之污染物。第17圖例示於其内具有晶片之晶圓 53，其被製造具有依據本發明之互連19，19，，。 依據本發明之糊料被設計成於其黏合劑已回流後實質 上維持其沈積時之形狀。因此，例如，若用以沈積糊料之 儀器之印刷孔形成具特定高度之立方體時，則黏合劑回流 20後形成之互連維持實質上相似於立方體沈積時之形狀之形 式。需注意於黏合劑回流後不可避免地於形狀具某些改 變。但是，形狀變化不會不利地影響互連之性能。 於晶圓内之動力MOSFET 40具有於其個別^極上形成 之互連19’，19”後，晶圓可使用任何適當之切塊方法切塊， 17 1277162 例如，以標準金剛石刀刀切割或雷射切割。切塊形成個別 之動力MOSFET。 於動力MOSFET 40已切單後，每—者可藉由導性點人 劑（諸如’以銀填充之環氧化物或烊料）電連接至個別罐48 5之内表面而形成封裝體。為實施此步驟，每一個別之動力 MOSFET可藉由自動取放機器拾起，且置於個別_内。 導性黏合劑（例如，以銀填充之環氧化物）可於將動力 MOSFET 4G置於其它前沈積於每_罐内。於將刪断仙 置於罐4納之後，固化步驟被完成以使導性環氧化物固化。 1〇 冑注意傳統取放機之拾起可能需被改良以清除頭連 i9’a9’、除改良之取放頭外，取放步驟可依據傳統已知 術實行。 需注意雖然以銀填充之環氧化物係較佳，但其它材料 (諸如，軟性焊料，或以碳及石墨為主之新賴導性材料)可於 15未偏離林明下被使用。此外，電絕緣之晶片附接材料(諸 如’ ％乳化物或聚醯亞胺）亦可於，例如，導電性係非所欲 時被使用。例如，當動力扣藉由本身或以動力裝置放置於 罐内時，當側動力IC或覆晶動力裝置被使用時，或當數個 牛被放置於共同罐内時，絕緣性晶片附接材料可被用以 2〇使一或多個元件與罐呈電絕緣，但仍利用其熱性質。 士所知般’罐48之目的係用以形成經動力卿 之電流所需之第三連接。此連接一般於此型式之元件中係 必要的’以提供用以導熱及導電之良好路徑。現今，用於 罐之·Μ土材料係銅，但其它金屬亦可被考量。除金屬外， 18 1277162 金屬基質或複合物及碳與石墨材料可被用以形成此連接。 罐48之形式及功能亦可依應用而改變。 依據本發明一方面，罐48包含作為其外精加工面之金 層。此係優於某些其中罐係以銀為精加工之習知封裝體之 5改良。已發現由於離子遷移，罐上之銀會促進罐及其内所 含半導體元件間之樹突物形成，因此造成二者短路及使封 裝體不能操作。以金精加工之罐48避免此一問題。於較佳 貫施例’金精加工可為〇〇5-〇2 um厚，且其可於罐上浸潰 沈積。 1〇 需注意依據第12圖之封裝體係於導性環氧化物固化後 形成。但是’為形成依據實施例13所示變體之封裝體，用 以形成鈍化結構50之材料係經由單針分配、多針分配，或 /主射技術（其係更準確且具變化性之方式）沈積於mdsfet 40之路出部份上。於沈積鈍化材料後，固化步驟被實行以 15 形成鈍化結構50。 需注意純化結構5〇無需終結於罐48之壁49處。相反 地，鈍化結構50可延伸越過壁邮，特別是當喷墨技術被用 以沈積鈍化結構50時。鈍化結構5〇延伸越過 罐48之壁49可 進一步增加追蹤距離。 、、、丁 σ之如第12及13圖所示之製造封裝體之方 法包含下列順序步驟： 以有機水石夕氧烧或另外之適當鈍化作用純化晶圓。 以依據本發明之糊料印刷晶圓。 使晶圓上之糊料回流。 19 1277162 清理助熔劑殘質。 使晶圓切塊。使晶片結合至罐内部。 固化導性黏合劑以附接晶片。 沈積鈍性材料（第二變體)（晶片之端緣，晶片及罐間之 5 間隙，罐之端緣）。 固化鈍化材料（第二變體）。 另外，用於使晶片與罐結合之導性黏合劑可為焊料。 若如此，此方法可包含於焊料回流後之清理步驟。 下列可為用以製造依據本發明之封裝體之另一方法。 10 以有機聚矽氧烷材料，或任何適當鈍化作用鈍化晶圓。 使晶圓切塊。 以導性黏合劑使晶片結合至罐内部。 固化晶片結合黏合劑。 使糊料沈積於晶片表面電極上。 15 使電極上之糊料回流。 清理助熔劑殘質。 沈積有機聚矽氧烷材料（晶片端緣，晶片及罐間之間 隙，罐之端緣）。 固化鈍化結構。 20 另外，用以使晶片與罐結合之導性黏合劑可為焊料。 但是，於此情況，無需額外之助熔劑清理，因為焊料及依 據本發明之糊料係於同一步驟回流。 依據第13圖所示變體之封裝體係比習知技藝之封裝體 (見第15圖）更強，其至少部份係由於凹式晶片之故，其係以 1277162 對於化學性及機械性之損害具高度雜之純化層厚塗覆。 再者，自依據本發明之糊料形成之相對較厚之互連現亦用 以防護晶 >;之接觸區域，即，閘電極及源極。 再者，增加之焊料接觸高度及用以形成依據本發明之 5互連之材料混合，及第二焊接處理，造成熱循環上之改良。 再者，相較於習知技術，用以製造依據第12及13圖所 不變體之封裝體之方法能使用更多種結構材料，其意指現 能使用此間所示且存在於習知技藝之罐48(其不具露出之 銀）製造元件。即，鈍化結構5〇可覆蓋銀，且因而使銀密封 10於封裝體内。再者，當焊料被作為晶片附接材料而替代銀 環氧化物時，銀可被有效地移除。 再者，具有較薄晶片及較大接觸面積能優於習知技藝 而改良ON電阻及熱性能。 此外，晶片厚度無需與罐48之深度相吻合。因此，當 15依據本發明之互連被用以使所有晶片及相關終端結構於相 同板内時，具有與罐48之深度不同之厚度之晶片可被封裝 於如習知技藝所用般相同之罐内。 再者，依據如第13圖所示變體之封裝體於不同電勢之 接觸與區域間獲得較大距離，此容許比習知技藝更高電壓 20之晶片。 額外有利結果係較大面積之晶片現可用於連接，因為 接觸（例如，閘電極及源極）可被移至比習知技藝可能者更接 近晶片端緣。因此，較低之ON電阻可被達成，因為頂金屬 擴散阻性之降低可被實現。更重要，因焊點内之電流密度 21 1277162 而指示之晶片尺寸邊界會被有利地移動。 於另一實施例’互連19之形成可被應用至覆晶型 MOSFET 41之電極’其包含位於相同表面上之漏極與間 電極44及源極42。此—元件之例子係例示於第16圖。需注 5思有利地，覆晶型之動力MOSFET 41亦可於晶圓水平製 造，然後於封裝前單切。 現芩考第18A-B圖，於依據習知技藝之封裝體，晶片之 電極與包路上之導性墊間之連接係經由焊料塊”製得（第 18A圖）。因此，晶片需粗略為罐牝之深度，如此，可與連 10接表面51共平面。因此，晶片厚度係受限於罐48之深度。 另-方面，當依據本發明之互連19，，29，，被使用（第圖）， 罐48之深度不再係-種限制。因此，較薄之晶片可用於依 據本發明之封裝體内。此一特徵使其能使薄晶片（諸如， IGBT晶片）與具習知技藝深度之罐仆一起使用。再者，需注 15意當互連19，，19”被使用時，於晶片與電路板間具較大之托 高。例如，托高可從100微米（焊料塊57作為依據習知技藝 之連接物）改變至2GG微米。托高之增加已發現相較於習知 封裝體係改良封裝體之耐疲勞度。 於另-實施例’互連19，，19”可以自僅其經純化結構5〇 2〇延伸之焊料合金形成之互連替代，因而利用藉由具此間所 述純化結構5G達成之有利性f。所用之烊料合金可為錫-銀 -銅合金(例如，95.5% Sn，3.8% Ag，〇·7% Cu(以重量計)），錫 -銀合金(96% Sn，4% Ag(以重量計），或9〇%如，i〇% Ag(以 重量計)），或高鉛焊料合金(95% Pb，5% Sn(以重量計)）。 22 1277162 雖然已以其相關特殊實施例描述，許多其它變化及改 良與其它用途係熟習此項技藝者可見的。因此，較佳係本 發明並不受限於此間之特殊揭露内容，但僅受限於所附之 申請專利範圍。 5 【圖式簡單說明】 第1及2圖例示依據習知技藝形成焊料凸塊互連之技 術。 第3圖例示以依據本發明之糊料形成之互連之主體之 一部份。 10 第4及5圖例示用以形成依據本發明之互連之技術。 第6圖顯示依據習知技藝之封裝體之截面圖。 第7圖顯示被改質包含依據本發明之互連之封裝體之 第一施例之截面圖。 第8圖顯示包含依據本發明之互連之封裝體之第二實 15 施例之側面圖。 第9圖顯示包含依據本發明之互連之封裝體之第三實 施例之側面圖。 第10圖顯示被改質包含位於其電極上之互連之半導體 晶片之頂平面圖。 20 第11圖顯示第10圖所示半導體晶片以箭頭1M1方向 所見之側平面圖。 第12圖顯示以包含依據本發明形成之互連之半導體晶 片形成之封裝體之第一變體之透視圖。 第13圖顯示以包含依據本發明形成之互連之半導體晶 1277162 片形成之封裝體之第二變體之透視圖。 第14圖顯示第13圖所示封裝體沿14-14線以箭頭方向 所見之截面圖。 第15圖顯示依據習知技藝之封裝體之截面圖。 5 第16圖顯示包含依據本發明形成之互連之覆晶半導體 元件。 第17圖例示含有製得具有依據本發明之互連之晶片之 晶圓。 第18 A圖例示依據習知技藝之封裝體與電路板連接時 10 之截面圖。 第18B圖例示依據本發明之封裝物與電路板連接時之 截面圖。 【主要元件符號說明】 4···· ..導性墊 20····· .第一電路板 5···· ..材料 21····· .導性墊 7…· ..材料 22•…· .第二電路板 10·· ....電路板 24····· .半導體晶片 12.. ....焊料罩 26…·· .焊料 14·· ....導性墊 28•…· .互連 15·· ....焊料糊料 30····· .第一半導體組件 16·· —填料顆粒 32…·· .第二半導體組件 17·· ....焊料凸塊 31,33. .....自由連接表面 18·· ....導電性黏合劑 34····· .絕緣 19·· —彎曲外表面 36····· .自由表面 24 1277162 19，，19, ’……互連 51··· ...外連接表面 40••… .動力 MOSFET 50... …鈍化結構 41••… .覆晶型之動力MOSFET 52... ...追蹤距離 42····· .源極 53··· 44····· .閘電極 57... ...焊料塊 48····· .導性罐 49····· .周圍壁
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Claims (1)

1277162 十、申請專利範圍： 1.一種半導體封裝體，包含： 半導體元件，其具有於其第一表面上之第一電極，於 其相對之第二表面上之第二電極； 5 導性罐，該導性罐包含一内部份及至少一壁，該壁包 含用於外部電連接之外連接表面； 導性黏合劑，其被置於該第一電極及該内部份間，以 使該内部份與第一電極呈電及機械連接，藉此，該半導體 元件被附接至該内部份且與該至少一壁間隔開； 10 導電性互連結構，其係與該第二電極呈電及機械連 接；及 鈍化層，其於該第二電極上形成，且被置於該半導體 元件與該至少一壁間之空間内，其中，該互連係經該鈍化 結構延伸。 15 2.如申請專利範圍第1項之半導體封裝體，其中，該鈍化結 構係包含以矽為主之聚合物。 3. 如申請專利範圍第1項之半導體封裝體，其中，該至少一 壁圍繞該内部份。 4. 如申請專利範圍第3項之半導體封裝體，其中，該罐係包 20 含銅。 5. 如申請專利範圍第1項之半導體封裝體，其中，該罐係包 含銅。 6.如申請專利範圍第1項之半導體封裝體，其中，該半導體 元件係動力MOSFET、二極體，或IGBT。 26 1277162 7. 如申請專利範圍第1項之半導體封裝體，其中，該導性黏 合劑係焊料或導性環氧化物。 8. 如申請專利範圍第1項之半導體封裝體，其中，該互連係 包含藉由導性黏合劑彼此膠黏之導電性顆粒。 5 9.如申請專利範圍第8項之半導體封裝體，其中，該黏合劑 包含焊料。 10. 如申請專利範圍第9項之半導體封裝體，其中，該焊料 包含錫-銀焊料。 11. 如申請專利範圍第10項之半導體封裝體，其中，該錫-10 銀焊料係實質上由99.5% Sn、3.8%銀，及0.7% Cu(以重量 計）所組成之組成物。 12. 如申請專利範圍第9項之半導體封裝體，其中，該焊料 係實質上由95% Sn及5% Sb(以重量計）所組成之組成物。 13. 如申請專利範圍第9項之半導體封裝體，其中，該焊料 15 係高鉛焊料。 14. 如申請專利範圍第9項之半導體封裝體，其中，該焊料 係錫-鉛焊料。 15. 如申請專利範圍第8項之半導體封裝體，其中，該導電 性顆粒係球形。 20 16.如申請專利範圍第8項之半導體封裝體，其中，該導電 性顆粒係立方體狀。 17. 如申請專利範圍第8項之半導體封裝體，其中，該導電 性顆粒係平行六面體。 18. 如申請專利範圍第8項之半導體封裝體，其中，該導電 27 1277162 性顆粒包含銅。 19. 如申請專利範圍第8項之半導體封裝體，其中，該導電 性顆粒係以鎳障壁物電鍍。 20. 如申請專利範圍第8項之半導體封裝體，其中，該導電 5 性顆粒係以錫鈍化。 21. 如申請專利範圍第8項之半導體封裝體，其中，該導電 性顆粒係以銀鈍化。 22. 如申請專利範圍第8項之半導體封裝體，其中，該導電 性顆粒包含錄。 10 23.如申請專利範圍第8項之半導體封裝體，其中，該導電 性顆粒包含錫銀。 24. 如申請專利範圍第8項之半導體封裝體，其中，該導電 性顆粒包含錫-絲。 25. 如申請專利範圍第1項之半導體封裝體，其中，該導電 15 性黏合劑包含該互連總重量之50-58%，且該導電性顆粒包 含該互連總重量之5-40%。 26. 如申請專利範圍第22項之半導體封裝體，其中，該導電 性顆粒尺寸係15 um-65 um。 27. 如申請專利範圍第1項之半導體封裝體，其中，該鈍化 20 係延伸過該至少一壁。 28. —種半導體封裝體，包含： 半導體元件，其具有於其第一表面上之第一電極，於 其相對之第二表面上之第二電極； 導性罐，該導性罐包含一内部份及至少一壁，該壁包 1277162 含用於外部電連接之外連接表面； 導性黏合劑，其被置於該第一電極及該内部份間，以 使該内部份與第一電極呈電及機械連接，藉此，該半導體 元件被附接至該内部份且與該至少一壁間隔開；及 5 導電性互連結構，其係與該第二電極呈電及機械連接； 其中，該互連包含數個導電性顆粒，其係藉由導性黏 合劑膠黏在一起。 29. 如申請專利範圍第28項之半導體封裝體，進一步包含鈍 化層，其於該第二電極上形成，且被置於該半導體元件與 10 該至少一壁間之空間内，其中，該互連係經該鈍化結構延 伸0 30. 如申請專利範圍第29項之半導體封裝體，其中，該鈍化 層延伸過該至少一壁。 31. 如申請專利範圍第29項之半導體封裝體，其中，該鈍化 15 結構包含以矽為主之聚合物。 32. 如申請專利範圍第29項之半導體封裝體，其中，該至少 一壁圍繞該内部份。 33. 如申請專利範圍第28項之半導體封裝體，其中，該罐係 包含銅。 20 34.如申請專利範圍第28項之半導體封裝體，其中，該半導 體元件係動力MOSFET、二極體，或IGBT。 35. 如申請專利範圍第28項之半導體封裝體，其中，該導性 黏合劑係焊料或導性環氧化物。 36. 如申請專利範圍第28項之半導體封裝體，其中，該黏合 29 1277162 劑包含焊料。 37. 如申請專利範圍第28項之半導體封裝體，其中，該焊料 包含錫-銀焊料。 38. 如申請專利範圍第37項之半導體封裝體，其中，該錫-5 銀焊料係實質上由99.5% Sn、3.8%銀，及0.7% Cu(以重量 計）所組成之組成物。 39. 如申請專利範圍第36項之半導體封裝體，其中，該焊料 係實質上由95% Sn及5% Sb(以重量計）所組成之組成物。 40. 如申請專利範圍第36項之半導體封裝體，其中，該焊料 10 係南錯焊料。 41. 如申請專利範圍第36項之半導體封裝體，其中，該焊料 係錫-鉛焊料。 42. 如申請專利範圍第28項之半導體封裝體，其中，該導電 性顆粒係球形。 15 43.如申請專利範圍第28項之半導體封裝體，其中，該導電 性顆粒係立方體狀。 44. 如申請專利範圍第28項之半導體封裝體，其中，該導電 性顆粒係平行六面體。 45. 如申請專利範圍第28項之半導體封裝體，其中，該導電 20 性顆粒包含銅。 46. 如申請專利範圍第28項之半導體封裝體，其中，該導電 性顆粒係以鎳障壁物電鍍。 47. 如申請專利範圍第28項之半導體封裝體，其中，該導電 性顆粒係以錫鈍化。 30 1277162 48.如申請專利範圍第28項之半導體封裝體，其中，該導電 性顆粒係以銀純化。 49. 如申請專利範圍第28項之半導體封裝體，其中，該導電 性顆粒包含鎳。 50. 如申請專利範圍第28項之半導體封裝體，其中，該導電 性顆粒包含錫銀。 51. 如申請專利範圍第28項之半導體封裝體，其中，該導電 性顆粒包含錫-絲。 10 52.如申請專利範圍第28項之半導體封裝體，其中，該導電 性黏合劑包含該互連總重量之50-58%，且該導電性顆粒包 含該互連總重量之5-40%。 53.如申請專利範圍第54項之半導體封裝體，其中，該導電 性顆粒尺寸係15 um-65 um。 54. —種半導體元件，包含： 15 半導體晶片，其具有位於其第一表面上之至少一第一 動力電極及一控制電極；及 互連結構，其係於該動力電極及該控制電極上形成， 該互連結構包含數個導電性顆粒，其係藉由導性黏合劑彼 此膠黏。 20 55.如申請專利範圍第54項之半導體元件，進一步包含位於 該第一表面上之第二動力電極，該第二動力電極進一步包 含互連結構，該互連結構包含數個導電性顆粒，其係藉由 導性黏合劑彼此膠黏。 56.如申請專利範圍第54項之半導體元件，進一步包含位於 31 1277162 該半導體晶片之第二表面上之第二動力電極，及導性罐， 其中，該第二動力電極係與該導性罐之内表面電連接。 57.如申請專利範圍第54項之半導體元件，其中，該黏合劑 包含焊料。 5 58.如申請專利範圍第54項之半導體元件，其中，該焊料包 含錫-銀焊料。
59.如申請專利範圍第58項之半導體元件，其中，該錫-銀焊 料係實質上由99.5% Sn、3.8%銀，及0.7% Cu(以重量計）所 組成之組成物。 10 60.如申請專利範圍第54項之半導體元件，其中，該焊料係 實質上由95% Sn及5% Sb(以重量計）所組成之組成物。 61. 如申請專利範圍第57項之半導體元件，其中，該焊料係 高船焊料。 62. 如申請專利範圍第57項之半導體元件，其中，該焊料係 15 錫-鉛焊料。
63. 如申請專利範圍第54項之半導體元件，其中，該導電性 顆粒係球形。 64. 如申請專利範圍第54項之半導體元件，其中，該導電性 顆粒係立方體狀。 20 65.如申請專利範圍第54項之半導體元件，其中，該導電性 顆粒係平行六面體。 66. 如申請專利範圍第54項之半導體元件，其中，該導電性 顆粒包含銅。 67. 如申請專利範圍第54項之半導體元件，其中，該導電性 32 1277162 顆粒係以鎳障壁物電鍍。 68. 如申請專利範圍第54項之半導體元件，其中，該導電性 顆粒係以錫純化。 69. 如申請專利範圍第54項之半導體元件，其中，該導電性 5 顆粒係以銀鈍化。 70. 如申請專利範圍第54項之半導體元件，其中，該導電性 顆粒包含鎳。
71. 如申請專利範圍第54項之半導體元件，其中，該導電性 顆粒包含錫銀。 10 72.如申請專利範圍第54項之半導體元件，其中，該導電性 顆粒包含錫-秘。 73.如申請專利範圍第54項之半導體元件，其中，該導電性 黏合劑包含該互連總重量之50-58%，且該導電性顆粒包含 該互連總重量之5-40%。 15 74.如申請專利範圍第73項之半導體元件，其中，該導電性
顆粒尺寸係15 um-65 um。 75. —種半導體封裝體，包含： 半導體元件； 罐，其具有該半導體件所在之内部份；及 20 於該罐上之金精加工層。 76. 如申請專利範圍第75項之半導體封裝體，其中，該元件 係動力MOSFET、二極體、IGBT，或動力1C。 77. 如申請專利範圍第75項之半導體封裝體，其中，該元件 係與該罐之該内部份電連接。 33 1277162 78. 如申請專利範圍第75項之半導體封裝體，其中，該金精 加工層之厚度係0.05-0.2 um。 79. —種半導體封裝體，包含： 半導體元件，其具有於其第一表面上之第一電極，於 5 其相對之第二表面上之第二電極； 導性罐，該導性罐包含一内部份及至少一壁，該壁包 含用於外部電連接之外連接表面； 導性黏合劑，其被置於該第一電極及該内部份間，以 使該内部份與第一電極呈電及機械連接，藉此，該半導體 10 元件被附接至該内部份且與該至少一壁間隔開； 導電性互連結構，其係與該第二電極呈電及機械連 接；及 鈍化層，其於該第二電極上形成，且被置於該半導體 元件與該至少一壁間之空間内，其中，該互連係經該鈍化 15 結構延伸。 80. 如申請專利範圍第79項之半導體封裝體，其中，該互連 結構包含焊料。 8L如申請專利範圍第80項之半導體封裝體，其中，該焊料 係由99.5% Sn、3.8%銀，0.7% Cu(以重量計）所組成。 20 82.如申請專利範圍第80項之半導體封裝體，其中，該焊料 係由96% Sn，4% Ag(以重量計）所組成。 83. 如申請專利範圍第80項之半導體封裝體，其中，該焊料 係由90% Sn，10% Ag(以重量計）所組成。 84. 如申請專利範圍第80項之半導體封裝體，其中，該焊料 34 1277162 係由95% Pb，5% Sn(以重量計）所組成。 85. 如申請專利範圍第80項之半導體封裝體，其中，該鈍化 層包含矽環氧化物或矽聚酯。 86. 如申請專利範圍第80項之半導體封裝體，其中，該鈍化 5 層包含矽環氧化物、矽聚酯、丙烯酸酯、熱催化劑，及紫 外線單體部份催化劑。
35
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US7315081B2 (en) 2008-01-01
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WO2005041266A2 (en) 2005-05-06
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US7482681B2 (en) 2009-01-27
US20070284722A1 (en) 2007-12-13

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