TWI267929B - Method for producing an integrated circuit with a rewiring device and corresponding integrated circuit - Google Patents

Method for producing an integrated circuit with a rewiring device and corresponding integrated circuit Download PDF

Info

Publication number
TWI267929B
TWI267929B TW092132458A TW92132458A TWI267929B TW I267929 B TWI267929 B TW I267929B TW 092132458 A TW092132458 A TW 092132458A TW 92132458 A TW92132458 A TW 92132458A TW I267929 B TWI267929 B TW I267929B
Authority
TW
Taiwan
Prior art keywords
carrier
integrated circuit
patterned
rewinding
carrier device
Prior art date
Application number
TW092132458A
Other languages
English (en)
Other versions
TW200425361A (en
Inventor
Harry Hedler
Roland Irsigler
Thorsten Meyer
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of TW200425361A publication Critical patent/TW200425361A/zh
Application granted granted Critical
Publication of TWI267929B publication Critical patent/TWI267929B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Description

1267929 九、發明說明： 本發明係有關具重繞裝置積體電路之製造方法及對應 積體電路。 現今主流晶片尺寸封裝(CSPs)係被建構於預製基板條 上。依據如微球格柵陣列(Tessera婚GA)之基板為基礎之 已知晶片尺寸封裝技術，重繞(重分配線路)或其至少部份 係已被整合入預製基板。呈現於基板上之該重繞係接著藉 由連接線或TAB連接被接觸連接至積體電路或晶片。基板 製造係需增加基板成本之複雜及昂貴處理步驟。再者，製 造及後續處理係以低度平行化，也就是具小於150晶片之平 板或狹條來實施。在此兩者成因係避免進一步降低晶片尺 寸封裝製造成本。扇出重繞亦可藉由基板為基礎之晶片尺 寸封裝技術，如BGA技術來產生。 晶圓位準封裝技術(WLP)同樣地提供製造晶片尺寸封 裝有效成本技術，但不能提供扇出重繞。晶圓位準封裝技 術基本上可使用前端晶圓，其薄膜技術係被用來製造扇入 重繞，如抗銲阻劑層之絕緣層，及焊接球。雖然被用於針 對金屬化，也就是濺鍍及電子沈積，製造，也就是光微影， 及製造保護層，也就是旋轉覆蓋例之此技術步驟係為成本 密集，但每晶片之個別成本可因高度平行化而維持很低(全 部晶圓達1000晶片）。此外，未來更節約成本之印刷技術將 逐漸取代昂貴光微影處理步驟。新印刷技術將可使用該印 刷方法來製造幕罩，其可被用於將接觸墊片高度精確接觸 連接於晶圓上，例如典型接觸墊片間隔包含13〇微米且典型 1267929 墊片開口包含60微米。印刷處理因此可被用於重繞裝置 製造結構觸面板上之絕緣親。然而，_辦封裝^ 術製造不能被用來製造扇出重繞，也就是突出 二 之重繞。 、5璦綠 因此’本發明目的係提供具重繞裝置積體電路之節約 成本方式製造方法及同樣地該積體電路。 、 依據本發明，此目的_由如帽專補_丨 重繞裝置積體電路之製造方法及藉由如中請專利範園^ 項之具重繞裝置積體電路來達成。 本發明概絲礎本質上係包含適#結合晶圓位準 技術及基板為基礎之^尺寸封裝技術處理步驟。因此，、 可避免具魏層之賴餘，重雛置健於晶片尺 裝製造處理_被製造於具高度平行化之簡單，大面積基于 本發明中，上述問題係特別藉由提供 電路之製妨狀較來職，料有町 預定或後續被圖案化切口之載髀 捉仏具 定㈣放置該積體電路至==:之預 :積體電―綱购===: 電路覆蓋之該載體裝置側面，刪除該切 連接裝置；將被圖案化重繞裝置施加至^ 區域。 =;=裝置―__裝置： =化祕柄加至不_被_化抗銲阻継置覆蓋之 此例優點為重繞或部件尚未必須自開端被提供於基板 威載體裝置。此外，扇出設計可行，也就是突出於晶片邊 緣之重繞。再者，載體裝置尺寸可大於如具積體重繞層之 傳統基板。特別是，該尺寸亦大於晶圓面積，係因即使成 本低廉，600公厘χ4〇〇公厘之面板尺寸亦可被實施。再者， 該載體裝置或面板不必如晶圓般圓，而亦可⑽應晶片幾 何方式被形成矩形。 除了這些直接節約成本優點外，本發明亦提供更大自 由選擇可用物質之伽，因域體裝置雜並不限於制式 曰曰片，所以亦可製造具不同型式及尺寸之積體電路或晶片 之俗稱多晶片模組之多晶片單元，並可於處理完成後做類 似已知之晶圓位準測試(WLT)及晶圓位準内建(wlb 晶粒測試及燒入。 本發明各主題之具優點發展及改善係被發掘於申請專 利範圍子項中。 ” 依據一較佳發展，載體裝置係為至少一切口被呈現或 隨後製造其中之印出孔型式之薄膜。 、依據進一步較佳發展，黏著劑係於施加積體電路之前 被施加至載體裝置。 裴置 依據進一步較佳發展，載體裝置係被嵌入如框之嵌 入 依據進一步較佳發展，複數個積體電路係藉由如取置 工具之置放裝置被施加至載體裝置。 依據進一步較佳發展，保護裝置係被施加至載體裝置 1267929 及至少一被施加積體電路之上。 依據進一步較佳發展，保護裝置係以射出成型方法之 印刷處理或灌注處理被施加於及/或被隨後硬化。 依據進-步I^佳發展，聚合物係被施加為絕緣裝置。 依據進-步較佳發展，該縣裝置細光微影處理 或製造。 依據進-步難發展，被_化錄裝置係藉由以下 步驟被施加至該絕緣裝置：施加龍金屬化至該絕緣裝 置，施加及圖案化幕罩於該載體金屬化；施 屬化於不被雜_化幕補蓋之該«金屬聽 移除該轉；及依_導錄道金·_化該載體金屬 1據進-錄佳發展，職黯雜顧顧及/或幕 ^ ί 11_纽卿錄道麵__鍍及/或 /載體盃屬化被以钱刻步驟圖案化。 =f進一步較佳發展’抗銲阻劑裝置係具有聚合物。 據進—步擁發展，抗銲阻舰被印刷。 依據進—步較佳發展，焊接球係以印刷處理圖案化型 η %加且隨紐親，較佳_巾而形成焊接球了 係於•鑛、^魏個積體電路 2坏接球後被分為個別積體電路或積體電路群组。 置汗t，步較佳發展，賴裝置上之複數個具重繞裝 置積體電路胁分隔之_行功紐職。 依據進—步較佳發展，被圖案化重繞裝置係以其外延 1267929 晶片邊緣上之方式來圖案化。 積體電路之 依據進-步較佳發展’較佳具有不同個別 多晶片模組係被形成。 釋於以 本發明實施_被描胁_巾且被更詳 下說明。 圖中，相同參考符號係代表相同或功能性相同組成部 件。 第一圖描提供垂直連續切σ11之細裝置1〇。例 如’載體裝置ίο絲板為馳錢性基板，切口u係以如 模壓孔型式出現。 依據第二圖，具有在此被提供切川之載體裝置^係 被提供黏著劑12於頂侧且被嵌入框13。該框13可具有圓及 角形’且其尺寸僅#由如光微影技術之後續處理步驟要求 來限制。特別是，載體裝置10之尺寸可延伸至晶圓尺寸(2〇〇 公厘，300公厘），但亦超過此。 依據第二圖之後續處理步驟中，積體電路14係以如積 體電路14之接觸墊丨之接觸裝置15被放置於切σ u區域中 之方式被施加及被顛倒放置於黏著劑12被施加之載體裝置 10上。此例中，積體電路14間之距離或切口 11間之距離係 較佳以後續被創造於不被提供黏著劑12之基板薄膜1〇或載 體裝置侧面之重繞層可被侧面導引晶片邊緣上之方式被選 擇。積體電路14可藉由如取置工具之置放裝置來施加及放 置。 依據第四圖，為了保護積體電路14，保護裝置16係較 1267929 ，被提供於積體電賴麵接·印之側面上。因此， 若製造重齡置之前，包含細裝上複數個積體電路 Μ之全部晶肢件適當II由射Λ細方法或另外灌注或印 刷方法被提彳編錄置16，該健裝置隨舰硬化。結果， 可獲得類似晶圓之硬質成分。 '第五圖顯示施加絕緣裝置π於不被提供積體電路14之 載财置聊面上之後之第四難置，無絕、雜置丨7被施 加於載體裝如口 11中之連接裝置15或接觸墊片〔原文如 此〕。較佳為聚合物之絕緣裝置17係被光微影或印刷方法 被施加。 依據第/、圖’重繞裝置18，19係被施加於該絕緣裝置 17上。重繞裝置18，19係具有導電區段18或導體轨道區段 電子、、、巴緣區丰又19 ’導體執道區段18被至少部份接觸連接 至接觸墊片I5。重繞裝置18，19之重繞金屬化係較佳被形 成如下·顧載體麵化絲緣裝置η ;施加及光微影圖 案化幕罩(無®tf); f化學沉積導體執道金屬化W於被賤 、又载體i屬化之未被幕罩覆蓋區域；及以該法働彳被圖案 :匕载體金屬化為導體執道金屬化18。此外，非電導物質D 可破側面提供於導體軌道區段18之間。因此，重繞裝置Μ， 19可藉由薄膜或印刷技術來製造於載體裝置1〇或不被提供 積體電路Η之基減_侧上。 ’、 y進一步方法步驟之後，依據第七圖，抗銲阻劑裝置2〇 係1印刷處理中關案化型式被施加至重繞裝置18，19。 車乂么包含聚合物之該抗銲阻劑裝置20係以切口被提供於重 Ϊ267929 、、 ^ 繞裝f 18，19之導體執道金屬化18之預定區段21上之方式 . 被圖案化。 依據第八圖，銲接球22係較佳以印刷處理被施加於導 體軌羞金屬化18之預定區段21上之抗銲阻劑裝置2〇中之切 口 2卜 依據第九圖裝置中，這些銲接球22係較佳被融化於逆 流爐中，且隨後被冷卻形成銲接球22,。
、遵照第十®，包含複數個積體電路14之晶片成分係被 为為具扇出重繞|置18，19，2Q之分離積體電路23。 依據第十-圖裝置中，係詳細顯示依據本發明方法製 造之分離，體電路23。然而，藉由所述程序之類似預製基 板’也叙具有重繞層例方式，可以高度平行化且可節約 成本來製w之重繞技術係被提供。依據本發明之此技術係 使用晶圓位準封裝技術處理，扇出設計現在亦可行。具重 、凡袭置積體電路23係較佳被制器分隔。
雖然本發明已在較佳實施織礎上作以上說明 ，但並 不限於此而可以多樣修改。 口此特別是已解釋物質(聚合物··.)係被視為例證。 再者’重繞裝置 18, 1Q，〇m一一·一 . . . . 12 1267929 【圖式簡單說明】 第一至十圖顯示具重繞裝置積體電路製程中之各階 段以解釋本發明實施例之橫斷面圖。 第十一圖顯示具重繞裝置積體電路以放大圖示解釋 本發明實施例之横斷面圖。 【主要元件符號說明】 ίο載體裝置 12黏著劑 14積體電路 16保護裝置 18傳導裝置 20抗銲阻劑裝置 11、71'焊接球 11 切口 13框 15連接裝置 17絕緣裝置 19非傳導裝置 21 區段/切口 23分離積體電路 13

Claims (1)

1267929 十、申請專利範圍： L一種具重繞裝置(18，19)積體電路(23)之製造方法，具有 以下步驟： k供具預定或隨後圖案化切口（11)之載體裝置(1〇) · 以該載體裝置(10)之該預定切口（11)被放置該積體 電路(14)至少一連接裝置(15)上之方式將至少一該積體 電路(14)顛倒施加至該載體裝置(1〇); 將絕緣裝置(17)施加至不被該積體電路(14)覆蓋之 该載體裝置(10)側面，刪除該切口（11)中該至少_連接果 置(15); " 將該被圖案化重繞裝置(18，19)施加至該絕緣裝置 (17)； " 將被圖案化抗銲阻劑裝置(20)施加至該被圖案化重 繞裝置(18，19);及 將被圖案化焊接球(22)施加至不被該被圖案化抗銲 阻劑裝置(20)覆蓋之該重繞裝置(18)之區段pi)。 2·如申請專利範圍第1項之方法，其特徵為該載體裝置(1〇) 係為其中至少一切口（11)被呈現印出孔型式之薄膜。 3·如申請專利範圍第1或2項之方法，其特徵為黏著劑(12) 係於施加該積體電路(14)之前被施加至該載體裝置(1〇)。 4·如申請專利範圍第1項之方法，其特徵為該載體裝置(1〇) 係被嵌入如框之嵌入裝置(13)。 5·如申請專利範圍第1項之方法，其特徵為複數個積體電路 (14)係藉由如取置工具之置放裝置被施加至該載體裝置 14 (10)。 1267929 6·如申請專利範圍第1項之方法，其特徵為保護裝置(16)係 被施加至該載體裝置(10)及被施加之至少一積體電路(14) 之上。 7·如申凊專利範圍第6項之方法，其特徵為該保護裝置(16) 係以射出成型方法或另外灌注或印刷處理被施加及/或 隨後部份或全部被硬化。 8·如申請專利範圍第1項之方法，其特徵為聚合物係被施加 為該絕緣裝置(17)。 9·如申凊專利範圍第1項之方法，其特徵為該絕緣裝置(17) 係以光微影處理來印刷或製造。 10·如申請專利範圍第1項之方法，其特徵為該被圖案化重 繞裝置（18，19)係藉由以下步驟被施加至該絕緣裝置 (17)： 知*加載體金屬化至該絕緣裝置(17); 施加及圖案化幕罩於該載體金屬化； 上施加導體軌道金屬化於不被該被圖案化幕罩覆蓋 之該載體金屬化區域中； 移除該幕罩；及 依據4導體軌道金屬化結構圖案化該載體金屬化。 ★申明專利範㈣陶之方法，其特徵為該載體金屬化 係被截錄及/或幕罩被光微影圖案化及/或導體軌道金屬 化(18)被化學電鑛及/或該載體金屬化被以飿刻步驟 化。 ’、 15 1267929 士申明專利圍弟1項之方法，其特徵為該抗焊阻劑裝 置(20)係具有聚合物。 ^ 13.如申請專利範圍第丨項之方法，其特徵為該抗銲阻劑裝 置(20)係被印刷。 14·如申請專利範圍第丨項之方法，其特徵為該焊接球(22) 係以印刷處理圖案化型式被施加且隨後被融化，較佳於 逆流爐中。 15.如申請專利範圍第丨項之方法’其特徵為該載體裝置(1〇) 上之複數個積體電路(14)係於施加該焊接球(22)後被分 為個別積體電路(23)或積體電路群組(24)。 16·如申請專利麵第15項之方法，其特徵為該載體裝置 (10)上之複數個具重繞裝置(18，19)積體電路(14，23)係 於分隔之前進行功能性測試。 R如申請專利範圍第旧之方法，其特徵為該被圖案化重 繞裝置(18, 19)係以其侧向延伸超出該積體電路⑽之方 式來圖案化。 18·如申請專利範圍第！項之方法，其特徵為較佳具有不同 個別積體電路之多晶片模組係被形成。 19·一種具重繞裝置(18，19)積體電路(23)，具有： 具預定或隨後圖案化切口⑴)之载體裝置⑽； 以该載體裝置(10)之該預定切口（11)被放置該積體 電路(1句至少-連接裝置⑼上之方式顛倒於該載體裝 置(10)之至少一該積體電路(14); 不被該積體電路(Η)覆蓋之該載體裝置⑽側面上 16 1267929 =巴緣I置(17)，刪除該切口⑼中該至少—連接襄置 圖案化重繞裝置(18, 19); ，19)上之被圖案化抗銲阻 该絕緣裝置(17)上之該被 该被圖案化重繞裝置(18 劑裝置(20);及 不被該被圖案化抗銲阻劑裝置⑽覆蓋之該重繞裝 置(18)之區段(21)上之焊接球(22)。 17 1267929 七、指定代表圖： (一) 本案指定代表圖為：第（11 )圖。 (二) 本代表圖之元件符號簡單說明： 10載體裝置 12黏著劑 14積體電路 15連接裝置 16保護裝置 17絕緣裝置 18傳導裝置 19非傳導裝置 20抗銲阻劑裝置 22’ 被融化焊接球 23分離積體電路 八、本案若有化學式時，請揭示最能顯示發明特徵的 化學式：
TW092132458A 2002-11-29 2003-11-19 Method for producing an integrated circuit with a rewiring device and corresponding integrated circuit TWI267929B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10255844A DE10255844B3 (de) 2002-11-29 2002-11-29 Verfahren zur Herstellung einer integrierten Schaltung mit einer Umverdrahtungseinrichtung und entsprechende integrierte Schaltung

Publications (2)

Publication Number Publication Date
TW200425361A TW200425361A (en) 2004-11-16
TWI267929B true TWI267929B (en) 2006-12-01

Family

ID=32518813

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092132458A TWI267929B (en) 2002-11-29 2003-11-19 Method for producing an integrated circuit with a rewiring device and corresponding integrated circuit

Country Status (7)

Country Link
US (1) US7074649B2 (zh)
JP (1) JP4118791B2 (zh)
KR (1) KR100574197B1 (zh)
CN (1) CN1235277C (zh)
DE (1) DE10255844B3 (zh)
SG (1) SG116512A1 (zh)
TW (1) TWI267929B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI381496B (zh) * 2009-01-23 2013-01-01 Everlight Electronics Co Ltd 封裝基板結構與晶片封裝結構及其製程

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100392845C (zh) * 2004-11-12 2008-06-04 日月光半导体制造股份有限公司 在基板和封装胶体间具有高粘着性的封装结构
US7599485B2 (en) * 2005-06-24 2009-10-06 Cisco Technology, Inc. Communications system employing single-pair identity circuit for remotely powered device
US8093722B2 (en) * 2008-05-27 2012-01-10 Mediatek Inc. System-in-package with fan-out WLCSP
US8310051B2 (en) 2008-05-27 2012-11-13 Mediatek Inc. Package-on-package with fan-out WLCSP
US7838975B2 (en) * 2008-05-27 2010-11-23 Mediatek Inc. Flip-chip package with fan-out WLCSP
US20100213588A1 (en) * 2009-02-20 2010-08-26 Tung-Hsien Hsieh Wire bond chip package
US20100213589A1 (en) * 2009-02-20 2010-08-26 Tung-Hsien Hsieh Multi-chip package
JP5469546B2 (ja) 2010-06-22 2014-04-16 株式会社ジェイデバイス 半導体装置の製造方法
JP5606243B2 (ja) 2010-09-24 2014-10-15 株式会社ジェイデバイス 半導体装置の製造方法
JP6238121B2 (ja) * 2013-10-01 2017-11-29 ローム株式会社 半導体装置
WO2015156075A1 (ja) 2014-04-07 2015-10-15 日本電気硝子株式会社 支持ガラス基板及びこれを用いた積層体
TWI556359B (zh) * 2015-03-31 2016-11-01 南茂科技股份有限公司 四方扁平無引腳封裝結構與四方扁平無引腳封裝導線架結構
CN109640521B (zh) 2018-11-20 2020-06-30 奥特斯科技(重庆)有限公司 制造具有嵌入式集群的部件承载件的方法以及部件承载件

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19702014A1 (de) * 1996-10-14 1998-04-16 Fraunhofer Ges Forschung Chipmodul sowie Verfahren zur Herstellung eines Chipmoduls
US6140707A (en) * 1998-05-07 2000-10-31 3M Innovative Properties Co. Laminated integrated circuit package
JP3446825B2 (ja) * 1999-04-06 2003-09-16 沖電気工業株式会社 半導体装置およびその製造方法
DE19960249A1 (de) * 1999-12-14 2001-07-05 Infineon Technologies Ag Verfahren zur Herstellung eines Halbleiterbausteins
JP3596864B2 (ja) 2000-05-25 2004-12-02 シャープ株式会社 半導体装置
DE10138042A1 (de) * 2001-08-08 2002-11-21 Infineon Technologies Ag Elektronisches Bauteil und Verfahren zu seiner Herstellung

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI381496B (zh) * 2009-01-23 2013-01-01 Everlight Electronics Co Ltd 封裝基板結構與晶片封裝結構及其製程
US8513820B2 (en) 2009-01-23 2013-08-20 Everlight Electronics Co., Ltd. Package substrate structure and chip package structure and manufacturing process thereof

Also Published As

Publication number Publication date
KR20040048351A (ko) 2004-06-09
CN1505126A (zh) 2004-06-16
US20050014309A1 (en) 2005-01-20
CN1235277C (zh) 2006-01-04
SG116512A1 (en) 2005-11-28
JP4118791B2 (ja) 2008-07-16
US7074649B2 (en) 2006-07-11
JP2004186688A (ja) 2004-07-02
KR100574197B1 (ko) 2006-04-27
DE10255844B3 (de) 2004-07-15
TW200425361A (en) 2004-11-16

Similar Documents

Publication Publication Date Title
US10770350B2 (en) Method of separating a back layer on a singulated semiconductor wafer attached to carrier substrate
TWI539508B (zh) 半導體裝置之製造方法及電子裝置之製造方法
TWI267929B (en) Method for producing an integrated circuit with a rewiring device and corresponding integrated circuit
US7772691B2 (en) Thermally enhanced wafer level package
CN100375232C (zh) 半导体器件及其制造方法
TWI296139B (zh)
US20150008566A1 (en) Method and structure of panelized packaging of semiconductor devices
US20090189279A1 (en) Methods and systems for packaging integrated circuits
KR20150104467A (ko) 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
US11289396B2 (en) Sensing component encapsulated by an encapsulation layer with a roughness surface having a hollow region
US11842902B2 (en) Semiconductor package with alignment mark and manufacturing method thereof
TW200539465A (en) Chip heat sink device and method
US8030138B1 (en) Methods and systems of packaging integrated circuits
US10636757B2 (en) Integrated circuit component package and method of fabricating the same
US20240153769A1 (en) Method for fabricating a chip package
KR20220050121A (ko) 임베딩된 코어 프레임을 사용하는 패키지의 휨 제어
JP2004103738A (ja) 半導体装置及びその製造方法
US20230299027A1 (en) Structure and method for semiconductor packaging
US20230197662A1 (en) Package
TW466652B (en) Wafer level package and its process thereof
US20200035629A1 (en) Packaged semiconductor device and method for preparing the same
TW200924132A (en) Thinning method for fabricating dies arrangement package structure
TW200416850A (en) Semiconductor device
JPH09129524A (ja) 半導体装置の製造方法
TW202226395A (zh) 半導體封裝以及其製造方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees