SG116512A1 - Method for producing an integrated circuit with a rewiring device and corresponding integrated circuit. - Google Patents

Method for producing an integrated circuit with a rewiring device and corresponding integrated circuit.

Info

Publication number
SG116512A1
SG116512A1 SG200306982A SG200306982A SG116512A1 SG 116512 A1 SG116512 A1 SG 116512A1 SG 200306982 A SG200306982 A SG 200306982A SG 200306982 A SG200306982 A SG 200306982A SG 116512 A1 SG116512 A1 SG 116512A1
Authority
SG
Singapore
Prior art keywords
integrated circuit
producing
patterned
rewiring device
insulator
Prior art date
Application number
SG200306982A
Other languages
English (en)
Inventor
Hedler Harry
Irsigler Roland
Meyer Thorsten
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of SG116512A1 publication Critical patent/SG116512A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
SG200306982A 2002-11-29 2003-11-26 Method for producing an integrated circuit with a rewiring device and corresponding integrated circuit. SG116512A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10255844A DE10255844B3 (de) 2002-11-29 2002-11-29 Verfahren zur Herstellung einer integrierten Schaltung mit einer Umverdrahtungseinrichtung und entsprechende integrierte Schaltung

Publications (1)

Publication Number Publication Date
SG116512A1 true SG116512A1 (en) 2005-11-28

Family

ID=32518813

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200306982A SG116512A1 (en) 2002-11-29 2003-11-26 Method for producing an integrated circuit with a rewiring device and corresponding integrated circuit.

Country Status (7)

Country Link
US (1) US7074649B2 (zh)
JP (1) JP4118791B2 (zh)
KR (1) KR100574197B1 (zh)
CN (1) CN1235277C (zh)
DE (1) DE10255844B3 (zh)
SG (1) SG116512A1 (zh)
TW (1) TWI267929B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11189500B2 (en) 2018-11-20 2021-11-30 AT&S (Chongqing) Company Limited Method of manufacturing a component carrier with an embedded cluster and the component carrier

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100392845C (zh) * 2004-11-12 2008-06-04 日月光半导体制造股份有限公司 在基板和封装胶体间具有高粘着性的封装结构
US7599485B2 (en) * 2005-06-24 2009-10-06 Cisco Technology, Inc. Communications system employing single-pair identity circuit for remotely powered device
US8093722B2 (en) * 2008-05-27 2012-01-10 Mediatek Inc. System-in-package with fan-out WLCSP
US8310051B2 (en) 2008-05-27 2012-11-13 Mediatek Inc. Package-on-package with fan-out WLCSP
US7838975B2 (en) * 2008-05-27 2010-11-23 Mediatek Inc. Flip-chip package with fan-out WLCSP
TWI381496B (zh) 2009-01-23 2013-01-01 Everlight Electronics Co Ltd 封裝基板結構與晶片封裝結構及其製程
US20100213588A1 (en) * 2009-02-20 2010-08-26 Tung-Hsien Hsieh Wire bond chip package
US20100213589A1 (en) * 2009-02-20 2010-08-26 Tung-Hsien Hsieh Multi-chip package
JP5469546B2 (ja) 2010-06-22 2014-04-16 株式会社ジェイデバイス 半導体装置の製造方法
JP5606243B2 (ja) 2010-09-24 2014-10-15 株式会社ジェイデバイス 半導体装置の製造方法
JP6238121B2 (ja) * 2013-10-01 2017-11-29 ローム株式会社 半導体装置
WO2015156075A1 (ja) 2014-04-07 2015-10-15 日本電気硝子株式会社 支持ガラス基板及びこれを用いた積層体
TWI556359B (zh) * 2015-03-31 2016-11-01 南茂科技股份有限公司 四方扁平無引腳封裝結構與四方扁平無引腳封裝導線架結構

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19702014A1 (de) * 1996-10-14 1998-04-16 Fraunhofer Ges Forschung Chipmodul sowie Verfahren zur Herstellung eines Chipmoduls
US6140707A (en) * 1998-05-07 2000-10-31 3M Innovative Properties Co. Laminated integrated circuit package
DE19960249A1 (de) * 1999-12-14 2001-07-05 Infineon Technologies Ag Verfahren zur Herstellung eines Halbleiterbausteins
JP2001332653A (ja) * 2000-05-25 2001-11-30 Sharp Corp 半導体装置
DE10138042A1 (de) * 2001-08-08 2002-11-21 Infineon Technologies Ag Elektronisches Bauteil und Verfahren zu seiner Herstellung

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3446825B2 (ja) * 1999-04-06 2003-09-16 沖電気工業株式会社 半導体装置およびその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19702014A1 (de) * 1996-10-14 1998-04-16 Fraunhofer Ges Forschung Chipmodul sowie Verfahren zur Herstellung eines Chipmoduls
US6140707A (en) * 1998-05-07 2000-10-31 3M Innovative Properties Co. Laminated integrated circuit package
DE19960249A1 (de) * 1999-12-14 2001-07-05 Infineon Technologies Ag Verfahren zur Herstellung eines Halbleiterbausteins
JP2001332653A (ja) * 2000-05-25 2001-11-30 Sharp Corp 半導体装置
DE10138042A1 (de) * 2001-08-08 2002-11-21 Infineon Technologies Ag Elektronisches Bauteil und Verfahren zu seiner Herstellung

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11189500B2 (en) 2018-11-20 2021-11-30 AT&S (Chongqing) Company Limited Method of manufacturing a component carrier with an embedded cluster and the component carrier

Also Published As

Publication number Publication date
KR20040048351A (ko) 2004-06-09
CN1505126A (zh) 2004-06-16
US20050014309A1 (en) 2005-01-20
CN1235277C (zh) 2006-01-04
JP4118791B2 (ja) 2008-07-16
US7074649B2 (en) 2006-07-11
TWI267929B (en) 2006-12-01
JP2004186688A (ja) 2004-07-02
KR100574197B1 (ko) 2006-04-27
DE10255844B3 (de) 2004-07-15
TW200425361A (en) 2004-11-16

Similar Documents

Publication Publication Date Title
MY128015A (en) Multilayer printed circuit board and multilayer printed circuit board manufacturing method
EP1041633A4 (en) SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD, PRINTED CIRCUIT BOARD, ELECTRONIC DEVICE
SG116512A1 (en) Method for producing an integrated circuit with a rewiring device and corresponding integrated circuit.
SG81960A1 (en) Semiconductor device, substrate for a semiconductor device, method of manufacture thereof, and electronic instrument
EP1107306A4 (en) SEMICONDUCTOR HOUSING, SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR HOUSING
WO2000054322A8 (en) Flip chip with integrated flux and underfill
CA2340677A1 (en) Semiconductor package, semiconductor device, electronic device, and method for producing semiconductor package
WO2003063248A8 (en) Semiconductor die package with semiconductor die having side electrical connection
WO2003015165A3 (de) Elektronisches bauteil mit einem kunststoffgehäuse und verfahren zu seiner herstellung
SG84587A1 (en) Semiconductor device and method of formation
WO2002027786A1 (fr) Element semi-conducteur, procede de fabrication d'un element semi-conducteur, carte a circuit imprime multicouche, et procede de fabrication d'une carte a circuit imprime multicouche
HK1095208A1 (en) Semiconductor device and method of fabricating thesame
WO2005013339A3 (en) Methods of forming conductive structures including titanium-tungsten base layers and related structures
FR2840711B1 (fr) Carte de circuit integre et procede de fabrication de celle-ci
EP1915040A3 (en) Printed wiring board and printed wiring board manufacturing method
WO2002067326A3 (en) Integrated circuit die having an electromagnetic interference shield
TW200512843A (en) Thermoplastic fluxing underfill composition and method
WO2003017324A3 (en) Structure and method for fabrication of a leadless chip carrier with embedded inductor
EP1814370A4 (en) CIRCUIT BOARD AND METHOD FOR ITS DESIGN AND DESIGN METHOD FOR A IC CAPSULE CONNECTION AND CONNECTING METHOD THEREFOR
TW200629512A (en) Non-circular via holes for bumping pads and related structures
MY131914A (en) Electronic assembly having composite electronic contacts for attaching a package substrate to a printed circuit board
TW200504952A (en) Method of manufacturing semiconductor package and method of manufacturing semiconductor device
WO2006008701A3 (en) Assembly and method of placing the assembly on an external board
CA2409912A1 (en) Improvements in grounding and thermal dissipation for integrated circuit packages
WO2004044984A3 (en) Chip-scale schottky device