TW466652B - Wafer level package and its process thereof - Google Patents

Abstract

The present invention includes polishing the wafer backside by a grinder. Subsequently, a glass is laminated on the wafer backside surface by using epoxy. Then, the wafer is etched to isolate the dies. An epoxy is then coated on the wafer by means of vacuum coating process. Then, a curing step is performed by using the ultraviolet (UV) radiation to harden the epoxy. A grinding process is optional used to grind the epoxy on the wafer circuit side. A plurality of pad openings is formed in the epoxy. Subsequently, a pad circuit re-distribution is arranged over the upper surface of the epoxy. A solder mask covers the epoxy and the pad circuit for isolation. A printing process is carried out to print solder on the pre-determined area and the solder contacts to the pad circuit. Then, the solder is re-flow, and the wafer is then set to a testing apparatus for wafer level testing. A sawing process is next performed after the wafer-level test to separate the dice by cutting the scribe line, thereby obtaining the chip scale package (CSP).

Description

4 6 665 2 V. Description of the invention (1) Field of the invention: The present invention relates to packaging technology, especially county packaging technology.疋 Background of the Invention: With the rapid evolution of semiconductor technology and the trend of faster 1 + functions, the more I c semiconductors have become, the more the density becomes 1 ¾. Faster and faster, so that the package's heat dissipation effect is improved, so the sealing structure usually sealed individually in plastic or ceramic material must be able to protect the chip and dissipate the chip. Traditional packaging is also used as a pre-chip The package is getting smaller and smaller to meet the current trend. The package also breaks through with the development of ball matrix array packaging technology (ba J for short BGA package) technology. The package tends to use the ball matrix array package. The / 0 pin is spherical and has a shorter distance and is less susceptible to damage and deformation. Its short sealing distance and fast speed can meet current and future numbers. There are already many different types of semiconductor types. The number of I / 0 of packaged products in thin, short, and multi-body not only increases the number of pins, but also the component power consumption becomes more and more important. Inside the semiconductor wafer. It is used for the thermal function test during the package operation. The goal is a high number of I / 0 1 grid arrays; below, therefore, IC semiconductor technology (BGA). The electrical transmission of the BGA structured L-line structured components and the fine-grained components requires the speed of the system. Encapsulation, no matter what kind

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-A-S ~ Sl6l5l_2- V. Description of the invention (2) Most types of packages are pushed and projected. Station 2 a The package is first cut into individuals and then installed in the lamp. However, the wafer is a pad, which is assembled by ^ 1, a trend of packaging into a semiconductor package (, 'will be described below. See Figure 1. A plurality of dies 4 form the surface of the conductor wafer 2, and a glass 8 uses Adhesion is attached to the surface of the sun. Then, the side without grains will be ground to reduce its thickness, which is usually called back grind (back gr 1 η 1 ng), as shown in Figure 1. Then the 'wafer is etched to separate] c and. The adhesive substance 6 of the hafnium will be exposed, see Fig. 3. Please refer to Fig. 4.' Another glass 1 2 is attached to the substrate with a grain The next step is shown in Figure 5. A film layer 14 is formed on the first glass 8, and then the first glass 8 and silver are etched into the part of the adhesive substance 8, 10. As shown in Figure 26, it is commonly referred to as a notch process, so a trench 16 is formed in the glass 8 and the adhesive materials 6, 10, and the 'tin ball will be formed on the film layer 14 in a subsequent process. The film layer 18 composed of solder will be patterned on the surface of the first glass 8 ' And along the surface of the trench 16 to provide electrical connection, the film layer 18 also covers the film layer 14, as shown in Figure 7. Referring to Figure 8, a solder paste mask 20 is then formed on the surface of the solder film layer 18. And the glass 8 to expose the surface corresponding to the film layer 14, see FIG. 9 and FIG. 10, the solder ball 22 is then planted on the solder film exposed by the solder paste mask 20 using the traditional ball-planting technique .. Layer 18 surface, the next step is to perform a cutting process to penetrate the glass 12 through the trench 14 to leave the crystal 12 to separate the crystal grains, as in the prior art, in this step

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Zt 6 66 5 2 Jade, the invention said / (3) before the application J a 丨 cutting tape 2 4 first attached to the second glass 0 and »the above process is too complicated j it requires cutting σ process and cutting The first glass step is used to separate the crystal grains. In addition, it includes forming the steep slope of the trench sloping surface J. The solder formed thereon will not easily adhere and lead to an open circuit. Therefore, the quality performance of the device will be reduced. The purpose of the present invention is to provide a package having a true chip size. Another aspect of the present invention is to provide a low manufacturing cost and to disclose a wafer type package and its manufacturing process. Another aspect of the present invention—which is to provide—is applicable to wafer type testing (wafer [eve te. St) Wafer type packaging > Facilitate wafer type collapse test and other tests. Burn-in test selects early failure products for heating life test □-Use the wafer back first --Grinding device grinding Before performing this step 9 Wafer tape is attached to the front side of the wafer and removed after grinding. A glass is attached to the back side of the wafer. 3 Suitable materials include, but are not limited to ring For epoxy resin, the glass can be attached using the conventional attachment technology. After m, a photoresist with a specific pattern is used as the engraved mask J 4k. The above wafer is used to separate 1C 0. The best Photoresist The opening σ corresponds to the scribe line (scrit) e 1 i ne) on the wafer to expose the scribe line 0 • m. The adhesive substance has a thickness of 1 to 2 mi 1 and is coated on the second side of the wafer. 3 It is best to use Vacuum coating process? Adhesive substance can be epoxy resin

Page 8 d 6 665 2 --- ~~~~ -_ V. Description of the invention (4) —-~ 丄 er ^ yr This step is similar to the principle of the existing tape, and its improvement is applied to 苴, the protective layer . This vacuum coating process can prevent bubble formation. I W ^ ^ epoxy resin (ePOxy) will fill the trench. A cured _t 1 is irradiated with ultraviolet rays or heat-treated to harden the above-mentioned epoxy tree. The grinding process can be selectively used to grind the epoxy resin (ep. xy) ◊ plural 成 / in I in the adhesive substance and corresponding to the pad on the die fPad) 'Then, the circuit redistributes the circuit contact pads provided on the surface of the epoxy' to establish electrical Sexual connection. A solder paste mask serves as an insulation. The solder paste mask exposes a specific area of the circuit, and the exposed area of the circuit is the area where the conductor ball is intended to be placed. A printing process is used to coat tin on the above-mentioned specific area. 1 Hou Chau heat flow process turns the solder paste into a solder ball. The wafer type package of the present invention includes: a crystal having a plurality of crystal grains formed thereon. A circle, wherein the wafer has a trench formed on the dicing path, a material is attached to the back of the wafer with a first adhesive material, a second adhesive material is located on the plurality of dies and fills the trench, The plurality of grains have a plurality of pads formed thereon, a circuit layout is formed on the second adhesive material, and a plurality of pads are connected to each other, and a solder ball cover covers the circuit layout and the second adhesive material. , And the circuit layout and solder ball of the exposed part are formed on the exposed part and the connection ^ circuit layout "

4 6 66 5 2 V. Description of the invention (5) Detailed description of the invention: The present invention discloses a wafer type package and a method for manufacturing the wafer type package. The detailed description is as follows. The preferred embodiment described is only one description. It is not intended to limit the present invention. Referring to FIG. 1, a wafer back surface (or a first surface) is first polished by a grinding device. Before performing this step, a wafer tape is attached to the front surface of the wafer 5 and attached. Remove a material such as glass before removing it. In a preferred embodiment, the thickness of the wafer 5 after grinding is about 6-8 m i 1. Next, a material 3 such as glass is attached to the back of a wafer having a plurality of crystal grains formed on it. Suitable materials include, but are not limited to, epoxy resin (e ρ ο X y). Adhesive technology for attaching, it is preferable that the thickness of glass 1 is about 1-2 mi 1, the actual thickness is related to other parameters of the manufacturing process. Quartz or ceramic can replace glass 1. The material used in the attaching process is better if it has a thermal expansion coefficient close to the wafer. Generally, the thermal expansion coefficient of Shi Xi is about 3 cm / cm / ° C, and the thermal expansion coefficient of glass is about 3-5 cm / cm / ° C. Then, a photoresist (not shown) with a specific pattern is used as an etching mask, and the wafer is etched to separate the IC. The best condition is that the photoresist opening corresponds to the scribe line on the wafer (s c r i b e 1 i n e) to expose the scribe line 7. Then, the wafer is etched by wet etching so that the trench formed in this step has a slope, which can be obtained by controlling the etching recipe using traditional etching techniques.

Page 10 4 6 665 2 V. Description of the invention (6) Refer to FIG. 11 to FIG. 13 'A cohesive substance u has a thickness of 2fllil and is applied on the second side of the wafer 5' is best to use vacuum coating In the manufacturing process, the adhesive substance 11 can be epoxy resin (ep0Xy). This step is similar to the principle of the existing tape, and it is applied to the protective layer on the wafer surface. This vacuum coating process can prevent bubbles from being formed therein, and epoxy resin (epoxy) will be filled into the trench 9. A curing step may use ultraviolet irradiation or heat treatment to harden the i-coating oxygen resin (e P 0 χ y). A lapping process can optionally be used to grind epoxy on the surface of the wafer with the circuit side. A plurality of openings 15 are formed in the adhesive substance 1 1 and correspond to Pd 1 3 'on the crystal grains. Of course, these I 3 will be exposed. It must be noted that epoxy The laser is a light-transmissive material, so the alignment mark on the cutting track will not be covered by epoxy resin (epoxy). In other words, the ' alignment marks are visible to subsequent alignment devices. In addition, the adhesive substance 11 must have flowability and resistance to moisture. Then, the conductive path layout or the pad circuit is redistributed and disposed on the surface of the epoxy 11 as shown in FIG. 14. The circuit 17 may be made of a conductive material such as a metal or an alloy, and preferably a Cr-Cu alloy. Part of the circuit Π contacts the pads 13 to establish an electrical connection. Still see Figure 14, a solder paste curtain! 9 covers the circuit 1 7 as an insulation and

46 665 2 V. Explanation of jealousy (7) The solder mask 19 exposes the specific area of the circuit 17, and the area where the circuit 17 is exposed is the area where the conductor ball is intended to be placed. A printing process is used to apply the solder paste 21 to the above specific areas. Then, the heat flux process is used to change the solder paste into solder balls. The temperature of the heat flux can use the known process temperature. See Figure 15 for details. The semiconductor die 5 will be coupled to the above-mentioned solder balls 21, and the solder balls can be fabricated by known BGA technology. The preferred solder balls are arranged in an array, and the solder balls are connected to the above circuit to establish electrical connection. Then, the wafer is transferred to a wafer type testing device for wafer type testing, such as a burst test (bur η-i η). After the wafer type measurement is completed, the wafer is cut to separate individual crystals. grain. The dicing process mainly cuts along the dicing path to obtain a wafer size package (c h i p s c a 1 e p a c k a g e, CSP). The following table is a comparison of wafer type wafer level package (wafer level CSP) and wafer type wafer level package (chip level CSP). The present invention has been described above with reference to the preferred embodiments, and those skilled in the art can make some modifications without departing from the spirit of the present invention. The scope of patent protection should be regarded as the scope of the attached patent application and its equivalent. Field-specific.

Page 12 E) Table 1 Wafer Type CSP Wafer Type CSP Package with whole wafer (Whole Individual wafer packaging Chip packaging) Maximum size to die boundary (Max Max size: die Size + percent (size size to die street) Twenty (Max size: die size USD 0.1 to 0.5 +20 percentage per pin) (Economy of scale 0.1 to 0,5 cent / lead) US $ 1 to 5 cents' Costly 1 to 5 cent / lead) 1 · Β1 Page 13 A6665 2 丨 _ 5. Description of the invention (9) 6 kg 6% 2% of the wafer type packaging of the present invention and other technologies Comparison. Table II Crystal® CSP Tessera (micro- BGA ^ Ricid laminate cost (its gold content / 4 — Ϊ 神 Ϊ Λ 面 翌 ΰ): Dornier «α is less than 0.5 its gold content / each jewel« other product package: large钤 1 its gold content / each connection »individual A chip package; greater than 丨 its gold content / each connection w 1 product initial investment is less than 10fc in the initial design; optionality * 捵:« change period: _ Tianzhizhuo is worth more than 50k in gold: 埂 It is expensive to change; «Change period: Early in the month of teaching is more than 30k in gold:« 捵 Cost is responsible;中 莘: You can use Λ ® Paralyzed tt crucible with medium and low reliability "with reward" package with wet · temperature and baking, eve. Silicon based "on one side Glob ιορ on flex twisted into bga | bga BGA Ping She only" The military side meter that needs to be dismantled and the new plan that requires a large bat degree, and «for size size, the size of the grain is larger than the size of the crystal, and the size of the grain is more than 20% of the size of the grain. (Die shrink) can Provided, the horror can go to Fengjie (30u) and be followed by Xuanjian, and its Mi 300α will be limited to S, and wire bonding. Discussion about the miniaturization of products by Takashi Shinoda and other TAB / lead bond Wire b〇nd / Flip chip applications Memory, logic, ASIC. [PC, smart media, analoe. RF Memory, logic ^ Memory, Logic Λ « Teach 0 less than 200 p 彳 nj less than 200 pms No limit * r Center & (Center pads) Super grade is not easy to pass

Page 14 Λ6 ^ 665 2 Simple explanation of the diagram Simple explanation of the present invention A picture of ten round steps diagram ten upper steps diagram ten semi-guide map ten diagrams ten circle steps ▲ The preferred embodiment of the month will be in the future The explanatory texts are supplemented by the following elaborate cabinet descriptions: Figures 10 through 10 are face-to-face drawings of traditional techniques. Shown is a cross-sectional view of a semiconductor wafer with a glass on the back of the wafer and an etch step in the present invention β = Shown is a cross-section of a semiconductor wafer with a vacuum-coated epoxy resin (epoxy) in a wafer step according to the present invention Illustration. The second display is a cross-sectional view of a wafer with a pad opening process using a laser. Four are cross-sectional views of a semiconductor wafer in a hot flow solder paste step. The five displays do not show the cross-sectional view of the semiconductor wafer with a glass attached to the back of the wafer and the etching process. ^ 11 epoxy 12 glass j 3 pad 1 4 film layer 1 5 openings 1 6 trench component symbol comparison 1 glass 3 epoxy (eP〇xy) 5 wafer 7 cutting path 9 trench 2 wafer 4 grain 6 epoxy resin 8 broken glass 1 epoxy resin

Page 15 4.6665 2, Round Simple Description 1 7 Circuit 19 Solder Paste Mask 2 1 Solder Ball 2 4 Cutting Tape 18 Solder Film Layer 20 Solder Paste 22 Solder Ball

Claims (1)

4 6 66 5 2 VI. Patent application scope Patent application scope: 1. A wafer type packaging process, the process includes: providing a wafer with a plurality of dies formed on it; grinding the back of the wafer ; Using a first adhesive substance to attach a material to the back surface of the wafer; etching a cutting track on the wafer to separate the plurality of grains; vacuum coating a second adhesive substance on the etched wafer Performing a pad opening step to expose the plurality of pads on the plurality of grains; performing a circuit redistribution step to place the circuit on the second adhesive substance; forming a solder paste mask on the second adhesive substance The substrate is used to expose a predetermined area on the circuit; a solder paste printing step is performed to form a solder paste on the predetermined area; and the solder paste is thermally flowed. 2. The manufacturing process of the wafer type package according to item 1 of the patent application scope, wherein the attached material includes glass. 3. The manufacturing process of the wafer type package according to item 1 of the patent application scope, wherein the attached material includes ceramics. V * 4. If the wafer type package manufacturing process of item 1 of the patent application scope, wherein the attached material includes quartz. Page 17 4 6 665 2 VI. Patent application scope 5, such as the wafer type packaging process of the first patent application scope, wherein the first adhesive material includes epoxy. 6 · The manufacturing process of the wafer type package according to the first patent application scope, wherein the second adhesive material includes epoxy. 7. For the wafer type packaging process of the first patent application scope, before grinding the back surface of the wafer, it further includes attaching an adhesive tape to the wafer. 8. If the wafer type packaging process of item 7 of the patent application scope, the method further includes removing the tape after attaching the substrate to the back of the wafer. 9. For example, the manufacturing process of the wafer type package of the first patent application scope, wherein after the vacuum coating the second adhesive material, the method further includes curing the second adhesive material. 10. The manufacturing process of the wafer type package according to item 9 of the scope of patent application, wherein the curing is performed by using ultraviolet irradiation. 1 1. The manufacturing process of the wafer type package according to item 1 of the patent application scope, wherein before performing the pad opening step, it further comprises grinding the second adhesive material. 1 2. If the wafer type package manufacturing process of item 1 of the patent application scope, where Page 18 2. VI. Scope of patent application The pad openings described are formed by laser. 1 3. The manufacturing process of the wafer type package according to item 1 of the patent application scope, wherein after performing the heat flow step, it further includes testing the wafer. 14. If the wafer type packaging process of item 13 in the scope of patent application is applied, after performing the test, the method further includes dicing the wafer to cut the wafer. 15. A wafer type package, comprising: a wafer having a plurality of dies formed thereon, wherein the wafer has trenches formed on the scribe line; a material is attached using a first adhesive material On the back of the wafer; a second adhesive material is located on the plurality of dies and fills the trench; the plurality of dies has a plurality of pads formed thereon; a circuit layout is formed on the second adhesive material A solder ball cover covering the circuit layout and the second adhesive material, and the circuit layout of the exposed portion; and a solder ball formed on the exposed portion and connected to the circuit layout . 16. The wafer type package according to item 15 of the patent application scope, wherein the attached material includes glass. '1 7. If the wafer type package of item 15 of the patent application scope, wherein the attachment Page 19 μ 2_ VI. Patent application materials include ceramics. 18. The wafer-type package according to item 15 of the scope of patent application, wherein the attached material includes quartz. 19. The wafer-type package according to item 15 of the scope of patent application, wherein the first adhesive material includes epoxy. 20. The wafer type package according to item 15 of the scope of patent application, wherein the second adhesive material comprises epoxy. Page 20