TWI713904B - Package and method of manufacturing the same - Google Patents

Package and method of manufacturing the same Download PDF

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Publication number
TWI713904B
TWI713904B TW107134220A TW107134220A TWI713904B TW I713904 B TWI713904 B TW I713904B TW 107134220 A TW107134220 A TW 107134220A TW 107134220 A TW107134220 A TW 107134220A TW I713904 B TWI713904 B TW I713904B
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Taiwan
Prior art keywords
package
component
carrier
conductive pillar
underfill
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TW107134220A
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Chinese (zh)
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TW201921526A (en
Inventor
黃英叡
謝靜華
余振華
劉重希
林志偉
黃見翎
Original Assignee
台灣積體電路製造股份有限公司
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Priority claimed from US15/966,468 external-priority patent/US11217555B2/en
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201921526A publication Critical patent/TW201921526A/en
Application granted granted Critical
Publication of TWI713904B publication Critical patent/TWI713904B/en

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    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/214—Connecting portions
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73209—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
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  • Wire Bonding (AREA)

Abstract

A method includes placing a first package component and a second package component over a carrier. The first conductive pillars of the first package component and second conductive pillars of the second package component face the carrier. The method further includes encapsulating the first package component and the second package component in an encapsulating material, de-bonding the first package component and the second package component from the carrier, planarizing the first conductive pillars, the second conductive pillars, and the encapsulating material, and forming redistribution lines to electrically couple to the first conductive pillars and the second conductive pillars.

Description

封裝體及其製造方法 Package body and manufacturing method thereof

本發明實施例是有關於一種封裝體及其製造方法。 The embodiment of the present invention relates to a package and a manufacturing method thereof.

隨著半導體技術的發展，半導體晶片/晶粒變得愈來愈小。同時，需要將更多功能整合至半導體晶粒中。因此，半導體晶粒需要將愈來愈多的I/O接墊封裝到更小的區域中，且I/O接墊的密度隨時間推移而快速提高。因此，半導體晶粒的封裝變得更加困難，此對封裝的良率具有不利的影響。 With the development of semiconductor technology, semiconductor wafers/dies become smaller and smaller. At the same time, more functions need to be integrated into the semiconductor die. Therefore, the semiconductor die needs to pack more and more I/O pads into a smaller area, and the density of the I/O pads increases rapidly over time. Therefore, the packaging of semiconductor dies becomes more difficult, which has an adverse effect on the yield of the packaging.

習知的封裝技術可分為兩類。在第一類中，晶圓上的晶粒在被鋸切之前進行封裝。此封裝技術具有一些有利特徵，例如，較大產量以及較低成本。另外，需要較少底填充劑或模製化合物。然而，此封裝技術也存在缺點。由於晶粒的尺寸變得愈來愈小，且各別封裝體可僅為扇入型封裝體，其中各晶粒的I/O接墊限於直接位於相應的晶粒的表面上方的區域。隨著晶粒的面積受限，I/O接墊的數量因I/O接墊的間距限制而受到限制。若接墊的間距將減小，則可出現焊料橋接(solder bridges)。另外，在固定焊球尺寸的要求下，焊球必須具有一定的尺寸，此又限制可封裝於晶 粒的表面上的焊球的數量。 The conventional packaging technology can be divided into two categories. In the first category, the die on the wafer is packaged before being sawed. This packaging technology has some advantageous features, such as greater yield and lower cost. In addition, less underfill or molding compound is required. However, this packaging technology also has disadvantages. As the size of the die becomes smaller and smaller, and the individual packages may only be fan-in packages, the I/O pads of each die are limited to the area directly above the surface of the corresponding die. As the area of the die is limited, the number of I/O pads is limited due to the spacing of the I/O pads. If the distance between the pads is reduced, solder bridges may occur. In addition, under the requirement of fixed solder ball size, the solder ball must have a certain size, which in turn limits the ability to be packaged in the crystal. The number of solder balls on the surface of the pellet.

在另一類的封裝中，晶粒在被封裝之前從晶圓上鋸切下來。此封裝技術的有利特徵為形成扇出型封裝體的可能性，這意謂可將晶粒上的I/O接墊可被重新分配至比晶粒更大的面積，且因此可增加封裝於晶粒的表面上的I/O接墊的數量。此封裝技術的另一有利特徵為封裝「已知良好晶粒(known-good-dies)」且拋棄有缺陷的晶粒，且因此不會浪費成本以及精力在有缺陷的晶粒上。 In another type of packaging, the die is sawed from the wafer before being packaged. The advantageous feature of this packaging technology is the possibility of forming a fan-out package, which means that the I/O pads on the die can be redistributed to a larger area than the die, and therefore the package can be increased The number of I/O pads on the surface of the die. Another advantageous feature of this packaging technology is packaging "known-good-dies" and discarding defective dies, and therefore it does not waste cost and energy on defective dies.

本發明實施例提供一種封裝體的製造方法，其步驟如下。將第一封裝組件以及第二封裝組件置放在載體上，其中第一封裝組件的第一導電柱以及第二封裝組件的第二導電柱面向載體；將第一封裝組件以及第二封裝組件包封在包封材料中；將第一封裝組件以及第二封裝組件自載體剝離；平坦化第一導電柱、第二導電柱以及包封材料；以及形成重佈線以電耦接至第一導電柱以及第二導電柱。 The embodiment of the present invention provides a method for manufacturing a package, and the steps are as follows. Place the first package component and the second package component on the carrier, wherein the first conductive post of the first package component and the second conductive post of the second package component face the carrier; the first package component and the second package component are packaged Encapsulated in an encapsulating material; peeling the first package component and the second package component from the carrier; planarizing the first conductive pillar, the second conductive pillar, and the encapsulating material; and forming a redistribution line to be electrically coupled to the first conductive pillar And the second conductive pillar.

本發明實施例提供一種封裝體的製造方法，其步驟如下。在載體上形成多個金屬接墊；將第一封裝組件的第一導電柱以及第二封裝組件的第二導電柱接合至多個金屬接墊；在第一封裝組件以及第二封裝組件下點膠底填充劑；將第一封裝組件以及第二封裝組件包封在包封材料中，以形成複合晶圓；將複合晶圓自載體剝離；以及對第一封裝組件、第二封裝組件、底填充劑以及包封材料進行第一平坦化，以移除多個金屬接墊。 The embodiment of the present invention provides a method for manufacturing a package, and the steps are as follows. A plurality of metal pads are formed on the carrier; the first conductive pillars of the first package component and the second conductive pillars of the second package component are bonded to the plurality of metal pads; glue is dispensed under the first package component and the second package component Underfill; encapsulate the first package component and the second package component in an encapsulating material to form a composite wafer; peel the composite wafer from the carrier; and fill the first package component, the second package component, and the underfill The agent and the encapsulating material are first planarized to remove the metal pads.

本發明實施例提供一種封裝體包括第一封裝組件、第二封裝組件、包封材料、底填充劑以及重佈線。包封材料包封第一封裝組件以及第二封裝組件於其中。介電層配置在包封材料上且接觸包封材料。底填充劑包括第一部分與第二部分。第一部分配置在第一封裝組件與介電層之間，其中第一封裝組件的第一導電柱位於底填充劑中，且底填充劑的上部部分寬於底填充劑的下部部分。第二部分配置在第二封裝組件與介電層之間，其中第二封裝組件的第二導電柱位於底填充劑中。重佈線延伸至介電層內，以接觸第一導電柱以及第二導電柱。 The embodiment of the present invention provides a package body including a first package component, a second package component, an encapsulating material, an underfill and a rewiring. The encapsulating material encapsulates the first packaging component and the second packaging component therein. The dielectric layer is disposed on and in contact with the encapsulation material. The underfill includes a first part and a second part. The first part is disposed between the first packaging component and the dielectric layer, wherein the first conductive pillar of the first packaging component is located in the underfill, and the upper part of the underfill is wider than the lower part of the underfill. The second part is configured between the second packaging component and the dielectric layer, wherein the second conductive pillar of the second packaging component is located in the underfill. The rewiring extends into the dielectric layer to contact the first conductive pillar and the second conductive pillar.

20、50:載體 20, 50: carrier

22:離型膜 22: Release film

23:模板膜 23: template film

24:聚合物緩衝層 24: polymer buffer layer

26:金屬層 26: Metal layer

26A:鈦層 26A: Titanium layer

26B:銅層 26B: Copper layer

28:金屬接墊 28: Metal pad

30:導引帶 30: guide belt

32A、32B、80:封裝組件 32A, 32B, 80: package components

34A、34B:半導體基底 34A, 34B: semiconductor substrate

36A、36B:內連結構 36A, 36B: internal connection structure

38A、38B:導電柱 38A, 38B: conductive pillar

40、78:焊料區域 40, 78: solder area

42、42’:底填充劑 42, 42’: Underfill

42A、46A:基質材料 42A, 46A: matrix material

42B、46B:填充劑粒子 42B, 46B: filler particles

44:點膠機 44: Dispenser

46:包封材料 46: Encapsulation material

52:離型膜 52: Release film

54:複合晶圓 54: Composite wafer

54'、84:封裝體 54', 84: package body

56、86:區域 56, 86: area

60、64、68、72:介電層 60, 64, 68, 72: dielectric layer

62、66、70:重佈線(RDL) 62, 66, 70: Rewiring (RDL)

62A:凹陷 62A: Depressed

74:凸塊下金屬(UBM) 74: Under bump metal (UBM)

76:電連接件 76: electrical connection

200、300:製程流程 200, 300: process flow

202、204、206、208、210、212、214、216、218、220、220、302、304、306、308、310、312、314、316、318、320:步驟 202, 204, 206, 208, 210, 212, 214, 216, 218, 220, 220, 302, 304, 306, 308, 310, 312, 314, 316, 318, 320: steps

當結合附圖閱讀時，自以下詳細描述最佳地理解本揭露內容的態樣。應注意，根據行業中的標準實踐，各種特徵未按比例繪製。事實上，可出於論述清楚起見，而任意地增大或減小各種特徵的尺寸。 When read in conjunction with the accompanying drawings, the aspect of the disclosure can be best understood from the following detailed description. It should be noted that the various features are not drawn to scale according to standard practice in the industry. In fact, the size of various features can be increased or decreased arbitrarily for clarity of discussion.

圖1至圖14示出根據一些實施例的封裝體的形成的中間階段的橫截面圖。 1 to 14 show cross-sectional views of intermediate stages of the formation of a package according to some embodiments.

圖15至圖22示出根據一些實施例的封裝體的形成的中間階段的橫截面圖。 15-22 illustrate cross-sectional views of intermediate stages of the formation of a package according to some embodiments.

圖23示出根據一些實施例的金屬接墊以及導引帶的俯視圖。 Figure 23 shows a top view of a metal pad and a guide band according to some embodiments.

圖24A以及圖24B分別示出根據一些實施例的封裝組件以及殘餘焊料區域中的導電柱的橫截面圖以及俯視圖。 24A and 24B respectively show a cross-sectional view and a top view of a package assembly and a conductive post in a residual solder area according to some embodiments.

圖25示出根據一些實施例的包括經平坦化的底填充劑以及包封材料的封裝體的一部分的放大圖。 Figure 25 shows an enlarged view of a portion of a package including a planarized underfill and an encapsulating material according to some embodiments.

圖26及圖27示出用於形成根據一些實施例的封裝體的製程流程。 Figures 26 and 27 illustrate a process flow for forming a package according to some embodiments.

以下揭露內容提供用於實施所提供的目標的不同特徵的許多不同實施例或實例。以下所描述構件與配置的具體實例來簡化本揭露。當然，這些僅僅是示例，而非用以限制。舉例而言，在以下的描述中，在第二特徵上方或在第二特徵上形成第一特徵可包括第一特徵與第二特徵形成為直接接觸的實施例，並且還可以包括第一特徵與第二特徵之間可形成有額外特徵，使得第一特徵與第二特徵可不直接接觸的實施例。此外，本揭露在各種實例中可重複使用元件標號及/或字母。元件標號的重複使用是為了簡單及清楚起見，且並不表示所欲討論的各個實施例及/或配置本身之間的關係。 The following disclosure provides many different embodiments or examples for implementing different features of the provided goals. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are just examples, not limitations. For example, in the following description, forming the first feature over or on the second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include the first feature and the Additional features may be formed between the second features, so that the first feature and the second feature may not directly contact an embodiment. In addition, the present disclosure may reuse element numbers and/or letters in various examples. The repeated use of element numbers is for simplicity and clarity, and does not indicate the relationship between the various embodiments and/or configurations to be discussed.

另外，如「在...下方」、「下面」、「下部」、「在...上方」、「上部」等空間相對術語來闡述圖中所示的一個元件或特徵與另一(些)元件或特徵的關係。除圖式中所描繪之定向以外，空間相對術語意欲涵蓋裝置或設備在使用或操作中之不同定向。裝置或設備可以其他方式定向(旋轉90度或處於其他定向)，且本文中所使用之空間相對描述詞可同樣相應地進行解釋。 In addition, relative terms such as "below", "below", "lower", "above", "upper" and other spatial relative terms are used to describe one element or feature shown in the figure with another (some ) The relationship between elements or features. In addition to the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of devices or equipment in use or operation. The device or equipment can be oriented in other ways (rotated by 90 degrees or in other orientations), and the spatial relative descriptors used in this text can also be interpreted accordingly.

根據各種例示性實施例來提供整合型扇出(Integrated Fan-Out；InFO)封裝體以及其形成方法。根據一些實施例說明形成InFO封裝體的中間階段。論述一些實施例的一些變化。在各種視圖以及說明性實施例，相同的元件標號用以表示相同的元件。 According to various exemplary embodiments, an integrated fan-out (InFO) package and a method of forming the same are provided. According to some embodiments, an intermediate stage of forming the InFO package is described. Some variations of some embodiments are discussed. In the various views and illustrative embodiments, the same element numbers are used to denote the same elements.

圖1至圖14示出根據一些實施例的封裝體的形成的中間階段的橫截面圖。繪示在圖1至圖14中的步驟亦示意地說明在圖26中所示出的製程流程200中。 1 to 14 show cross-sectional views of intermediate stages of the formation of a package according to some embodiments. The steps depicted in FIGS. 1 to 14 are also schematically illustrated in the process flow 200 shown in FIG. 26.

參照圖1，提供載體20，且在載體20上塗佈離型膜22。載體20由透明材料形成，且可為玻璃載體、陶瓷載體、有機載體或類似者。載體20可具有圓形的俯視形狀，且可具有矽晶圓的尺寸。舉例而言，載體20可具有8英吋直徑、12英吋直徑或類似者。離型膜22與載體20的頂表面物理接觸。離型膜22可由光熱轉換(Light-To-Heat-Conversion；LTHC)塗佈材料形成。離型膜22可經由塗佈而塗覆至載體20上。根據本揭露內容的一些實施例，LTHC塗佈材料在光/輻射(例如，雷射)的熱能下能夠分解，且因此可分離形成於其上的結構與載體20。根據本揭露內容的一些實施例，LTHC層22包括碳黑(碳粒子)、溶劑、填料及/或環氧樹脂。LTHC層22可以可流動形式來塗佈，且接著在例如紫外(ultra-violet；UV)光下進行固化。 1, a carrier 20 is provided, and a release film 22 is coated on the carrier 20. The carrier 20 is formed of a transparent material, and may be a glass carrier, a ceramic carrier, an organic carrier, or the like. The carrier 20 may have a circular top view shape and may have the size of a silicon wafer. For example, the carrier 20 may have a diameter of 8 inches, a diameter of 12 inches, or the like. The release film 22 is in physical contact with the top surface of the carrier 20. The release film 22 may be formed of a light-to-heat conversion (LTHC) coating material. The release film 22 may be coated on the carrier 20 through coating. According to some embodiments of the present disclosure, the LTHC coating material can be decomposed under the thermal energy of light/radiation (for example, laser), and thus the structure formed thereon and the carrier 20 can be separated. According to some embodiments of the present disclosure, the LTHC layer 22 includes carbon black (carbon particles), solvent, filler, and/or epoxy. The LTHC layer 22 may be coated in a flowable form, and then cured under, for example, ultraviolet (UV) light.

根據一些實施例，如亦在圖1中所繪示，聚合物緩衝層24形成於離型膜22上。根據一些實施例，聚合物緩衝層24由聚苯并噁唑(PBO)、聚醯亞胺、苯并環丁烯(BCB)或另一可適用的聚合物來形成。根據本揭露內容的替代性實施例，不形成聚合物緩衝層24。因此，將聚合物緩衝層24繪示為虛線以表示其可或可不形成。 According to some embodiments, as also shown in FIG. 1, the polymer buffer layer 24 is formed on the release film 22. According to some embodiments, the polymer buffer layer 24 is formed of polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or another applicable polymer. According to an alternative embodiment of the present disclosure, the polymer buffer layer 24 is not formed. Therefore, the polymer buffer layer 24 is drawn as a dotted line to indicate that it may or may not be formed.

圖1進一步說明金屬層26的形成，其可經由沈積來進行。將相應的步驟繪示為圖26中所示的製程流程中的步驟202。金屬層26可(例如)經由物理氣相沈積(Physical Vapor Deposition；PVD)形成。根據本揭露內容的一些實施例，在LTHC塗層22與金屬層26之間沒有形成介電層，因此金屬層26與LTHC層22物理接觸。舉例而言，於金屬層26與LTHC層22之間沒有聚合物層(例如，聚醯亞胺層、聚苯并噁唑(PBO)層或苯并環丁烯(BCB)層)。根據本揭露內容的一些實施例，金屬層26包括鈦層26A以及在鈦層26A上的銅層26B。根據本揭露內容的替代性實施例，金屬層26為可為銅層的均質層。 Figure 1 further illustrates the formation of the metal layer 26, which can be carried out via deposition. The corresponding steps are shown as step 202 in the process flow shown in FIG. 26. The metal layer 26 can be, for example, via physical vapor deposition (Physical Vapor Deposition) Deposition; PVD) formation. According to some embodiments of the present disclosure, no dielectric layer is formed between the LTHC coating 22 and the metal layer 26, so the metal layer 26 is in physical contact with the LTHC layer 22. For example, there is no polymer layer (for example, a polyimide layer, a polybenzoxazole (PBO) layer, or a benzocyclobutene (BCB) layer) between the metal layer 26 and the LTHC layer 22. According to some embodiments of the present disclosure, the metal layer 26 includes a titanium layer 26A and a copper layer 26B on the titanium layer 26A. According to an alternative embodiment of the present disclosure, the metal layer 26 is a homogeneous layer that may be a copper layer.

現在參照圖2。接下來，藉由蝕刻以圖案化金屬層26，且形成金屬接墊28。將相應的步驟繪示為圖26所示的製程流程中的步驟204。決定金屬接墊28的位置以及尺寸以匹配後續置放的封裝組件32A以及32B(如圖3所示)的位置以及尺寸，使得封裝組件32A以及32B可接合至金屬接墊28。除了金屬接墊28外，金屬層26的其餘部分可(或可不)包括細長條的導引帶(guiding strips)30。圖23示出根據本揭露內容的一些實施例的一些例示性的金屬接墊28以及導引帶30的俯視圖。如圖23所示，至少一些導引帶30位於金屬接墊28的兩個群組之間，且導引帶30自一個群組引導至另一群組。圖23亦示意性示出封裝組件32A以及32B，其在圖3所示的步驟中隨後接合至金屬接墊28。 Refer now to Figure 2. Next, the metal layer 26 is patterned by etching, and the metal pad 28 is formed. The corresponding steps are shown as step 204 in the process flow shown in FIG. 26. The position and size of the metal pad 28 are determined to match the positions and sizes of the package components 32A and 32B (as shown in FIG. 3) to be placed subsequently, so that the package components 32A and 32B can be bonded to the metal pad 28. Except for the metal pads 28, the rest of the metal layer 26 may (or may not) include elongated guiding strips 30. FIG. 23 shows a top view of some exemplary metal pads 28 and guide bands 30 according to some embodiments of the present disclosure. As shown in FIG. 23, at least some of the guiding tapes 30 are located between the two groups of metal pads 28, and the guiding tapes 30 are guided from one group to another group. FIG. 23 also schematically shows the package components 32A and 32B, which are subsequently bonded to the metal pad 28 in the step shown in FIG. 3.

根據本揭露內容的替代性實施例，金屬接墊28以及導引帶30的形成包括沈積毯覆式金屬晶種層、形成並圖案化光阻以暴露毯覆式金屬晶種層的一些部分、在光阻中的開口中鍍覆金屬材料、移除光阻以及蝕刻不被金屬材料所覆蓋的部分金屬晶種層。經鍍覆的金屬材料以及金屬晶種層的其餘部分形成金屬接墊28以及導引帶30。 According to an alternative embodiment of the present disclosure, the formation of the metal pad 28 and the guiding tape 30 includes depositing a blanket metal seed layer, forming and patterning a photoresist to expose some parts of the blanket metal seed layer, The opening in the photoresist is plated with metal material, the photoresist is removed, and part of the metal seed layer not covered by the metal material is etched. The plated metal material and the remaining part of the metal seed layer form the metal pad 28 and the guiding strip 30.

圖3示出封裝組件32A以及32B(其亦共同地以及個別地被稱作封裝組件32或裝置32)的置放/附著。封裝組件32A以及32B可包括裝置晶粒，裝置晶粒包括在各別半導體基底34A以及34B的前表面(面向下的表面)處的積體電路裝置(例如，包括電晶體的主動裝置)。根據本揭露內容的一些實施例，封裝組件32A以及32B中的每一者可為邏輯晶粒，邏輯晶粒可為中央處理單元(Central Processing Unit；CPU)晶粒、圖形處理單元(Graphic Processing Unit；GPU)晶粒、行動應用晶粒、微型控制單元(Micro Control Unit；MCU)晶粒、輸入輸出(input-output；IO)晶粒、基頻(BaseBand；BB)晶粒或應用處理器(Application processor；AP)晶粒。封裝組件32A以及32B中的每一者亦可為系統上晶片(System-On-Chip)晶粒、記憶體晶粒(例如，靜態隨機存取記憶體(Static Random Access Memory；SRAM)晶粒或動態隨機存取記憶體(Dynamic Random Access Memory；DRAM)晶粒)、高頻寬記憶體(High-Bandwidth-Memory；HBM)立方體或類似者。 Figure 3 shows the placement/attachment of package components 32A and 32B (which are also collectively and individually referred to as package components 32 or devices 32). The package components 32A and 32B may include device dies, and the device dies include integrated circuit devices (for example, active devices including transistors) at the front surfaces (downward-facing surfaces) of the respective semiconductor substrates 34A and 34B. According to some embodiments of the present disclosure, each of the package components 32A and 32B may be a logic die, and the logic die may be a central processing unit (CPU) die, or a graphic processing unit (Graphic Processing Unit). ; GPU) die, mobile application die, Micro Control Unit (MCU) die, input-output (input-output; IO) die, BaseBand (BB) die or application processor ( Application processor; AP) die. Each of the package components 32A and 32B may also be a system-on-chip (System-On-Chip) die, a memory die (for example, a static random access memory (Static Random Access Memory; SRAM) die or Dynamic Random Access Memory (DRAM) die), High-Bandwidth-Memory (HBM) cube or the like.

封裝組件32A以及32B可包括半導體基底34A以及34B，根據一些例示性實施例，半導體基底亦可為矽基底。封裝組件32A以及32B亦可分別包括內連結構36A與36B以及導電柱38A與38B。內連結構36A以及36B可包括介電層以及介電層中的金屬線與通孔。導電柱38A以及38B可為金屬柱，且可包括銅柱，其可或可不包括例如鎳層、金層、鈀層或類似者的額外層。導電柱38A以及38B可具有垂直且筆直的邊緣，且可分別突出於封裝組件32A以及32B中的介電層的各別表面的下方。導電柱38A以及38B被預先形成為封裝組件32A以及32B的一部分，且分別 電耦接至封裝組件32A以及32B中的積體電路裝置(例如電晶體)。 The package components 32A and 32B may include semiconductor substrates 34A and 34B. According to some exemplary embodiments, the semiconductor substrate may also be a silicon substrate. The packaging components 32A and 32B may also include interconnecting structures 36A and 36B and conductive posts 38A and 38B, respectively. The interconnection structures 36A and 36B may include a dielectric layer and metal lines and vias in the dielectric layer. The conductive pillars 38A and 38B may be metal pillars, and may include copper pillars, which may or may not include additional layers such as a nickel layer, a gold layer, a palladium layer, or the like. The conductive pillars 38A and 38B may have vertical and straight edges, and may protrude below the respective surfaces of the dielectric layers in the package components 32A and 32B, respectively. The conductive posts 38A and 38B are pre-formed as part of the package components 32A and 32B, and are respectively It is electrically coupled to integrated circuit devices (such as transistors) in the package components 32A and 32B.

封裝組件(裝置)32經由焊料區域40接合至金屬接墊28，焊料區域40可為預先形成的封裝組件32的一部分。將相應的步驟繪示為圖26所示的製程流程中的步驟206。所述接合包括對準步驟、輕壓每一個封裝組件32以及回焊製程。可在置放所有封裝組件32後進行回焊，或可對每一個封裝組件32進行回焊。將導電柱38A以及38B的位置與相應的金屬接墊28對準。金屬接墊28的水平尺寸可大於、等於或小於相應的上覆導電柱38A以及38B的水平尺寸。回焊製程亦為自對準製程，這是由於封裝組件32A以及32B的位置將藉由熔融焊料區域40而對準。因此，只要金屬接墊28準確地形成至預定的位置，封裝組件32A以及32B則將與載體20上的預期的位置對準。另外，藉由面向下的方式置放封裝組件32A以及32B，以使導電柱38A以及38B接合至在同一平面上的金屬接墊28，而導電柱38A的底表面與導電柱38B的底表面實質上對齊至同一水平面。 The package component (device) 32 is bonded to the metal pad 28 via a solder area 40, which may be a part of a pre-formed package component 32. The corresponding steps are shown as step 206 in the process flow shown in FIG. 26. The bonding includes an alignment step, light pressing of each package component 32, and a reflow process. Reflow may be performed after placing all the package components 32, or each package component 32 may be reflowed. Align the positions of the conductive pillars 38A and 38B with the corresponding metal pads 28. The horizontal size of the metal pad 28 may be greater than, equal to, or smaller than the horizontal size of the corresponding overlying conductive posts 38A and 38B. The reflow process is also a self-aligning process, because the positions of the package components 32A and 32B will be aligned by the molten solder area 40. Therefore, as long as the metal pad 28 is accurately formed to the predetermined position, the package components 32A and 32B will be aligned with the expected position on the carrier 20. In addition, by placing the package components 32A and 32B face down, the conductive pillars 38A and 38B are bonded to the metal pad 28 on the same plane, and the bottom surface of the conductive pillar 38A and the bottom surface of the conductive pillar 38B are substantially Align the top to the same horizontal plane.

由於載體20處於晶圓級，因此雖然繪示出一個封裝組件32A以及一個封裝組件32B，但多個相同的裝置晶粒32A以及多個相同的裝置晶粒32B可接合至相應的金屬接墊28。封裝組件32A以及32B可配置為裝置群組，各自包括一個封裝組件32A以及一個封裝組件32B。所述裝置群組可配置為包括多個列以及多個行的陣列。 Since the carrier 20 is at the wafer level, although one package component 32A and one package component 32B are shown, a plurality of the same device die 32A and a plurality of the same device die 32B can be bonded to the corresponding metal pad 28 . The packaging components 32A and 32B can be configured as a device group, and each includes one packaging component 32A and one packaging component 32B. The device group may be configured as an array including multiple columns and multiple rows.

圖4示出底填充劑42的點膠(dispensing)以及固化。相應的步驟繪示為圖26所示的製程流程中的步驟208。根據本揭露內容的一些實施例，藉由在包括封裝組件32A以及32B的裝置 群組的一側上的點膠機44點膠底填充劑42。底填充劑42隨後流動至緩衝層24與封裝組件32A之間的間隙、封裝組件32A與32B之間的間隙以及緩衝層24與封裝組件32B之間的間隙。導引帶30具有引導底填充劑42的流動的功能，使得底填充劑42更易於流經封裝組件32A與32B之間的間隙，且流動至緩衝層24與封裝組件32B之間的間隙內。在無導引帶30的情況下，底填充劑42更可能累積於封裝組件32A與32B之間的間隙中，且流動至緩衝層24與封裝組件32B之間的間隙內的底填充劑42較少。 FIG. 4 shows the dispensing and curing of the underfill 42. The corresponding steps are shown as step 208 in the process flow shown in FIG. 26. According to some embodiments of the present disclosure, by using a device including packaging components 32A and 32B The dispenser 44 on one side of the group dispenses the underfill 42. The underfill 42 then flows to the gap between the buffer layer 24 and the package component 32A, the gap between the package components 32A and 32B, and the gap between the buffer layer 24 and the package component 32B. The guiding belt 30 has the function of guiding the flow of the underfill 42 so that the underfill 42 can more easily flow through the gap between the packaging components 32A and 32B and into the gap between the buffer layer 24 and the packaging component 32B. Without the guiding tape 30, the underfill 42 is more likely to accumulate in the gap between the package components 32A and 32B, and the underfill 42 flowing into the gap between the buffer layer 24 and the package component 32B is more likely less.

底填充劑42可包括基質材料42A(參照圖25)與基質材料42A中的填充劑粒子42B，其中基質材料42A可為聚合物、樹脂、環氧樹脂或類似者。填充劑粒子42B可為SiO2、Al2O3、二氧化矽(silica)或類似者的介電粒子，且可具有球形形狀。另外，球形填充劑粒子可具有多個不同的直徑。底填充劑42中的填充劑粒子42B以及基質材料42A兩者皆可與聚合物緩衝層24物理接觸(如圖4所示)；若未形成聚合物層24，則底填充劑42中的填充劑粒子42B以及基質材料42A兩者皆可與LTHC層22物理接觸。 The underfill 42 may include a matrix material 42A (refer to FIG. 25) and filler particles 42B in the matrix material 42A, wherein the matrix material 42A can be a polymer, resin, epoxy, or the like. The filler particles 42B may be dielectric particles of SiO 2 , Al 2 O 3 , silica or the like, and may have a spherical shape. In addition, the spherical filler particles may have multiple different diameters. Both the filler particles 42B and the matrix material 42A in the underfill 42 can be in physical contact with the polymer buffer layer 24 (as shown in FIG. 4); if the polymer layer 24 is not formed, the filling in the underfill 42 Both the agent particles 42B and the matrix material 42A can be in physical contact with the LTHC layer 22.

接下來，將封裝組件32A以及32B包封在包封材料46中，如圖5所示。將相應的步驟繪示為圖26所示的製程流程中的步驟210。包封材料46填入相鄰封裝組件32A與32B之間的間隙。包封材料46可包括模製化合物、模製底填充劑、環氧樹脂及/或樹脂。包封材料46的頂表面高於兩個封裝組件32A以及32B的頂表面。包封材料46亦可包括基質材料46A(參照圖25)以及基質材料46A中的填充劑粒子46B，其中基質材料46A可為聚合物、樹脂、環氧樹脂或類似者。填充劑粒子46B可為SiO2、Al2O3、二氧 化矽或類似者的介電粒子，且可具有球形形狀。另外，球形填充劑粒子46B可具有多個不同的直徑。結合圖5與圖25所示，填充劑粒子46B以及基質材料46A兩者可與聚合物緩衝層24物理接觸；若未形成聚合物層24，則填充劑粒子46B以及基質材料46A兩者可與LTHC層22物理接觸。 Next, the packaging components 32A and 32B are encapsulated in the packaging material 46, as shown in FIG. 5. The corresponding steps are shown as step 210 in the process flow shown in FIG. 26. The encapsulating material 46 fills the gap between adjacent package components 32A and 32B. The encapsulating material 46 may include a molding compound, a molding underfill, epoxy, and/or resin. The top surface of the encapsulating material 46 is higher than the top surfaces of the two packaging components 32A and 32B. The encapsulation material 46 may also include a matrix material 46A (refer to FIG. 25) and filler particles 46B in the matrix material 46A, where the matrix material 46A can be a polymer, resin, epoxy resin, or the like. The filler particles 46B may be dielectric particles of SiO 2 , Al 2 O 3 , silicon dioxide, or the like, and may have a spherical shape. In addition, the spherical filler particles 46B may have a plurality of different diameters. 5 and 25, both the filler particles 46B and the matrix material 46A can be in physical contact with the polymer buffer layer 24; if the polymer layer 24 is not formed, the filler particles 46B and the matrix material 46A can be in contact with The LTHC layer 22 is in physical contact.

在後續步驟中，如圖6中所繪示，進行例如化學機械拋光(Chemical Mechanical Polish；CMP)步驟或機械研磨步驟的平坦化步驟以薄化包封材料46，直至暴露出封裝組件32A以及32B中的一者或兩者。將相應的步驟繪示為圖26所示的製程流程中的步驟212。根據本揭露內容的一些實施例，可為矽基底的基底34A以及34B被暴露。由於所述平坦化製程，封裝組件32A以及32B的頂表面與包封材料46的頂表面實質上齊平(共平面)。根據替代性實施例，在結束平坦化之後，封裝組件32A以及32B中的一者不被暴露，且其被包封材料46的剩餘層直接覆蓋。在全文中，上覆LTHC層22的結構被稱作複合晶圓54。 In the subsequent steps, as shown in FIG. 6, a planarization step such as a chemical mechanical polishing (CMP) step or a mechanical polishing step is performed to thin the encapsulating material 46 until the package components 32A and 32B are exposed One or both of them. The corresponding steps are shown as step 212 in the process flow shown in FIG. 26. According to some embodiments of the present disclosure, the substrates 34A and 34B, which may be silicon substrates, are exposed. Due to the planarization process, the top surfaces of the package components 32A and 32B and the top surface of the encapsulation material 46 are substantially flush (coplanar). According to an alternative embodiment, after the planarization is finished, one of the packaging components 32A and 32B is not exposed, and it is directly covered by the remaining layer of the encapsulation material 46. Throughout the text, the structure overlying the LTHC layer 22 is referred to as a composite wafer 54.

圖7示出載體調換。將相應的步驟繪示為圖26所示的製程流程中的步驟214。在載體調換期間，載體50例如藉由離型膜52附著至封裝組件32A、32B以及包封材料46所示的表面。載體50附著至複合晶圓54的一側，其相對於載體20(如圖6所示)。接下來，自載體20卸下封裝組件32A、32B以及包封材料46(如圖6所示)。根據本揭露內容的一些實施例，所述卸下包括分解LTHC層22，其包括在LTHC層22上投射例如雷射光束的載熱輻射。因此，LTHC層22被分解，且載體20可自LTHC層22分離。複合晶圓54因此自載體20剝離(卸下)。所得結構繪示於圖7中。 若複合晶圓54包括聚合物緩衝層24(如圖6所示)，則亦移除聚合物緩衝層24，從而暴露底填充劑42以及包封材料46，如亦在圖7中所示。因此暴露出金屬接墊28以及導引帶30。 Figure 7 shows carrier swapping. The corresponding steps are shown as step 214 in the process flow shown in FIG. 26. During the exchange of the carrier, the carrier 50 is attached to the surface shown by the packaging components 32A, 32B and the packaging material 46 by, for example, a release film 52. The carrier 50 is attached to one side of the composite wafer 54 opposite to the carrier 20 (as shown in FIG. 6). Next, the packaging components 32A, 32B and the packaging material 46 are removed from the carrier 20 (as shown in FIG. 6). According to some embodiments of the present disclosure, the removal includes decomposing the LTHC layer 22, which includes projecting heat-carrying radiation such as a laser beam on the LTHC layer 22. Therefore, the LTHC layer 22 is decomposed, and the carrier 20 can be separated from the LTHC layer 22. The composite wafer 54 is thus peeled (unloaded) from the carrier 20. The resulting structure is shown in FIG. 7. If the composite wafer 54 includes the polymer buffer layer 24 (as shown in FIG. 6), the polymer buffer layer 24 is also removed, thereby exposing the underfill 42 and the encapsulating material 46, as also shown in FIG. Therefore, the metal pad 28 and the guiding tape 30 are exposed.

接下來，進行例如CMP或機械研磨的平坦化步驟以移除金屬接墊28、導引帶30以及焊料區域40，使得導電柱38的頂表面被暴露出來。將相應的步驟繪示為圖26所示的製程流程中的步驟216。所得結構繪示於圖8中。根據本揭露內容的一些實施例，移除所有焊料區域40，因此沒有焊料區域40的殘餘物留在複合晶圓54中。根據本揭露內容的一些實施例，在將封裝組件32A以及32B接合至金屬接墊28時，焊料區域40的一些部分流至導電柱38A以及38B的側壁。焊料區域40的這些部分可留或可不留在複合晶圓54中，如圖8中所繪示。圖24A繪示出圖8中的區域56的放大圖。如圖24A所示，焊料區域40的殘餘部分接觸導電柱38A(或38B)的頂部部分的側壁，且不接觸相應的導電柱38A(或38B)的底部部分的側壁。圖24B繪示出區域56的俯視圖。如圖24B中所繪示，焊料區域40的殘餘部分可接觸側壁的一部分(在俯視圖中)，而不接觸其他部分。焊料區域40的殘餘部分亦可形成環繞導電柱38A(或38B)的環，如虛線所示。焊料區域40的圖案是隨機的。舉例而言，焊料區域40的殘餘部分可留在一些導電柱38A以及38B上，且不會留在另一些導電柱38A以及38B上。 Next, a planarization step such as CMP or mechanical polishing is performed to remove the metal pad 28, the guiding tape 30, and the solder region 40, so that the top surface of the conductive pillar 38 is exposed. The corresponding steps are shown as step 216 in the process flow shown in FIG. 26. The resulting structure is shown in Figure 8. According to some embodiments of the present disclosure, all the solder regions 40 are removed, so no residue of the solder regions 40 remains in the composite wafer 54. According to some embodiments of the present disclosure, when the package components 32A and 32B are bonded to the metal pad 28, some parts of the solder region 40 flow to the sidewalls of the conductive pillars 38A and 38B. These parts of the solder area 40 may or may not remain in the composite wafer 54 as shown in FIG. 8. FIG. 24A illustrates an enlarged view of the area 56 in FIG. 8. As shown in FIG. 24A, the remaining portion of the solder region 40 contacts the sidewall of the top portion of the conductive pillar 38A (or 38B), and does not contact the sidewall of the bottom portion of the corresponding conductive pillar 38A (or 38B). FIG. 24B illustrates a top view of the area 56. As shown in FIG. 24B, the remaining part of the solder region 40 may contact a part of the sidewall (in a top view), but not other parts. The remaining part of the solder region 40 can also form a ring surrounding the conductive pillar 38A (or 38B), as shown by the dashed line. The pattern of the solder area 40 is random. For example, the remaining part of the solder region 40 may be left on some conductive pillars 38A and 38B, but not on other conductive pillars 38A and 38B.

圖9至圖12示出前側內連結構的形成。將相應的步驟繪示為圖26所示的製程流程中的步驟218。圖9示出第一重佈線(Redistribution Line；RDL)層以及相應的介電層的形成。介電層 60形成於封裝組件32A與32B以及包封材料46之上。根據本揭露內容的一些實施例，介電層60由例如PBO、聚醯亞胺或類似者的聚合物形成。所述形成方法包括以可流動形式塗佈介電層60，並接著固化介電層60。根據本揭露內容的替代性實施例，介電層60由例如氮化矽、氧化矽或類似者的無機介電材料形成。形成方法可包括化學氣相沈積(Chemical Vapor Deposition；CVD)、原子層沈積(Atomic Layer Deposition；ALD)、電漿增強型化學氣相沈積(Plasma-Enhanced Chemical Vapor Deposition；PECVD)或其他可適用的沈積法。舉例來說，藉由黃光微影製程，接著於介電層60中形成開口(被特徵62所佔)，以暴露出下方的導電柱38A以及38B。根據一些實施例，由例如PBO或聚醯亞胺的感光性材料所形成的介電層60，開口的形成涉及使用微影罩幕的曝光，以及顯影步驟。 Figures 9 to 12 show the formation of the front side interconnection structure. The corresponding steps are shown as step 218 in the process flow shown in FIG. 26. FIG. 9 shows the formation of the first Redistribution Line (RDL) layer and the corresponding dielectric layer. Dielectric layer 60 is formed on the packaging components 32A and 32B and the packaging material 46. According to some embodiments of the present disclosure, the dielectric layer 60 is formed of a polymer such as PBO, polyimide, or the like. The forming method includes coating the dielectric layer 60 in a flowable form, and then curing the dielectric layer 60. According to an alternative embodiment of the present disclosure, the dielectric layer 60 is formed of an inorganic dielectric material such as silicon nitride, silicon oxide or the like. The formation method may include chemical vapor deposition (Chemical Vapor Deposition; CVD), atomic layer deposition (Atomic Layer Deposition; ALD), plasma-enhanced chemical vapor deposition (Plasma-Enhanced Chemical Vapor Deposition; PECVD) or other applicable Deposition method. For example, through the yellow light lithography process, an opening (occupied by the feature 62) is then formed in the dielectric layer 60 to expose the conductive pillars 38A and 38B below. According to some embodiments, for the dielectric layer 60 formed of a photosensitive material such as PBO or polyimide, the formation of the opening involves exposure using a lithography mask, and a development step.

接下來，亦如圖9所示，形成重佈線(RDL)62。重佈線62包括延伸至介電層60內以連接至導電柱38A以及38B的通孔，以及在介電層60上的金屬跡線(金屬線)。根據本揭露內容的一些實施例，重佈線62在鍍覆製程中形成，所述製程包括沈積金屬晶種層，於金屬晶種層上形成光阻並圖案化之，以及於金屬晶種層上鍍覆金屬材料(例如，銅及/或鋁)。金屬晶種層以及所鍍覆的金屬材料可由相同金屬或不同金屬形成。接著移除圖案化的光阻，接著蝕刻被先前經圖案化的光阻所覆蓋的部分金屬晶種層。 Next, as also shown in FIG. 9, a rewiring (RDL) 62 is formed. The rewiring 62 includes through holes extending into the dielectric layer 60 to connect to the conductive pillars 38A and 38B, and metal traces (metal lines) on the dielectric layer 60. According to some embodiments of the present disclosure, the rewiring 62 is formed in a plating process including depositing a metal seed layer, forming a photoresist on the metal seed layer and patterning it, and on the metal seed layer Plating metal materials (for example, copper and/or aluminum). The metal seed layer and the metal material plated may be formed of the same metal or different metals. Then the patterned photoresist is removed, and then part of the metal seed layer covered by the previously patterned photoresist is etched.

由於鍍覆製程，重佈線62的金屬線部分可能不平坦，且直接形成在通孔部分上的重佈線62的金屬線部分可具有凹口(凹陷)，如由示意性繪示的虛線62A所示。此外，通孔部分與重 佈線62的金屬線部分之間不會有可區分的界面。雖未繪示，但在圖14以及圖22中繪示的隨後形成的重佈線62、66以及70可具有類似凹陷，這表示重佈線62、66以及70是在點膠包封材料46以及底填充劑42之後形成。 Due to the plating process, the metal line portion of the rewiring 62 may not be flat, and the metal line portion of the rewiring 62 directly formed on the through hole portion may have a notch (recess), as shown by the dashed line 62A schematically. Show. In addition, the through hole There will be no distinguishable interface between the metal line portions of the wiring 62. Although not shown, the redistribution lines 62, 66, and 70 that are subsequently formed shown in FIGS. 14 and 22 may have similar depressions, which means that the redistribution lines 62, 66, and 70 are formed on the encapsulating material 46 and the bottom of the glue. The filler 42 is formed later.

於介電層60以及重佈線62上形成介電層64。介電層64可使用選自用於形成介電層60的相同候選材料的材料來形成，所述材料可包括PBO、聚醯亞胺、BCB或其他有機或無機材料。 A dielectric layer 64 is formed on the dielectric layer 60 and the rewiring 62. The dielectric layer 64 may be formed using a material selected from the same candidate materials used to form the dielectric layer 60, and the material may include PBO, polyimide, BCB, or other organic or inorganic materials.

接著可在介電層64中形成開口以暴露部分的重佈線62。參照圖10，形成重佈線66。重佈線66亦包括延伸至介電層64中的開口內以接觸重佈線62的通孔部分，以及介電層64上的金屬線部分。重佈線66的形成可與重佈線62的形成相同，其包括形成晶種層、形成經圖案化罩幕、鍍覆重佈線66以及接著移除經圖案化罩幕以及晶種層的不需要的部分。接著形成介電層68。介電層68可由選自用於形成介電層60以及64的相同候選材料群組的材料來形成。 An opening may then be formed in the dielectric layer 64 to expose a portion of the redistribution 62. 10, the rewiring 66 is formed. The rewiring 66 also includes a through hole portion extending into the opening in the dielectric layer 64 to contact the rewiring 62 and a metal line portion on the dielectric layer 64. The formation of the rewiring 66 can be the same as the formation of the rewiring 62, which includes forming a seed layer, forming a patterned mask, plating the rewiring 66, and then removing the unnecessary patterns of the patterned mask and the seed layer. section. Next, a dielectric layer 68 is formed. The dielectric layer 68 may be formed of a material selected from the same candidate material group used to form the dielectric layers 60 and 64.

圖11示出重佈線70的形成。重佈線70亦可由包括鋁、銅、鎢或其合金的金屬或金屬合金形成。應瞭解，儘管在繪示的例示性實施例中形成三層重佈線(62、66以及70)，但所述封裝體可具有任何數量的重佈線層，例如，一層、兩層或多於三層。 FIG. 11 shows the formation of the rewiring 70. The rewiring 70 may also be formed of a metal or metal alloy including aluminum, copper, tungsten, or alloys thereof. It should be understood that although three layers of rewiring (62, 66, and 70) are formed in the illustrated exemplary embodiment, the package may have any number of rewiring layers, for example, one layer, two layers, or more than three layers. Floor.

圖12示出根據一些例示性實施例的介電層72、凸塊下金屬(Under-Bump Metallurgy；UBM)74以及電連接件76的形成。介電層72可由選自用於形成介電層60、64以及68的相同候選材料群組的材料來形成。舉例而言，介電層72可使用PBO、聚 醯亞胺或BCB形成。開口形成於介電層72中以暴露下方的金屬接墊，在例示性的實施例中，所述金屬接墊為重佈線70的部分。根據本揭露內容的一些實施例，形成UBM 74以延伸至介電層72中的開口內。UBM 74可由鎳、銅、鈦或其多層形成。根據一些例示性實施例，UBM 74包括鈦層以及在鈦層上的銅層。 FIG. 12 illustrates the formation of a dielectric layer 72, an under-bump metallurgy (UBM) 74, and electrical connections 76 according to some exemplary embodiments. The dielectric layer 72 may be formed of a material selected from the same candidate material group used to form the dielectric layers 60, 64, and 68. For example, the dielectric layer 72 can use PBO, poly Formation of imine or BCB. Openings are formed in the dielectric layer 72 to expose the underlying metal pads. In an exemplary embodiment, the metal pads are part of the rewiring 70. According to some embodiments of the present disclosure, the UBM 74 is formed to extend into the opening in the dielectric layer 72. The UBM 74 may be formed of nickel, copper, titanium, or multiple layers thereof. According to some exemplary embodiments, UBM 74 includes a titanium layer and a copper layer on the titanium layer.

接著形成電連接件76。電連接件76的形成可包括在UBM 74的經暴露部分上鍍覆非焊料(例如，銅)金屬柱，鍍覆焊料層，以及接著回焊焊料層76。根據本揭露內容的替代性實施例，電連接件76的形成包括進行鍍覆步驟以在UBM 74上直接形成焊料層，並接著回焊焊料層。 Next, an electrical connector 76 is formed. The formation of the electrical connector 76 may include plating a non-solder (for example, copper) metal post on the exposed portion of the UBM 74, plating a solder layer, and then reflowing the solder layer 76. According to an alternative embodiment of the present disclosure, the formation of the electrical connector 76 includes performing a plating step to directly form a solder layer on the UBM 74, and then reflow the solder layer.

根據本揭露內容的一些實施例，將複合晶圓54自載體50(圖12)剝離，其中所得的晶圓54繪示於圖13中。複合晶圓54可附著至切割膠帶。複合晶圓54包括彼此相同的多個封裝體54'，其中每一個封裝體54'包括封裝組件32A以及32B。接著經由晶粒切割將複合晶圓54單體化為多個分離的封裝體54'。將相應的步驟繪示為圖26所示的製程流程中的步驟220。 According to some embodiments of the present disclosure, the composite wafer 54 is peeled from the carrier 50 (FIG. 12 ), and the resulting wafer 54 is shown in FIG. 13. The composite wafer 54 may be attached to a dicing tape. The composite wafer 54 includes a plurality of package bodies 54 ′ that are identical to each other, and each package body 54 ′ includes package components 32A and 32B. Then, the composite wafer 54 is singulated into a plurality of separated packages 54' through die dicing. The corresponding steps are shown as step 220 in the process flow shown in FIG. 26.

圖14示出將封裝體54'接合至封裝組件80上，藉此形成封裝體84。將相應的步驟繪示為圖26所示的製程流程中的步驟222。所述接合藉由電連接件76以及焊料區域78來進行。根據本揭露內容的一些實施例，封裝組件80為封裝基底，其可為無核心基底或具有核心的基底。根據本揭露內容的其他實施例，封裝組件80包括印刷電路板或封裝體。 FIG. 14 shows that the package 54 ′ is bonded to the package assembly 80, thereby forming the package 84. The corresponding steps are shown as step 222 in the process flow shown in FIG. 26. The bonding is performed by the electrical connection member 76 and the solder area 78. According to some embodiments of the present disclosure, the packaging component 80 is a packaging substrate, which may be a coreless substrate or a substrate with a core. According to other embodiments of the present disclosure, the package component 80 includes a printed circuit board or a package body.

圖25示出如圖14所示的封裝體84中的區域86的放大圖。根據本揭露內容的一些實施例，包封材料46包括基質材料46A 以及基質材料46A中的填充劑粒子46B。另外，底填充劑42可包括基質材料42A以及基質材料42A中的填充劑粒子42B。填充劑粒子42B以及46B可具有球形形狀，且可由例如二氧化矽的介電材料形成。由於面向封裝組件32A以及32B(包括導電柱38A以及38B)的部分底填充劑42的未被CMP或機械研磨平坦化，因此與封裝組件32A以及32B所示的頂表面以及垂直邊緣接觸的球形粒子42B具有球形表面。相較之下，與介電層60接觸的部分包封材料46以及底填充劑42已在圖8所示的步驟中被平坦化。因此，與介電層60接觸的球形顆粒42B以及46B在平坦化期間被部分切割，從而與介電層60接觸的球形顆粒42B以及46B具有實質上平坦的頂表面(而非圓的頂表面)。另一方面，內球形顆粒42B以及46B並未被平坦化，其保持具有非平坦(例如，球形)表面的原始形狀。在全文中，在平坦化中被研磨的粒子42B以及46B被稱作部分粒子。另外，封裝體84的底部的部分包封材料46已在圖6所示的步驟中平坦化。因此，封裝體84的底表面處的球形顆粒46B在平坦化期間被部分切割，且因此具有實質上平坦的底表面(而非圓的底表面)。 FIG. 25 shows an enlarged view of the area 86 in the package 84 shown in FIG. 14. According to some embodiments of the present disclosure, the encapsulating material 46 includes a matrix material 46A And filler particles 46B in the matrix material 46A. In addition, the underfill 42 may include a matrix material 42A and filler particles 42B in the matrix material 42A. The filler particles 42B and 46B may have a spherical shape, and may be formed of a dielectric material such as silicon dioxide. Since part of the underfill 42 facing the package components 32A and 32B (including the conductive posts 38A and 38B) is not planarized by CMP or mechanical polishing, the spherical particles contacting the top surface and vertical edges of the package components 32A and 32B 42B has a spherical surface. In contrast, the part of the encapsulating material 46 and the underfill 42 in contact with the dielectric layer 60 have been planarized in the step shown in FIG. 8. Therefore, the spherical particles 42B and 46B in contact with the dielectric layer 60 are partially cut during planarization, so that the spherical particles 42B and 46B in contact with the dielectric layer 60 have substantially flat top surfaces (rather than round top surfaces) . On the other hand, the inner spherical particles 42B and 46B are not flattened, and they maintain the original shape having a non-flat (for example, spherical) surface. In the entire text, the particles 42B and 46B polished during the flattening are called partial particles. In addition, part of the encapsulating material 46 on the bottom of the package body 84 has been planarized in the step shown in FIG. 6. Therefore, the spherical particles 46B at the bottom surface of the package body 84 are partially cut during planarization, and thus have a substantially flat bottom surface (rather than a round bottom surface).

亦如圖14所示，底填充劑42的上部部分寬於底填充劑42的相應的下部部分。根據一些實施例，如虛線42'所示，平坦化可使鄰近封裝組件32A的部分底填充劑42與鄰近封裝組件32B的部分底填充劑42斷開。另外，虛線42'亦繪示出若從圖14中的包含線B-B的平面所獲得的底填充劑42的橫截面圖的形狀。 As also shown in FIG. 14, the upper portion of the underfill 42 is wider than the corresponding lower portion of the underfill 42. According to some embodiments, as shown by the dashed line 42', the planarization may disconnect a portion of the underfill 42 adjacent to the package component 32A from the portion of the underfill 42 adjacent to the package component 32B. In addition, the dashed line 42' also depicts the shape of the cross-sectional view of the underfill 42 obtained from the plane including the line B-B in FIG. 14.

圖15至圖22示出根據本揭露內容的一些實施例的InFO封裝體的形成的中間階段的橫截面圖。圖15至圖22中所繪示的 步驟亦示意性地說明於圖27的製程流程300中。這些實施例類似於圖1至圖14所繪示的實施例，除了封裝組件的導電柱是被插入至膜內而不是接合在金屬接墊上。除非另有說明，否則這些實施例中的組件的材料以及形成方法基本上與圖1至圖14所繪示的實施例中的相同的元件標號所表示的相同的組件相同。因此，可以在圖1至圖14所示的實施例的敘述中找到關於圖15至圖22中所示的組件的形成製程以及材料的細節。 15-22 illustrate cross-sectional views of an intermediate stage of the formation of an InFO package according to some embodiments of the present disclosure. Shown in Figure 15 to Figure 22 The steps are also schematically illustrated in the process flow 300 of FIG. 27. These embodiments are similar to the embodiments depicted in FIGS. 1-14, except that the conductive posts of the package assembly are inserted into the film instead of being bonded to the metal pads. Unless otherwise specified, the materials and forming methods of the components in these embodiments are basically the same as the same components denoted by the same component numbers in the embodiments shown in FIGS. 1 to 14. Therefore, details about the forming process and materials of the components shown in FIGS. 15-22 can be found in the description of the embodiments shown in FIGS. 1-14.

參照圖15，模板膜23形成或附著於載體20上。將相應的步驟繪示為圖27所示的製程流程中的步驟302。模板膜23可為附著於或塗佈於載體20上的預先形成的膜。模板膜23可由其中無導電性特徵、金屬特徵等的均質材料所形成。模板膜23可由黏著膜所形成，黏著膜可以是用以將裝置晶粒附著至其他表面的晶粒附著膜(Die-Attach film)。根據本揭露內容的一些實施例，LTHC層22塗佈於載體20上，且模板膜23形成於LTHC層22上且可與LTHC層22接觸。根據本揭露內容的替代性實施例，LTHC層22並未形成，而模板膜23與載體20接觸。 Referring to FIG. 15, the template film 23 is formed or attached to the carrier 20. The corresponding steps are shown as step 302 in the process flow shown in FIG. 27. The template film 23 may be a pre-formed film attached or coated on the carrier 20. The template film 23 may be formed of a homogeneous material without conductive features, metallic features, and the like. The template film 23 may be formed of an adhesive film, and the adhesive film may be a die-attach film for attaching device dies to other surfaces. According to some embodiments of the present disclosure, the LTHC layer 22 is coated on the carrier 20, and the template film 23 is formed on the LTHC layer 22 and can be in contact with the LTHC layer 22. According to an alternative embodiment of the present disclosure, the LTHC layer 22 is not formed, and the template film 23 is in contact with the carrier 20.

參照圖16，將封裝組件32A以及32B拾取且置放於模板膜23上。將相應的步驟繪示為圖27所示的製程流程中的步驟304。導電柱38A以及38B至少與模板膜23接觸。可對封裝組件32A以及32B施加輕微的力道，使得導電柱38A以及38B延伸至模板膜23內，並使得封裝組件32A以及32B的位置固定於模板膜23上。舉例而言，導電柱38A以及38B可延伸至模板膜23的厚度的約20%至約80%。如圖16中所繪示，導電柱38A的長度可與導電柱38B的長度不同。藉由將封裝組件32A以及32B面向下置 放，導電柱38A的底表面與38B的底表面實質上對齊至同一水平面。根據本揭露內容的一些實施例，圖16所示的製程步驟處於晶圓級。因此，存在與包括封裝組件32A以及32B的裝置群組相同的多個裝置群組置放於模板膜23上。如圖16所示，封裝組件32A的頂表面以及封裝組件32B的頂表面可以處於同一平面或可以不處於同一平面。 Referring to FIG. 16, the packaging components 32A and 32B are picked up and placed on the template film 23. The corresponding steps are shown as step 304 in the process flow shown in FIG. 27. The conductive pillars 38A and 38B are in contact with at least the template film 23. A slight force can be applied to the packaging components 32A and 32B, so that the conductive posts 38A and 38B extend into the template film 23 and the positions of the packaging components 32A and 32B are fixed on the template film 23. For example, the conductive pillars 38A and 38B may extend to about 20% to about 80% of the thickness of the template film 23. As shown in FIG. 16, the length of the conductive pillar 38A may be different from the length of the conductive pillar 38B. By placing the package components 32A and 32B face down The bottom surface of the conductive pillar 38A and the bottom surface of the conductive column 38B are substantially aligned to the same horizontal plane. According to some embodiments of the present disclosure, the process steps shown in FIG. 16 are at the wafer level. Therefore, there are a plurality of device groups that are the same as the device group including the package components 32A and 32B to be placed on the template film 23. As shown in FIG. 16, the top surface of the packaging component 32A and the top surface of the packaging component 32B may be on the same plane or may not be on the same plane.

參照圖17，舉例而言，自裝置群組的一側點膠底填充劑42。將相應的步驟繪示為圖27所示的製程流程中的步驟306。底填充劑42流動至模板膜23、封裝組件32A與封裝組件32B之間的間隙內。底填充劑42的材料與組成可與圖1至圖14所示的實施例所敘述的材料與組成相同，且可包括基質材料42A以及填充劑粒子42B，如圖25中所繪示。 Referring to FIG. 17, for example, an underfill 42 is dispensed from one side of the device group. The corresponding steps are shown as step 306 in the process flow shown in FIG. 27. The underfill 42 flows into the gap between the template film 23, the packaging component 32A, and the packaging component 32B. The material and composition of the underfill 42 may be the same as those described in the embodiment shown in FIGS. 1 to 14, and may include a matrix material 42A and filler particles 42B, as shown in FIG. 25.

接下來，將封裝組件32A以及32B包封在包封材料46中，如圖18所示。將相應的步驟繪示為圖27所示的製程流程中的步驟308。包封材料46亦可包括基質材料(其可為聚合物、樹脂、環氧樹脂或類似者)，以及基質材料中的填充劑粒子，其在圖25中分別繪示為46A以及46B。 Next, the packaging components 32A and 32B are encapsulated in the encapsulating material 46, as shown in FIG. 18. The corresponding steps are shown as step 308 in the process flow shown in FIG. 27. The encapsulating material 46 may also include a matrix material (which may be a polymer, resin, epoxy resin, or the like), and filler particles in the matrix material, which are shown as 46A and 46B in FIG. 25, respectively.

在後續步驟中，如圖19所示，進行例如CMP步驟或機械研磨步驟的平坦化步驟以薄化包封材料，直至暴露處一個或兩個封裝組件32A以及32B。將相應的步驟繪示為圖27所示的製程流程中的步驟310。根據替代性實施例，在結束平坦化之後，封裝組件32A以及32B中的一者未暴露出來，且其被包封材料層的剩餘層直接覆蓋。根據本揭露內容的一些實施例，可以是矽基底的基底34A以及34B被暴露出來。由於平坦化製程，封裝組件32A 以及32B的頂表面與包封材料46的頂表面實質上齊平(共平面)。從而形成複合晶圓54。 In the subsequent step, as shown in FIG. 19, a planarization step such as a CMP step or a mechanical polishing step is performed to thin the encapsulation material until one or two encapsulation components 32A and 32B are exposed. The corresponding steps are shown as step 310 in the process flow shown in FIG. 27. According to an alternative embodiment, after the planarization is finished, one of the packaging components 32A and 32B is not exposed, and it is directly covered by the remaining layer of the encapsulating material layer. According to some embodiments of the present disclosure, the substrates 34A and 34B, which may be silicon substrates, are exposed. Due to the planarization process, the package component 32A And the top surface of 32B and the top surface of the encapsulating material 46 are substantially flush (coplanar). Thus, a composite wafer 54 is formed.

圖20示出載體調換。將相應的步驟繪示為圖27所示的製程流程中的步驟312。在載體調換期間，載體50例如藉由離型膜52附著至複合晶圓54所示的表面。載體50附著至複合晶圓54的一側，其相對於載體20(如圖19所示)。接下來，自載體20剝離封裝組件32A、32B以及包封材料46(如圖19所示)。根據本揭露內容的一些實施例，所述剝離包括分解LTHC層22，其包括在LTHC層22上投射例如雷射光束的載熱輻射。若模板膜23直接配置在載體50上，則模板膜23可以是熱離型膜，其在升高的溫度下膨脹，並因此與載體20分離。因此，複合晶圓54自載體20剝離(卸下)。所得結構繪示於圖20中。 Figure 20 shows carrier swapping. The corresponding steps are shown as step 312 in the process flow shown in FIG. 27. During the carrier exchange, the carrier 50 is attached to the surface shown on the composite wafer 54 by, for example, a release film 52. The carrier 50 is attached to one side of the composite wafer 54 opposite to the carrier 20 (as shown in FIG. 19). Next, the packaging components 32A, 32B and the packaging material 46 are peeled off from the carrier 20 (as shown in FIG. 19). According to some embodiments of the present disclosure, the stripping includes decomposing the LTHC layer 22, which includes projecting heat-carrying radiation such as a laser beam on the LTHC layer 22. If the template film 23 is directly disposed on the carrier 50, the template film 23 may be a thermal release film, which expands at an elevated temperature, and thus is separated from the carrier 20. Therefore, the composite wafer 54 is peeled (detached) from the carrier 20. The resulting structure is shown in Figure 20.

模板膜23可具有附著至導電柱38A以及38B的一些殘餘部分。接下來，進行例如CMP或機械研磨的平坦化步驟以移除模板膜23的殘餘部分，並平坦化導電柱38A以及38B的表面。將相應的步驟繪示為圖27所示的製程流程中的步驟314。導電柱38A以及38B的頂表面因此與包封材料46以及底填充劑42的頂表面共平面。 The template film 23 may have some residual parts attached to the conductive pillars 38A and 38B. Next, a planarization step such as CMP or mechanical polishing is performed to remove the remaining part of the template film 23 and planarize the surfaces of the conductive pillars 38A and 38B. The corresponding steps are shown as step 314 in the process flow shown in FIG. 27. The top surfaces of the conductive pillars 38A and 38B are therefore coplanar with the top surfaces of the encapsulation material 46 and the underfill 42.

後續步驟基本上與圖9至圖13所繪示的步驟相同，其中形成前側內連結構，且所得結構繪示於圖22中。將相應的步驟繪示為圖27所示的製程流程中的步驟316。如圖22所示的複合晶圓54類似於圖13中繪示的複合晶圓54，惟以下情況除外：由於沒有焊料區域接合至導電柱38A以及38B，因此在導電柱38A以及38B的側壁上不存在焊料殘餘物。在後續步驟中，將複合晶圓 54單體化成多個相同封裝體54'，其中一個繪示於圖14中。將相應的步驟繪示為圖27所示的製程流程中的步驟318。另外，封裝體54'可接合至封裝組件80，且所得封裝體84亦繪示於圖14中。將相應的步驟繪示為圖27所示的製程流程中的步驟320。 The subsequent steps are basically the same as those shown in FIGS. 9 to 13, in which the front side interconnection structure is formed, and the resulting structure is shown in FIG. 22. The corresponding steps are shown as step 316 in the process flow shown in FIG. 27. The composite wafer 54 shown in FIG. 22 is similar to the composite wafer 54 shown in FIG. 13, except for the following cases: Since there is no solder area bonded to the conductive pillars 38A and 38B, the sidewalls of the conductive pillars 38A and 38B are There is no solder residue. In the next step, the composite wafer 54 is singulated into multiple identical packages 54 ′, one of which is shown in FIG. 14. The corresponding steps are shown as step 318 in the process flow shown in FIG. 27. In addition, the package 54' can be bonded to the package component 80, and the resulting package 84 is also shown in FIG. 14. The corresponding steps are shown as step 320 in the process flow shown in FIG. 27.

在以上說明的例示性實施例中，根據本揭露內容的一些實施例論述一些例示性製程以及特徵。還可包括其他特徵及製程。舉例來說，可包括測試結構以說明進行三維(3D)封裝體或三維積體電路裝置的驗證測試。測試結構可包括例如形成於重佈線層中或基底上的測試墊，所述測試墊使得能夠測試3D封裝體或3DIC、使用探針(probe)及/或探針卡(probe card)等。可對中間結構及最終結構執行驗證測試。另外，本文中所公開的結構及方法可接合包括對已知良好晶粒(known good dies)的中間驗證的測試方法一起使用，以提高良率(yield)及降低成本。 In the exemplary embodiments described above, some exemplary processes and features are discussed according to some embodiments of the present disclosure. It may also include other features and processes. For example, a test structure may be included to illustrate the verification test of a three-dimensional (3D) package or a three-dimensional integrated circuit device. The test structure may include, for example, test pads formed in the redistribution layer or on the substrate, the test pads enabling testing of 3D packages or 3DIC, using probes and/or probe cards, and the like. Verification tests can be performed on the intermediate structure and the final structure. In addition, the structure and method disclosed herein can be used in conjunction with a test method including intermediate verification of known good dies to improve yield and reduce cost.

本揭露內容的實施例具有一些有利特徵。在習知InFO封裝體的形成中，封裝組件(例如，裝置晶粒)的背表面藉由晶粒附著膜附著至離型膜，且裝置晶粒中的導電柱面向上。接著包封封裝組件，且形成RDL以連接至導電柱。應該理解，雖然封裝組件有意地製造成具有相同厚度，但仍存在製程變化，從而導致封裝組件的厚度變化。舉例而言，HBM立方體(cube)的厚度可具有±25μm的變化。所述變化導致RDL的形成的困難。根據本揭露內容的一些實施例，封裝組件的導電柱可藉由焊料接合至金屬接墊，或者是經由附著至模板膜而被對齊至同一平面。導電柱的長度的差異與封裝組件的厚度的差異因此得到了補償。製程裕度因此增加。 The embodiments of the present disclosure have some advantageous features. In the formation of the conventional InFO package, the back surface of the package component (for example, the device die) is attached to the release film by the die attach film, and the conductive pillars in the device die face upward. The package component is then encapsulated, and an RDL is formed to connect to the conductive pillar. It should be understood that although the package components are deliberately manufactured to have the same thickness, there are still manufacturing process variations, resulting in variations in the thickness of the package components. For example, the thickness of the HBM cube may have a variation of ±25 μm. The changes cause difficulties in the formation of RDL. According to some embodiments of the present disclosure, the conductive pillars of the package component may be bonded to the metal pads by solder, or aligned to the same plane by being attached to the template film. The difference in the length of the conductive pillar and the difference in the thickness of the package component are thus compensated. The process margin is therefore increased.

根據本揭露內容的一些實施例，一種方法包括：將第一封裝組件以及第二封裝組件置放在載體上，其中第一封裝組件的第一導電柱以及第二封裝組件的第二導電柱面向載體；將第一封裝組件以及第二封裝組件包封在包封材料中；將第一封裝組件以及第二封裝組件自載體剝離；平坦化第一導電柱、第二導電柱以及包封材料；以及形成重佈線以電耦接至第一導電柱以及第二導電柱。在一實施例中，當進行包封時，將第一導電柱以及第二導電柱的表面實質上對齊至同一平面。在一實施例中，所述方法更包括在載體與第一封裝組件之間以及在載體與第二封裝組件之間點膠底填充劑，其中在平坦化中，底填充劑亦被平坦化。在一實施例中，所述方法更包括：在載體上形成多個金屬接墊；將第一導電柱以及第二導電柱接合至多個金屬接墊；以及自第一導電柱以及第二導電柱移除多個金屬接墊。在一實施例中，所述移除包括對多個金屬接墊進行化學機械拋光或機械研磨。在一實施例中，所述方法更包括在載體上形成模板膜，其中將第一導電柱以及第二導電柱插入至模板膜內；以及移除模板膜。在一實施例中，移除模板膜包括對模板膜進行化學機械拋光或機械研磨。 According to some embodiments of the present disclosure, a method includes: placing a first package component and a second package component on a carrier, wherein the first conductive post of the first package component and the second conductive post of the second package component face Carrier; encapsulating the first packaging component and the second packaging component in the packaging material; peeling the first packaging component and the second packaging component from the carrier; planarizing the first conductive pillar, the second conductive pillar and the packaging material; And forming a redistribution line to be electrically coupled to the first conductive pillar and the second conductive pillar. In one embodiment, when the encapsulation is performed, the surfaces of the first conductive pillar and the second conductive pillar are substantially aligned to the same plane. In one embodiment, the method further includes dispensing an underfill between the carrier and the first packaging component and between the carrier and the second packaging component, wherein in the planarization, the underfill is also planarized. In one embodiment, the method further includes: forming a plurality of metal pads on the carrier; bonding the first conductive pillar and the second conductive pillar to the plurality of metal pads; and from the first conductive pillar and the second conductive pillar Remove multiple metal pads. In one embodiment, the removing includes chemical mechanical polishing or mechanical polishing on a plurality of metal pads. In one embodiment, the method further includes forming a template film on the carrier, wherein the first conductive column and the second conductive column are inserted into the template film; and the template film is removed. In one embodiment, removing the template film includes chemical mechanical polishing or mechanical grinding of the template film.

根據本揭露內容的一些實施例，一種方法包括：在載體上形成多個金屬接墊；將第一封裝組件的第一導電柱以及第二封裝組件的第二導電柱接合至多個金屬接墊；在第一封裝組件以及第二封裝組件下點膠底填充劑；將第一封裝組件以及第二封裝組件包封在包封材料中，以形成複合晶圓；將複合晶圓自載體剝離；以及對第一封裝組件與第二封裝組件、底填充劑以及包封材料進行第一平坦化，以移除多個金屬接墊。在一實施例中，第一導電 柱以及第二導電柱藉由焊料區域接合至多個金屬接墊。在一實施例中，在第一平坦化後，移除焊料區域以暴露第一導電柱以及第二導電柱的表面。在一實施例中，在第一平坦化後，焊料區域的殘餘部分留在第一導電柱以及第二導電柱中的一者的側壁上。在一實施例中，所述方法更包括在剝離前，對包封材料進行第二平坦化，以暴露第一封裝組件以及第二封裝組件中的至少一者。在一實施例中，所述方法更包括當形成多個金屬接墊時，形成多個導引帶，其中多個導引帶引導底填充劑自第一封裝組件流動至第二封裝組件。在一實施例中，所述方法更包括在第一平坦化中移除多個導引帶。 According to some embodiments of the present disclosure, a method includes: forming a plurality of metal pads on a carrier; bonding a first conductive pillar of a first package component and a second conductive pillar of a second package component to the plurality of metal pads; Dispense underfill under the first package component and the second package component; encapsulate the first package component and the second package component in the encapsulating material to form a composite wafer; peel the composite wafer from the carrier; and The first package component and the second package component, the underfill and the encapsulation material are first planarized to remove a plurality of metal pads. In one embodiment, the first conductive The pillars and the second conductive pillars are joined to a plurality of metal pads by solder regions. In one embodiment, after the first planarization, the solder region is removed to expose the surfaces of the first conductive pillar and the second conductive pillar. In one embodiment, after the first planarization, the remaining part of the solder region remains on the sidewall of one of the first conductive pillar and the second conductive pillar. In one embodiment, the method further includes performing a second planarization on the encapsulating material before peeling off, so as to expose at least one of the first packaging component and the second packaging component. In one embodiment, the method further includes forming a plurality of guide strips when forming the plurality of metal pads, wherein the plurality of guide strips guide the underfill to flow from the first package component to the second package component. In an embodiment, the method further includes removing a plurality of guiding tapes in the first planarization.

根據本揭露內容的一些實施例，一種封裝體包括：第一封裝組件以及第二封裝組件；將第一封裝組件以及第二封裝組件包封在其中的包封材料；配置在包封材料上且與其接觸的介電層；底填充劑包括：第一部分與第二部分，第一部分配置在第一封裝組件與介電層之間，其中第一封裝組件的第一導電柱在底填充劑中，且底填充劑的上部部分寬於底填充劑的下部部分，第二部分配置在第二封裝組件與介電層之間，其中第二封裝組件的第二導電柱在底填充劑中；以及重佈線，其延伸至介電層內，以接觸第一導電柱以及第二導電柱。在一實施例中，第一導電柱與第二導電柱具有不同長度。在一實施例中，底填充劑包括：第一球形粒子；以及接觸介電層的第一部分粒子。在一實施例中，包封材料包括：第二球形粒子；以及接觸介電層的第二部分粒子。在一實施例中，第一封裝組件包括裝置晶粒。在一實施例中，底填充劑橫向延伸超出第一封裝組件的邊緣。 According to some embodiments of the present disclosure, a package includes: a first package component and a second package component; an encapsulation material encapsulating the first package component and the second package component; and is arranged on the encapsulation material and The dielectric layer in contact with it; the underfill includes: a first part and a second part, the first part is disposed between the first package component and the dielectric layer, wherein the first conductive pillar of the first package component is in the underfill, And the upper part of the underfill is wider than the lower part of the underfill, the second part is disposed between the second packaging component and the dielectric layer, wherein the second conductive pillar of the second packaging component is in the underfill; and The wiring extends into the dielectric layer to contact the first conductive pillar and the second conductive pillar. In an embodiment, the first conductive pillar and the second conductive pillar have different lengths. In an embodiment, the underfill includes: first spherical particles; and a first portion of particles contacting the dielectric layer. In an embodiment, the encapsulating material includes: second spherical particles; and a second portion of particles contacting the dielectric layer. In an embodiment, the first package component includes a device die. In one embodiment, the underfill extends laterally beyond the edge of the first package component.

以上概述若干實施例的特徵，以使得本領域的技術人員可較好地理解本揭露內容的態樣。本領域的技術人員應理解，其可易於使用本揭露內容作為設計或修改用於實現本文中所引入之實施例的相同目的且/或達成相同優點的其他方法及結構的基礎。本領域的技術人員亦應認識到，此類等效構造並不脫離本揭露內容之精神及範疇，且本領域的技術人員可在不脫離本揭露內容的精神及範疇之情況下在本文中作出各種改變、替代及更改。 The above summarizes the features of several embodiments, so that those skilled in the art can better understand the aspect of the disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other methods and structures for achieving the same purpose and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent structures do not depart from the spirit and scope of the disclosure, and those skilled in the art can make in this article without departing from the spirit and scope of the disclosure. Various changes, substitutions and alterations.

200:製程流程 200: Process flow

202、204、206、208、210、212、214、216、218、220、222:步驟 202, 204, 206, 208, 210, 212, 214, 216, 218, 220, 222: steps

Claims (10)

一種封裝體的製造方法，包括：將第一封裝組件以及第二封裝組件置放在載體上，其中所述第一封裝組件的第一導電柱以及所述第二封裝組件的第二導電柱面向所述載體；將所述第一封裝組件以及所述第二封裝組件包封在包封材料中；將所述第一封裝組件以及所述第二封裝組件自所述載體剝離，其中所述剝離包括投射光以分解與所述載體接合至所述第一封裝組件的離型膜；在所述剝離之後，平坦化所述第一導電柱、所述第二導電柱以及所述包封材料；以及形成重佈線以電耦接至所述第一導電柱以及所述第二導電柱。 A manufacturing method of a package body includes: placing a first package component and a second package component on a carrier, wherein the first conductive post of the first package component and the second conductive post of the second package component face The carrier; encapsulating the first packaging component and the second packaging component in an encapsulating material; peeling the first packaging component and the second packaging component from the carrier, wherein the peeling Including projecting light to decompose the release film bonded with the carrier to the first packaging component; after the peeling, planarizing the first conductive pillar, the second conductive pillar, and the encapsulating material; And forming a redistribution line to be electrically coupled to the first conductive pillar and the second conductive pillar. 如申請專利範圍第1項所述的封裝體的製造方法，其中當進行所述包封時，將所述第一導電柱的表面與所述第二導電柱的表面實質上對齊至同一平面。 The method for manufacturing a package as described in claim 1, wherein when the encapsulation is performed, the surface of the first conductive pillar and the surface of the second conductive pillar are substantially aligned to the same plane. 如申請專利範圍第1項所述的封裝體的製造方法，更包括在所述載體與所述第一封裝組件之間以及在所述載體與所述第二封裝組件之間點膠底填充劑，其中在所述平坦化中，所述底填充劑亦被平坦化。 The manufacturing method of the package as described in the first item of the scope of the patent application further includes dispensing an underfill between the carrier and the first package component and between the carrier and the second package component , Wherein in the planarization, the underfill is also planarized. 如申請專利範圍第1項所述的封裝體的製造方法，更包括：在所述載體上形成多個金屬接墊； 將所述第一導電柱以及所述第二導電柱接合至所述多個金屬接墊；以及自所述第一導電柱以及所述第二導電柱移除所述多個金屬接墊。 As described in item 1 of the scope of patent application, the method for manufacturing a package body further includes: forming a plurality of metal pads on the carrier; Bonding the first conductive pillar and the second conductive pillar to the plurality of metal pads; and removing the plurality of metal pads from the first conductive pillar and the second conductive pillar. 如申請專利範圍第1項所述的封裝體的製造方法，更包括：在所述載體上形成模板膜，其中將所述第一導電柱以及所述第二導電柱插入至所述模板膜內；以及移除所述模板膜。 The manufacturing method of the package as described in the first item of the scope of the patent application further includes: forming a template film on the carrier, wherein the first conductive pillar and the second conductive pillar are inserted into the template film ; And removing the template film. 一種封裝體的製造方法，包括：在載體上形成多個金屬接墊；將第一封裝組件的第一導電柱以及第二封裝組件的第二導電柱接合至所述多個金屬接墊；在所述第一封裝組件以及所述第二封裝組件下點膠底填充劑；將所述第一封裝組件以及所述第二封裝組件包封在包封材料中，以形成複合晶圓；將所述複合晶圓自所述載體剝離，其中所述剝離包括投射光以分解與所述載體接合至所述複合晶圓的離型膜；以及在所述剝離之後，對所述第一封裝組件、所述第二封裝組件、所述底填充劑以及所述包封材料進行第一平坦化，以移除所述多個金屬接墊。 A method for manufacturing a package includes: forming a plurality of metal pads on a carrier; bonding a first conductive post of a first package component and a second conductive post of a second package component to the multiple metal pads; Dispense underfill under the first package component and the second package component; encapsulate the first package component and the second package component in an encapsulating material to form a composite wafer; The composite wafer is peeled from the carrier, wherein the peeling includes projecting light to decompose the release film bonded with the carrier to the composite wafer; and after the peeling, the first package component, The second packaging component, the underfill and the encapsulating material are first planarized to remove the plurality of metal pads. 如申請專利範圍第6項所述的封裝體的製造方法，更包括當形成所述多個金屬接墊時，形成多個導引帶，其中所述多個 導引帶引導底填充劑自所述第一封裝組件流動至所述第二封裝組件。 The manufacturing method of the package body as described in item 6 of the scope of the patent application further includes forming a plurality of guide strips when forming the plurality of metal pads, wherein the plurality of The guiding tape guides the underfill from the first packaging component to the second packaging component. 如申請專利範圍第7項所述的封裝體的製造方法，更包括在所述第一平坦化中移除所述多個導引帶。 The manufacturing method of the package body as described in item 7 of the scope of the patent application further includes removing the plurality of guide bands in the first planarization. 一種封裝體，包括：第一封裝組件以及第二封裝組件；包封材料，包封所述第一封裝組件以及所述第二封裝組件於其中；介電層，配置在所述包封材料上且接觸所述包封材料；底填充劑，包括：第一部分，配置在所述第一封裝組件與所述介電層之間，其中所述第一封裝組件的第一導電柱位於所述底填充劑中，且所述底填充劑的上部部分寬於所述底填充劑的下部部分；以及第二部分，配置在所述第二封裝組件與所述介電層之間，其中所述第二封裝組件的第二導電柱位於所述底填充劑中；以及重佈線，延伸至所述介電層內，以接觸所述第一導電柱以及所述第二導電柱。 A package body, comprising: a first package component and a second package component; an encapsulation material, which encapsulates the first package component and the second package component therein; and a dielectric layer, which is arranged on the encapsulation material And in contact with the encapsulating material; an under-filler, including: a first part, arranged between the first packaging component and the dielectric layer, wherein the first conductive pillar of the first packaging component is located at the bottom In the filler, and the upper part of the underfill is wider than the lower part of the underfill; and the second part is arranged between the second packaging component and the dielectric layer, wherein the first The second conductive pillars of the two package components are located in the underfill; and the redistribution line extends into the dielectric layer to contact the first conductive pillars and the second conductive pillars. 如申請專利範圍第9項所述的封裝體，其中所述第一導電柱與所述第二導電柱具有不同長度。 The package body according to the 9th patent application, wherein the first conductive pillar and the second conductive pillar have different lengths.
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