TWI743900B - Package structure and manufacturing method thereof - Google Patents

Abstract

A package structure includes a chip, a redistribution circuit layer, a plurality of conductors, a molding compound and a plurality of solder balls. The chip has an active surface and a back surface opposite to each other, and a surrounding surface connecting the active surface and the back surface and includes a plurality of pads. The active surface is divided into a central area and two peripheral areas located on both sides of the central area, and the pads are located in the central area. The redistribution circuit layer is disposed on the active surface of the chip and includes a plurality of circuits and a plurality of connection pads. The connection pads are located on the peripheral areas of the chip. The circuits are connected to the pads and a portion of the connection pads. The conductors are respectively disposed on the connection pads. The molding compound covers the redistribution circuit layer and fills between the conductors, and at least exposes a lower surface of each of the conductors. The solder balls are disposed outside the molding compound and electrically connected to the conductors.

Description

Packaging structure and manufacturing method thereof

The present invention relates to a packaging structure and a manufacturing method thereof, and particularly relates to a wafer level (Wafer level) packaging structure and a manufacturing method thereof.

Generally speaking, the substrate of a window-type BGA (WBGA) package structure has windows penetrating through the upper and lower surfaces, wherein the chip is placed on the substrate through the die-bonding layer and covers the window, and the chip is placed on the window through The inner wire (such as gold wire) is electrically connected to the substrate. Due to the large size of the chip, the packaging glue cannot flow to the lower mold through the window of the substrate, and the glue bubbles/holes/incomplete filling phenomenon are also easily generated in the lower mold. Furthermore, during the packaging process, the mold flow is unstable due to the structure, and the gold wire is easily collapsed, which in turn leads to the problem of short circuit. In addition, because of the large size of the chip, it is easy to cause warpage of the overall package structure.

The present invention provides a package structure without a substrate, window and die-bonding layer design, which can have a thinner package thickness and better structural reliability.

The present invention also provides a manufacturing method of the packaging structure for manufacturing the above-mentioned packaging structure.

The packaging structure of the present invention includes a chip, a reconfiguration circuit layer, a plurality of conductors, a packaging glue and a plurality of solder balls. The chip has an active surface and a back surface opposite to each other, and a peripheral surface connecting the active surface and the back surface, and includes a plurality of pads. The active surface is divided into a central area and two peripheral areas located on both sides of the central area, and the pads are located in the central area. The reconfiguration circuit layer is disposed on the active surface of the chip and includes a plurality of circuits and a plurality of connection pads. The connection pads are located on the peripheral area of the chip. The circuit is connected to the connecting pad and part of the connecting pad. The conductors are respectively arranged on the connection pads. The encapsulant covers the reconfiguration circuit layer and fills between the conductors, and at least exposes the lower surface of each conductor. The solder balls are arranged outside the packaging compound and are electrically connected to the conductors.

In an embodiment of the present invention, each of the aforementioned conductors includes a metal pillar or a metal ball.

In an embodiment of the present invention, the material of the metal pillars mentioned above includes copper, silver, tin or other highly conductive materials.

In an embodiment of the present invention, the material of the aforementioned metal ball includes tin (Sn), lead-free solder, tin-indium (Sn-In), tin-lead (Sn-Pb), tin-bismuth (Sn-Bi), or tin-silver Copper (Sn-Ag-Cu).

In an embodiment of the present invention, the above-mentioned packaging glue covers the peripheral surface of the chip. The packaging glue has a top surface and a bottom surface opposite to each other. The top surface of the packaging compound is cut flush with the back surface of the chip. The bottom surface of the encapsulating body is cut flush with the bottom surface of each conductive body.

In an embodiment of the present invention, the aforementioned packaging structure further includes an additional packaging compound and an additional reconfiguration circuit layer. The additional packaging glue covers the backside of the chip and the packaging glue. An additional bottom surface of the additional packaging glue is cut flush with the bottom surface of the packaging glue. The additional reconfiguration circuit layer is configured on the bottom surface of the packaging glue and the additional bottom surface of the additional packaging glue, and is located between the solder balls and the conductor. The additional reconfiguration circuit layer electrically connects the conductor and the solder balls.

In an embodiment of the present invention, the above-mentioned packaging structure further includes an additional packaging compound having an additional top surface and an additional bottom surface opposite to each other. The additional packaging glue covers the surrounding surface of the chip. The partially reconfigured circuit layer extends out of the active surface of the chip and is arranged on the additional bottom surface of the additional packaging compound.

In an embodiment of the present invention, the aforementioned packaging glue covers the additional top surface of the additional packaging glue and the back surface of the chip.

In an embodiment of the present invention, the aforementioned chip includes a dynamic random access memory.

In an embodiment of the present invention, the above-mentioned encapsulant has a plurality of sides, and a horizontal distance between the peripheral surface of the chip and each side of the encapsulant is the same. This horizontal distance is the shortest distance to block water vapor.

The manufacturing method of the package structure of the present invention includes the following steps. A wafer is provided, and the wafer includes a plurality of chips. Each chip has an active surface and a back surface opposite to each other, and a peripheral surface connecting the active surface and the back surface, and includes a plurality of pads. The active surface is divided into a central area and two peripheral areas located on both sides of the central area, and the pads are located in the central area. A reconfiguration circuit layer is formed on the wafer. The reconfiguration circuit layer is located on the active surface of each chip and includes a plurality of circuits and a plurality of connection pads. The connection pads are located on the peripheral area of each chip. The circuit is connected to the connecting pad and part of the connecting pad. A plurality of conductive bodies are formed on the connection pads respectively. A first singulation process is performed on the wafer to form a plurality of chip units. Each chip unit includes each chip, a reconfiguration circuit layer on the active surface of each chip, and a conductor. A packaging process is performed on the chip unit, so that a packaging glue covers the peripheral surface of each chip and reconfigures the circuit layer, and at least exposes the lower surface of each conductor. A plurality of solder balls are formed outside the packaging body, wherein the solder balls are electrically connected to the conductor. A second singulation process is performed on the packaging compound to form a plurality of packaging structures with solder balls.

In an embodiment of the present invention, the above-mentioned method of forming a conductive body on the connection pad includes an electroplating method, an electroless plating deposition method, a metal bonding etching method, or a reflow soldering ball method.

In an embodiment of the present invention, each of the aforementioned conductors includes a metal pillar or a metal ball.

In an embodiment of the present invention, the material of the metal pillars mentioned above includes copper or other highly conductive materials.

In an embodiment of the present invention, the material of the aforementioned metal ball includes tin (Sn), lead-free solder, tin-indium (Sn-In), tin-lead (Sn-Pb), tin-bismuth (Sn-Bi) or tin Silver copper (Sn-Ag-Cu).

In an embodiment of the present invention, the step of performing the packaging process on the chip unit includes: providing a carrier with an adhesive layer. The chip unit is positioned on the carrier board through the adhesive layer. The adhesive layer is located between the back of each chip and the carrier. A packaging material layer is formed on the carrier. The packaging material layer covers the chip unit and the adhesive layer. A grinding process is performed on the packaging material layer to expose the lower surface of each conductor to form a packaging gel.

In an embodiment of the present invention, after the solder balls are formed outside the package body and before the second singulation process, the adhesive layer and the carrier are removed to expose the backside of each chip.

In an embodiment of the present invention, the aforementioned encapsulant is filled between the conductors. The packaging glue has a top surface and a bottom surface opposite to each other. The top surface of the packaging compound is cut flush with the back surface of the chip. The bottom surface of the encapsulating body is cut flush with the bottom surface of each conductive body.

In an embodiment of the present invention, the aforementioned chip includes a dynamic random access memory.

In an embodiment of the present invention, the above-mentioned encapsulant has a plurality of sides, and a horizontal distance between the peripheral surface of the chip and each side of the encapsulant is the same.

Based on the above, in the design of the package structure of the present invention, the conductors are arranged on the connection pads of the reconfiguration circuit layer, and the pads of the chip can be electrically connected to the solder balls through the reconfiguration circuit layer and the conductors, and the packaging gel is covered The circuit layer is reconfigured and filled between the conductors, and the encapsulant at least exposes the lower surface of the conductors. Thereby, the packaging structure of the present invention does not need to be known in the design of the substrate, the window and the die bonding layer, and the substrate can be replaced by the packaging glue to protect and support the chip. Furthermore, because of the windowless design of the package structure of the present invention, the package per unit area can tolerate the largest chip, which means that the effective use of space can be maximized. In addition, due to the simplification of materials and interfaces, the package structure of the present invention can not only have a better signal transmission effect, but also has a thinner design and can have a thinner package thickness.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

1A to FIG. 1I are schematic diagrams of a manufacturing method of a package structure according to an embodiment of the present invention. For the convenience of description, FIG. 1A shows a partially enlarged top view, and FIG. 1B shows a partially enlarged perspective view, and FIGS. 1C to 1I are shown as cross-sectional views.

Regarding the manufacturing method of the package structure of this embodiment, firstly, referring to FIG. 1A, a wafer 10 is provided, where the wafer 10 includes a plurality of chips 110. In detail, each chip 110 has an active surface 111 and a back surface 113 opposite to each other, and a peripheral surface 115 connecting the active surface 111 and the back surface 113 and includes a plurality of pads 112. The active surface 111 is divided into a central area C and two peripheral areas P located on both sides of the central area C, and the pad 112 is located in the central area C. Here, each chip 110 is, for example, a dynamic random access memory (Dynamic Random Access Memory, DRAM), but it is not limited thereto.

Next, referring to FIG. 1A again, a reconfiguration circuit layer 120 is formed on the wafer 10. In detail, the reconfiguration circuit layer 120 is located on the active surface 111 of each chip 110 and includes at least one insulating layer 122, a plurality of circuits 124 and a plurality of connection pads 126. The insulating layer 122 covers the active surface 111 of the chip 110, and the circuit 124 is buried in the insulating layer 122 and electrically connects the pad 112 of the chip 110 and a part of the connection pad 126. The connection pads 126 are arranged in an array and are aligned on the surface of the insulating layer 122 that is relatively far away from the chip 110. In particular, the connection pad 126 is located on the peripheral area P of the wafer 110. In other words, through the arrangement of the reconfiguration circuit layer 120, the signal of the pad 112 of the chip 110 can be pulled from the central area C to the connection pad 126 in the peripheral area P.

Next, referring to FIG. 1B, a plurality of conductive bodies 130 are formed on the connection pads 126 and arranged in an array. In this embodiment, the method of forming the conductor 130 on the connection pad 126 is, for example, an electroplating method, an electroless plating deposition method, a metal bonding etching method, or a reflow soldering ball method, but it is not limited thereto. Here, the conductor 130 can be used as a signal vertical connection channel, where the conductor 130 is, for example, a metal pillar or a metal ball. Here, a metal pillar is taken as an example for description, where the material of the metal pillar is, for example, copper, silver, tin, or other highly conductive materials, but not limited to this.

Next, referring to FIG. 1B and FIG. 1C at the same time, a first singulation process is performed on the wafer 10 to form a plurality of chip units U (only one is schematically shown in FIG. 1C). That is, the wafer 10 is subjected to grinding and cutting procedures to form a single wafer unit U. Here, each chip unit U includes each chip 110, a reconfiguration circuit layer 120 on the active surface 111 of each chip 110, and a conductor 130.

Next, referring to FIG. 1F, perform a packaging process on the chip unit U so that a packaging compound 140 covers the peripheral surface 115 of each chip 110 and the reconfiguration circuit layer 120, and at least exposes a portion of each conductor 130 Surface 132. In detail, for the steps of the packaging process for the chip unit U, first, referring to FIG. 1D, a carrier 20 with an adhesive layer 30 is provided. Next, a plurality of chip units U that have been selected as good products are positioned on the carrier board 20 through the adhesive layer 30. Here, the adhesive layer 30 is located between the back surface 113 of each chip 110 and the carrier 20, which means that the chip 110 is adhered to the carrier 20 with the active surface 111 facing up. Here, the carrier board 20 is, for example, a glass substrate with a positioning point design, which is cheap and transparent, can confirm the adhesion state of the crystal surface (such as whether there are adhesive bubbles, foreign objects, etc.), and can be reused after cleaning. In one embodiment, the adhesive layer 30 can also be a tape type (such as DAF tape) attached to the backside 113 of the chip 110 so that the chip 110 can be directly aligned and attached to the positioning points on the carrier 20.

Next, referring to FIG. 1E, a packaging material layer 140 a is formed on the carrier 20, wherein the packaging material layer 140 a covers the chip unit U and the adhesive layer 30.

After that, referring to FIG. 1E and FIG. 1F at the same time, perform a grinding process on the packaging material layer 140 a to expose the lower surface 132 of each conductive body 130 to form the packaging glue 140. Here, the encapsulant 140 is filled between the conductive bodies 130. The encapsulant 140 has a top surface 141 and a bottom surface 143 opposite to each other. The top surface 141 of the encapsulant 140 is aligned with the back surface 113 of the chip 110, and the bottom surface 143 of the encapsulant 140 is aligned with the bottom surface 132 of each conductive body 130.

Next, referring to FIG. 1G, a plurality of solder balls 150 are formed outside the encapsulant 140, wherein the solder balls 150 and the conductor 130 are electrically connected. Here, the solder ball 150 is directly structurally and electrically connected to the conductor 130, but it is not limited to this.

After that, referring to FIGS. 1G and 1H at the same time, the adhesive layer 30 and the carrier 20 are removed, and the backside 113 of each chip 110 is exposed.

Finally, referring to FIG. 1H and FIG. 1I at the same time, a second singulation process is performed on the package compound 140 to cut the package compound 140 to form a plurality of package structures 100 a with solder balls 150. So far, the fabrication of the wafer level (wafer level) and ball grid array (Ball Grid Array, BGA) package structure 100a has been completed.

In terms of structure, please refer to FIG. 1I, FIG. 1J and FIG. 1K at the same time. The package structure 100a includes a chip 110, a reconfiguration circuit layer 120, a conductor 130, a package glue 140, and a solder ball 150. The chip 110 has an active surface 111 and a back surface 113 opposite to each other, and a peripheral surface 115 connecting the active surface 111 and the back surface 113 and includes a pad 112. The active surface 111 is divided into a central area C and a peripheral area P located on both sides of the central area C, and the pad 112 is located in the central area C. Here, the chip 110 is, for example, a dynamic random access memory, but it is not limited thereto. The reconfiguration circuit layer 120 is disposed on the active surface 111 of the chip 110 and includes an insulating layer 122, a circuit 124 and a plurality of connection pads 126. The insulating layer 122 covers the active surface 111 of the chip 110, and the circuit 124 is buried in the insulating layer 122 and electrically connects the pad 112 of the chip 110 and a part of the connection pad 126. In particular, the peripheral area P of the connection pad 126 on the active surface 111 of the chip 110 means that the design of the reconfiguration circuit layer 120 in this embodiment belongs to the RDL Re-layout structure. In addition, the reconfiguration circuit layer 120 of this embodiment can be a fan-in design or a fan-out design, which is not limited herein.

Furthermore, the conductors 130 of this embodiment are respectively disposed on the connection pads 126 and can be used as vertical connection channels for signals. Here, the conductor 130 is, for example, a metal pillar, and the material of the metal pillar is, for example, copper, silver, tin, or other highly conductive materials, but not limited to this. The encapsulant 140 covers the peripheral surface 115 of the chip 110 and the reconfiguration circuit layer 120, and exposes the back surface 113 of the chip 110 and the lower surface 132 of the conductor 130. Furthermore, the encapsulant 140 is filled between the conductive bodies 130. The encapsulant 140 has a top surface 141 and a bottom surface 143 opposite to each other. The top surface 141 of the encapsulant 140 is aligned with the back surface 113 of the chip 110, and the bottom surface 143 of the encapsulant 140 is aligned with the bottom surface 132 of each conductive body 130. The encapsulant 140 further has a plurality of side surfaces 145, and a horizontal distance H1, H2 between the peripheral surface 115 of the chip 110 and each side 145 of the encapsulant 140 is the same. The horizontal spacing H1 and H2 can be regarded as the shortest distance to block water vapor, and the thickness of the package body can be designed in accordance with international standards, which can minimize the total thickness of the specifications. The solder ball 150 is disposed outside the encapsulant 140, and the solder ball 150 is structurally and electrically connected to the conductor 130.

Since the back surface 113 of the chip 110 of this embodiment is aligned with the top surface 141 of the encapsulant 140, which means that the encapsulant 140 does not cover the back 113 of the chip 110, the chip 110 of this embodiment can conduct electricity through the conductor 130. In addition to heat transfer, heat can also be dissipated through the back surface 113 of the chip 110. Therefore, the package structure 100a of this embodiment can have a better heat dissipation effect. Furthermore, the conductor 130 of this embodiment can be regarded as a circuit and is electrically connected to the solder ball 150. In addition, the packaging structure 100a of this embodiment does not need to be familiar with the design of the substrate, the window and the die-bonding layer, and the substrate can be replaced by the encapsulant 140 to protect and support the chip 110. Due to the windowless design of the package structure 100a of the present embodiment, the maximum chip per unit area is allowed, which means that the effective use of space can be maximized. In addition, due to the simplification of materials and interfaces, the package structure 100a of the present embodiment can not only have a better signal transmission effect, but also have a thin design, which can have a thinner package thickness.

It must be noted here that the following embodiments use the element numbers and part of the content of the foregoing embodiments, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

2 is a schematic cross-sectional view of a package structure according to an embodiment of the invention. Please refer to FIG. 1I and FIG. 2 at the same time. The package structure 100b of this embodiment is similar to the package structure 100a of FIG. The material of the ball includes tin (Sn) or other low-temperature soldering materials, such as lead-free solder, tin-indium (Sn-In), tin-lead (Sn-Pb), tin-bismuth (Sn-Bi) or tin-silver-copper (Sn- Ag-Cu). Here, the bottom surface 143 of the encapsulant 140 is aligned with the bottom surface 137 of each conductive body 135, and the conductive body 135 is directly structurally and electrically connected to the solder ball 150. In short, the present invention does not limit the structure of the conductors 130 and 135, which can be columnar, spherical or other suitable structure types.

FIG. 3 is a schematic cross-sectional view of a package structure according to another embodiment of the present invention. Please refer to FIG. 1I and FIG. 3 at the same time. The package structure 100c of this embodiment is similar to the package structure 100a of FIG. Reconfigure the circuit layer 170. The additional packaging glue 160c covers the back surface 113 of the chip 110 and the top surface 141 and the side surfaces 145 of the packaging glue 140. An additional bottom surface 163c of the additional packaging glue 160c is aligned with a bottom surface 143 of the packaging glue 140. The additional reconfiguration circuit layer 170 is disposed on the bottom surface 143 of the packaging glue 140 and the additional bottom surface 163c of the additional packaging glue 160c, and is located between the solder balls 150c and the conductor 130. The additional reconfiguration circuit layer 170 is of a fan-out structure, in which the edge of the additional reconfiguration circuit layer 170 is aligned with the edge of the additional packaging glue 160c. The additional reconfiguration circuit layer 170 electrically connects the conductor 130 and the solder ball 150c. The package structure 100c of this embodiment can be applied to a package with a small chip but many external input/output contacts (I/O).

4 is a schematic cross-sectional view of a package structure according to another embodiment of the invention. Please refer to FIG. 1I and FIG. 4 at the same time. The package structure 100d of this embodiment is similar to the package structure 100a of FIG. An additional top surface 161d and an additional bottom surface 163d, and cover the peripheral surface 115 of the wafer 110. The partially reconfigured circuit layer 120 extends from the active surface 111 of the chip 110 and is disposed on the additional bottom surface 163d of the additional packaging compound 160d. The back surface 113 of the chip 110 is aligned with the top surface 141 of the packaging glue 140 and the additional top surface 161d of the additional packaging glue 160d, so that the packaging structure 100d has a better heat dissipation effect. The active surface 111 of the chip 110 is aligned with the additional bottom surface 163d of the additional encapsulation compound 160d, and the edge of the reconfiguration circuit layer 120 is aligned with the edge of the additional encapsulation compound 160d. For example, if the chip 110 has a small area but a large package spec (Package Spec) area, the external input/output contacts (I/O) must be extended, so that there is enough space to accommodate more external inputs/ Demand for outgoing contacts. In production, the additional packaging compound 160d can be formed first, and then the reconfiguration circuit layer 120 is formed, and then the packaging compound 140 is formed to protect the conductor 130 and the chip 110 and the reconfiguration circuit layer 120 to avoid final test (Final Test, FT) is crushed.

FIG. 5 is a schematic cross-sectional view of a package structure according to another embodiment of the present invention. Please refer to FIGS. 4 and 5 at the same time. The packaging structure 100e of this embodiment is similar to the packaging structure 100d of FIG. The top surface 161d and the back surface 113 of the wafer 110 are added. Since the encapsulant 140e of this embodiment completely covers the chip 110 and the additional encapsulant 160d, it has better protection.

In summary, in the design of the package structure of the present invention, the conductors are arranged on the connection pads of the reconfiguration circuit layer, and the chip pads can be electrically connected to the solder balls through the reconfiguration circuit layer and the conductors, and the package The glue covers the reconfiguration circuit layer and is filled between the conductors, and the encapsulation glue at least exposes the lower surface of the conductors. Thereby, the packaging structure of the present invention does not need to be known in the design of the substrate, the window and the die bonding layer, and the substrate can be replaced by the packaging glue to protect and support the chip. Furthermore, because of the windowless design of the package structure of the present invention, the package per unit area can tolerate the largest chip, which means that the effective use of space can be maximized. In addition, due to the simplification of materials and interfaces, the package structure of the present invention can not only have a better signal transmission effect, but also has a thinner design and can have a thinner package thickness.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

10: Wafer 20: Carrier board 30: Adhesive layer 100a, 100b, 100c, 100d, 100e: package structure 110: chip 111: active side 112: pad 113: Back 115: surrounding surface 120: Reconfigure the circuit layer 122: Insulation layer 124: Line 126: connection pad 130, 135: Conductor 132, 137: lower surface 140, 140e: Encapsulation gel 140a: encapsulation material layer 141: top surface 143: Bottom 145: side 150, 150c: solder ball 160c, 160d, 160e: additional packaging glue 161d, 161e: additional top surface 163c, 163d, 163e: additional bottom surface 170: Additional reconfiguration line layer C: Chuo District H1, H2: horizontal spacing P: Surrounding area U: chip unit

1A to FIG. 1I are schematic diagrams of a manufacturing method of a package structure according to an embodiment of the present invention. FIG. 1J is a schematic top view of the package structure of FIG. 1I. FIG. 1K is a schematic bottom view of the package structure of FIG. 1I. 2 is a schematic cross-sectional view of a package structure according to an embodiment of the invention. FIG. 3 is a schematic cross-sectional view of a package structure according to another embodiment of the present invention. 4 is a schematic cross-sectional view of a package structure according to another embodiment of the invention. FIG. 5 is a schematic cross-sectional view of a package structure according to another embodiment of the present invention.

100a: Package structure

110: chip

111: active side

112: pad

113: Back

115: surrounding surface

120: Reconfigure the circuit layer

122: Insulation layer

124: Line

126: connection pad

130: Conductor

132: lower surface

140: Encapsulation colloid

141: top surface

143: Bottom

145: side

150: solder ball

C: Chuo District

P: Surrounding area

Claims (20)

A packaging structure, including: A chip has an active surface and a back surface opposite to each other, and a peripheral surface connecting the active surface and the back surface, and includes a plurality of pads. The active surface is divided into a central area and two sides located on both sides of the central area. Peripheral area, and the pads are located in the central area; A reconfiguration circuit layer is arranged on the active surface of the chip and includes a plurality of circuits and a plurality of connection pads, the connection pads are located on the peripheral area of the chip, and the circuits are connected to the pads and Some of these connecting pads; A plurality of electrical conductors are respectively arranged on the connection pads; An encapsulation glue covering the reconfiguration circuit layer and filling between the conductors, and exposing at least the lower surface of each conductor; and A plurality of solder balls are arranged outside the packaging rubber body and electrically connected with the conductors. The package structure according to claim 1, wherein each of the conductors includes a metal pillar or a metal ball. The package structure according to claim 2, wherein the material of the metal pillar includes copper, silver or tin. The package structure according to claim 2, wherein the material of the metal ball includes tin, lead-free solder, tin indium, tin lead, tin bismuth, or tin silver copper. The packaging structure according to claim 1, wherein the packaging glue covers the peripheral surface of the chip, and the packaging glue has a top surface and a bottom surface opposite to each other, and the top surface of the packaging glue is aligned with the top surface of the chip. The back surface, and the bottom surface of the encapsulating glue is in line with the bottom surface of each of the conductors. The packaging structure described in claim 5 further includes: An additional packaging glue covering the back surface of the chip and the packaging glue, wherein an additional bottom surface of the additional packaging glue is cut flush with the bottom surface of the packaging glue; and An additional reconfiguration circuit layer is disposed on the bottom surface of the packaging compound and the additional bottom surface of the additional packaging compound, and is located between the solder balls and the conductors, wherein the additional reconfiguration wiring layer is electrically connected The conductors and the solder balls. The packaging structure as described in claim 1, further including: An additional packaging compound has an additional top surface and an additional bottom surface opposite to each other, and covers the peripheral surface of the chip, wherein part of the reconfiguration circuit layer extends out of the active surface of the chip and is disposed on the additional packaging plastic body The attached bottom surface. The packaging structure according to claim 7, wherein the packaging glue covers the additional top surface of the additional packaging glue and the back surface of the chip. The package structure according to claim 1, wherein the chip includes a dynamic random access memory. The packaging structure according to claim 1, wherein the packaging compound has a plurality of side surfaces, and a horizontal distance between the peripheral surface of the chip and each of the side surfaces of the packaging compound is the same. A manufacturing method of an encapsulation structure, including: A wafer is provided, the wafer includes a plurality of chips, each of the chips has an opposite active surface and a back surface and a peripheral surface connecting the active surface and the back surface, and includes a plurality of pads, and the active surface is divided into A central area and two peripheral areas located on both sides of the central area, and the pads are located in the central area; A reconfiguration circuit layer is formed on the wafer, the reconfiguration circuit layer is located on the active surface of each chip, and includes a plurality of circuits and a plurality of connection pads, and the connection pads are located on the peripheral area of each chip , And the lines are connected to the pads and part of the connection pads; Forming a plurality of electrical conductors respectively on the connection pads; Perform a first singulation process on the wafer to form a plurality of chip units, wherein each of the chip units includes each of the chips, the reconfiguration circuit layer on the active surface of each of the chips, and the conductive body; Performing an encapsulation process on the chip units, so that an encapsulating glue covers the peripheral surface of each chip and the reconfiguration circuit layer, and at least exposes the lower surface of each conductor; Forming a plurality of solder balls outside the packaging body, wherein the solder balls are electrically connected to the conductors; and A second singulation process is performed on the packaging glue to form a plurality of packaging structures with the solder balls. The manufacturing method of the package structure according to claim 11, wherein the method of forming the conductive bodies on the connecting pads includes an electroplating method, an electroless plating deposition method, a metal bonding etching method, or a reflow soldering ball method. The manufacturing method of the package structure according to claim 11, wherein each of the conductors includes a metal pillar or a metal ball. The manufacturing method of the package structure according to claim 13, wherein the material of the metal pillar includes copper, silver or tin. The manufacturing method of the package structure according to claim 13, wherein the material of the metal ball includes tin, lead-free solder, tin indium, tin lead, tin bismuth, or tin silver copper. The manufacturing method of the packaging structure according to claim 11, wherein the step of performing the packaging procedure on the chip units includes: Provide a carrier board with an adhesive layer; Positioning the chip units on the carrier board through the adhesive layer, wherein the adhesive layer is located between the back surface of each chip and the carrier board; Forming a packaging material layer on the carrier, the packaging material layer covering the chip units and the adhesive layer; and A grinding process is performed on the packaging material layer to expose the lower surface of each of the conductors to form the packaging gel. The manufacturing method of the package structure according to claim 16, wherein after the solder balls are formed outside the package body and before the second singulation process, the adhesive layer and the carrier are removed, The backside of each chip is exposed. The manufacturing method of the package structure according to claim 11, wherein the package glue is filled between the conductors, and the package glue has a top surface and a bottom surface opposite to each other, and the top surface of the package glue is aligned with The back surface of the chip, and the bottom surface of the encapsulating glue is in line with the lower surface of each of the conductors. The manufacturing method of the package structure according to claim 11, wherein the chip includes a dynamic random access memory. The manufacturing method of the package structure according to claim 11, wherein the package compound has a plurality of side surfaces, and a horizontal distance between the peripheral surface of the chip and each side surface of the package compound is the same.

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