CN109585312B - Alignment bumps in fan-out packaging process - Google Patents

Alignment bumps in fan-out packaging process Download PDF

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Publication number
CN109585312B
CN109585312B CN201811122570.2A CN201811122570A CN109585312B CN 109585312 B CN109585312 B CN 109585312B CN 201811122570 A CN201811122570 A CN 201811122570A CN 109585312 B CN109585312 B CN 109585312B
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package
carrier
underfill
conductive pillars
metal
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CN201811122570.2A
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CN109585312A (en
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黄英叡
黄见翎
林志伟
谢静华
刘重希
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US15/966,468 external-priority patent/US11217555B2/en
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Abstract

A method includes placing a first package assembly and a second package assembly over a carrier. The first conductive pillar of the first packaging assembly and the second conductive pillar of the second packaging assembly face the carrier. The method further includes encapsulating the first package component and the second package component in an encapsulation material; debonding the first and second package components from the carrier; planarizing the first conductive pillars, the second conductive pillars, and the sealing material, and forming redistribution lines to electrically connect to the first conductive pillars and the second conductive pillars. Embodiments of the present invention relate to a package and a method of forming the same, and more particularly, to an alignment bump in a fan-out packaging process.

Description

Alignment bumps in fan-out packaging process
Technical Field
Embodiments of the invention relate to alignment bumps in a fan-out packaging process.
Background
As semiconductor technology advances, semiconductor chips/dies become smaller and smaller. At the same time, more functionality needs to be integrated into the semiconductor die. Therefore, semiconductor dies need to pack more and more I/O pads into smaller areas, and thus the density of I/O pads is rapidly increasing over time. As a result, packaging of the semiconductor die becomes more difficult, which can adversely affect package yield.
Conventional packaging techniques can be divided into two categories. In the first category, the dies on the wafer are packaged before they are diced. This packaging technique has some advantageous features such as greater throughput and lower cost. In addition, less underfill or molding compound is required. However, this packaging technique also has drawbacks. As the size of the die is getting smaller and smaller, and the corresponding packages can only be fan-in packages, where the I/O pads of each die are limited to the area directly above the surface of the corresponding die. Due to the limited area of the die, the number of I/O pads is limited due to the spacing limitations of the I/O pads. Solder bridging may occur if the pitch of the pads is reduced. Furthermore, with fixed solder ball size requirements, the solder balls must be of a particular size, which in turn limits the number of solder balls that can be packaged on the die surface.
In another type of package, the die are cut from the wafer prior to packaging the die. An advantageous feature of this packaging technique is the possibility of forming a fan-out package, which means that the I/O pads on the die can be distributed to a larger area than the die and thus the number of I/O pads on the surface of the die can be increased by the package. Another advantageous feature of this packaging technique is that the "known good die" is packaged, and the defective die is discarded, and therefore cost and effort is not wasted on the defective die.
Disclosure of Invention
According to some embodiments of the invention, there is provided a method of forming a package, comprising: placing a first package component and a second package component over a carrier, wherein a first conductive pillar of the first package component and a second conductive pillar of the second package component face the carrier; sealing the first and second package components in an encapsulant material; debonding the first and second packaging components from the carrier; planarizing the first conductive pillars, the second conductive pillars, and the sealing material, and forming a redistribution line to be electrically connected to the first conductive pillars and the second conductive pillars.
In the above method, when the sealing is performed, the surfaces of the first conductive pillar and the second conductive pillar are aligned to the same plane.
In the above method, further comprising: an underfill is dispensed between the carrier and the first package component and between the carrier and the second package component, wherein in the planarizing, the underfill is also planarized.
In the above method, further comprising: forming a plurality of metal pads over the carrier; bonding the first and second conductive pillars to the plurality of metal pads; and removing the plurality of metal pads from the first and second conductive pillars.
In the above method, the removing includes performing chemical mechanical polishing or mechanical grinding on the plurality of metal pads.
In the above method, further comprising: forming a template film over the carrier, wherein the first and second conductive pillars are inserted into the template film; and removing the template film.
In the above method, removing the template film comprises subjecting the template film to chemical mechanical polishing or mechanical grinding.
There is also provided, in accordance with yet other embodiments of the present invention, a method of forming a package, including: forming a plurality of metal pads over a carrier; bonding the first conductive pillars of the first package assembly and the second conductive pillars of the second package assembly to the plurality of metal pads; dispensing an underfill under the first and second package components; encapsulating the first and second package components in an encapsulant material to form a composite wafer; debonding the composite wafer from the carrier; and performing first planarization on the first and second package components, the underfill, and the sealing material to remove the plurality of metal pads.
In the above method, the first conductive pillar and the second conductive pillar are bonded to the plurality of metal pads by solder regions.
In the above method, after the first planarization, the solder region is removed to expose the surfaces of the first and second conductive pillars.
In the above method, a residual portion of the solder region remains on a sidewall of one of the first conductive pillar and the second conductive pillar after the first planarization.
In the above method, further comprising performing a second planarization on the sealing material to expose at least one of the first package member and the second package member before the debonding.
In the above method, further comprising: when the plurality of metal pads are formed, a plurality of guide belts are formed, wherein the plurality of guide belts guide the underfill to flow from the first package assembly to the second package assembly.
In the above method, further comprising: removing the plurality of guide strips in the first planarization.
There is also provided, in accordance with yet other embodiments of the present invention, a package, including: a first package assembly and a second package assembly; a sealing material in which the first package member and the second package member are sealed; a dielectric layer over and contacting the encapsulation material; an underfill comprising: a first portion between the first package component and the dielectric layer, wherein the first conductive pillars of the first package component are located in the underfill, and an upper portion of the underfill is wider than a lower portion of the underfill; and a second portion between the second package component and the dielectric layer, wherein the second conductive pillars of the second package component are located in the underfill; and a redistribution line extending into the dielectric layer to contact the first and second conductive pillars.
In the above package, the first conductive pillar and the second conductive pillar have different lengths.
In the above package, the underfill comprises: a first spherical particle; and a first portion of particles contacting the dielectric layer.
In the above package, the sealing material includes: a second spherical particle; and a second portion of particles contacting the dielectric layer.
In the above package, the first package assembly includes a device die.
In the above package, the underfill extends laterally beyond an edge of the first package component.
Drawings
The various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1-14 illustrate cross-sectional views of intermediate stages in forming a package, according to some embodiments.
Fig. 15-22 illustrate cross-sectional views of intermediate stages in forming a package, according to some embodiments.
Fig. 23 illustrates a top view of a metal pad and a bootstrap band in accordance with some embodiments.
Fig. 24A and 24B illustrate cross-sectional and top views, respectively, of package assemblies and conductive pillars in residual solder regions, according to some embodiments.
Fig. 25 illustrates an enlarged view of a portion of a package including a planarized underfill and encapsulant material according to some embodiments.
Fig. 26 and 27 illustrate a process flow for forming a package according to some embodiments.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Also, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another (or other) element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
An integrated fan out (InFO) package and method of forming the same are provided according to various exemplary embodiments. An intermediate stage of forming an InFO package is shown according to some embodiments. Some variations of some embodiments are discussed. Like reference numerals are used to designate like elements throughout the various figures and exemplary embodiments.
Fig. 1-14 illustrate cross-sectional views of intermediate stages in forming a package, according to some embodiments; the steps illustrated in fig. 1-14 are also schematically illustrated in the process flow 200 illustrated in fig. 26.
Referring to fig. 1, a carrier 20 is provided, and a release film 22 is coated on the carrier 20. The support 20 is formed of a transparent material, and may be a glass support, a ceramic support, an organic support, or the like. The carrier 20 may have a circular plan view shape and may have the size of a silicon wafer. For example, the carrier 20 may have a diameter of 8 inches, a diameter of 12 inches, or the like. The release film 22 is in physical contact with the top surface of the carrier 20. The release film 22 may be formed of a light-to-heat conversion (LTHC) coating material. The release film 22 may be applied to the carrier 20 by coating. According to some embodiments of the present invention, the LTHC coating material is capable of decomposing under the heat of light/radiation (such as a laser) and thus may release the carrier 20 from the structure formed thereon. According to some embodiments of the invention, the LTHC layer 22 includes carbon black (carbon particles), a solvent, a filler, and/or an epoxy resin. The LTHC layer 22 may be applied in a flowable form and then cured, for example, under Ultraviolet (UV) light.
According to some embodiments, as also shown in FIG. 1, a polymeric buffer layer 24 is formed on the release film 22. According to some embodiments, the polymer buffer layer 24 is formed of Polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or another applicable polymer. According to an alternative embodiment of the present invention, the polymer buffer layer 24 is not formed. Thus, the polymer buffer layer 24 is shown in dashed lines to indicate that it may or may not be formed.
Fig. 1 further illustrates the formation of a metal layer 26 that may be implemented by deposition. The corresponding step is shown in the process flow shown in fig. 26 as step 202. The metal layer 26 may be formed, for example, by Physical Vapor Deposition (PVD). According to some embodiments of the invention, no dielectric layer is formed between the LTHC coating 22 and the metal layer 26, and thus the metal layer 26 is in physical contact with the LTHC layer 22. For example, there is no polymer layer such as a polyimide layer, a Polybenzoxazole (PBO) layer, or a benzocyclobutene (BCB) layer between the metal layer 26 and the LTHC layer 22. According to some embodiments of the present invention, metal layer 26 comprises titanium layer 26A and copper layer 26B over titanium layer 26A. According to an alternative embodiment of the invention, the metal layer 26 is a homogenous layer, which may be a copper layer.
Reference is now made to fig. 2. Next, the metal layer 26 is patterned by etching, and the metal pad 28 is formed. The corresponding step is shown in the process flow shown in fig. 26 as step 204. The metal pads 28 are positioned and sized to match the position and size of subsequently placed package components 32A and 32B (shown in fig. 3) so that the package components 32A and 32B may be bonded to the metal pads 28. The remainder of the metal layer 26, in addition to the metal pad 28, may (or may not) include an elongated strip of guide tape 30. Fig. 23 illustrates a top view of some exemplary metal pads 28 and bootstrap bands 30, in accordance with some embodiments of the present invention. As shown in fig. 23, at least some of the guide strips 30 are located between two sets of metal pads 28, and the guide strips 30 are guided from one set to the other. Fig. 23 also schematically shows package assemblies 32A and 32B, which are subsequently bonded to metal pads 28 in the step shown in fig. 3.
In accordance with an alternative embodiment of the present invention, forming the metal pad 28 and the guide strip 30 includes depositing a blanket metal seed layer, forming and patterning a photoresist to expose portions of the blanket metal seed layer, plating a metal material in openings located in the photoresist, removing the photoresist, and etching portions of the metal seed layer not covered by the photoresist. The plated metallic material and the remaining portion of the metal seed layer form the metal pad 28 and the lead strip 30.
Fig. 3 shows placement/ attachment package assemblies 32A and 32B, package assemblies 32A and 32B also collectively and individually referred to as package assemblies 32 or devices 32. The package assemblies 32A and 32B may include device dies that include integrated circuit devices (e.g., such as active devices including transistors) located at the front surfaces (face-down surfaces) of the respective semiconductor substrates 34A and 34B. According to some embodiments of the invention, each of the package components 32A and 32B may be a logic die, wherein the logic die may be a Central Processing Unit (CPU) die, a Graphics Processing Unit (GPU) die, a mobile application die, a Micro Control Unit (MCU) die, an input-output (IO) die, a baseband (BB) die, or an Application Processor (AP) die. Each of the package assemblies 32A and 32B may also be a system-on-chip die, a memory die (such as a Static Random Access Memory (SRAM) die or a Dynamic Random Access Memory (DRAM) die), a High Bandwidth Memory (HBM) cube, or the like.
According to some example embodiments, the package assemblies 32A and 32B may include semiconductor substrates 34A and 34B, wherein the semiconductor substrates 34A and 34B may also be silicon substrates. The package assemblies 32A and 32B may also include interconnect structures 36A and 36B and conductive pillars 38A and 38B, respectively. Interconnect structures 36A and 36B may include dielectric layers, as well as metal lines and vias in the dielectric layers. The conductive posts 38A and 38B may be metal posts, and may include copper posts, which may or may not include additional layers such as a nickel layer, a gold layer, a palladium layer, and the like. The conductive posts 38A and 38B may have vertical and straight edges and may protrude below the respective surface dielectric layers in the package assemblies 32A and 32B, respectively. The conductive pillars 38A and 38B are formed in advance as part of the package assemblies 32A and 32B, and are electrically connected to integrated circuit devices such as transistors in the package assemblies 32A and 32B, respectively.
The package assembly (device) 32 is bonded to the metal pads 28 by solder regions 40, wherein the solder regions 40 may be part of a pre-formed package assembly 32. The corresponding step is shown in the process flow shown in fig. 26 as step 206. Bonding includes alignment steps, light pressure on each package assembly 32, and a reflow process. The reflow may be performed after placing all the package assemblies 32, or the reflow may be performed for each package assembly 32. The locations of the conductive posts 38A and 38B are aligned with the corresponding metal pads 28. The horizontal dimension of the metal pad 28 may be greater than, equal to, or less than the horizontal dimension of the corresponding overlying conductive pillars 38A and 38B. The reflow process is also a self-aligned process because the locations of the package components 32A and 32B will be aligned by the molten solder areas 40. Thus, as long as the metal pads 28 are precisely formed to the desired locations, the package assemblies 32A and 32B will be aligned with the desired locations on the carrier 20. Also, by placing the package assemblies 32A and 32B face down to allow the conductive posts 38A and 38B to bond to the metal pads 28 on the same plane, the bottom surfaces of the conductive posts 38A and 38B are approximately aligned with the same horizontal plane.
Since the carrier 20 is at the wafer level, although one package assembly 32A and one package assembly 32B are shown, multiple identical device dies 32A and multiple identical device dies 32B may be bonded to respective metal pads 28. The package assemblies 32A and 32B may be arranged as groups of devices, each group of devices including one package assembly 32A and one package assembly 32B. The device groups may be arranged as an array comprising a plurality of rows and a plurality of columns.
Fig. 4 illustrates dispensing and curing the underfill 42. The corresponding step is shown in the process flow shown in fig. 26 as step 208. According to some embodiments of the invention, the underfill 42 is dispensed by a dispenser 44 located on one side of the device group including the package assemblies 32A and 32B. The underfill 42 then flows into the gap between the buffer layer 24 and the package assembly 32A, the gap between the package assemblies 32A and 32B, and the gap between the buffer layer 24 and the package assembly 32B. The guide tape 30 has a function of guiding the flow of the underfill 42, thereby making it easier for the underfill 42 to flow through the gap between the package members 32A and 32B and into the gap between the buffer layer 24 and the package member 32B. Without the leader tape 30, the underfill 42 is more likely to accumulate in the gap between the encapsulation components 32A and 32B, and less underfill 42 will flow into the gap between the buffer layer 24 and the encapsulation component 32B.
The underfill 42 may include a base material 42A (refer to fig. 25) and filler particles 42B in the base material 42A, wherein the base material may be a polymer, a resin, an epoxy resin, or the like. The filler particles 42B may be SiO 2、Al2O3Dielectric particles of white carbon, and the like, and may have a spherical shape. Moreover, the spherical filler particles can have a variety of different diameters. The filler particles 42B and the substrate 42A in the underfill 42 may be in physical contact with the polymer buffer layer 24 (fig. 4) or the LTHC layer 22 (if the polymer layer 24 is not formed).
Next, as shown in fig. 5, the package assemblies 32A and 32B are sealed in the sealing material 46. The corresponding step is shown in the process flow shown in fig. 26 as step 210. The sealing material 46 fills the gap between the adjacent package assemblies 32A and 32B. The encapsulant 46 may include a molding compound, a molded underfill, an epoxy, and/or a resin. The top surface of the encapsulation material 46 is higher than the top surfaces of both the package assemblies 32A and 32B. The encapsulant 46 may also include a substrate 46A (fig. 25) and filler particles 46B in the substrate 46A, wherein the substrate may be a polymer, a resin, an epoxy, or the like. The filler particles 46B may be SiO2、Al2O3Dielectric particles of white carbon, and the like, and may have a spherical shape. Moreover, the spherical filler particles 46B can have a variety of different diameters. As shown in fig. 25 in conjunction with fig. 5, both the filler particles 46B and the substrate 46A may be in physical contact with the polymer buffer layer 24 or the LTHC layer 22 (if the polymer layer 24 is not formed).
In subsequent steps, as shown in fig. 6, a planarization step, such as a Chemical Mechanical Polishing (CMP) step or a mechanical grinding step, is performed to thin the encapsulation material 46 until one or both of the package components 32A and 32B are exposed. The corresponding step is shown in the process flow shown in fig. 26 as step 212. According to some embodiments of the invention, substrates 34A and 34B, which may be silicon substrates, are exposed. Due to the planarization process, the top surfaces of the package assemblies 32A and 32B are substantially flush (coplanar) with the top surface of the encapsulation material 46. According to an alternative embodiment, after planarization is completed, one of the package assemblies 32A and 32B is not exposed and is covered by the remaining layer of the sealing material 46 directly above it. Throughout the description, the structure above the LTHC layer 22 is referred to as a composite wafer 54.
Figure 7 shows the exchange of vectors. The corresponding step is shown in the process flow shown in fig. 26 as step 214. During carrier exchange, the carrier 50 is attached to the illustrated surfaces of the package assemblies 32A and 32B and the sealing material 46, for example, by a release film 52. The carrier 50 is attached to the opposite side of the composite wafer 54 from the carrier 20 (fig. 6). Next, the package assemblies 32A and 32B and the sealing material 46 are removed from the carrier 20 (fig. 6). According to some embodiments of the invention, removing includes decomposing the LTHC layer 22, which includes projecting heat carrying radiation, such as a laser beam, onto the LTHC layer 22. As a result, the LTHC layer 22 is decomposed, and the carrier 20 may be detached from the LTHC layer 22. Thus, the composite wafer 54 is debonded (debonded) from the carrier 20. The resulting structure is shown in fig. 7. As also shown in fig. 7, if the composite wafer 54 includes the polymer buffer layer 24 (fig. 6), the polymer buffer layer 24 is also removed, exposing the underfill 42 and the encapsulation material 46. Thereby exposing the metal pad 28 and the bootstrap band 30.
Next, a planarization step, such as CMP or mechanical grinding, is performed to remove the metal pads 28, the lead strips 30, and the solder regions 40 so that the top surfaces of the conductive posts 38 are exposed. The corresponding step is shown in the process flow shown in fig. 26 as step 216. The resulting structure is shown in fig. 8. According to some embodiments of the present invention, all of the solder regions 40 are removed, and thus no residual solder regions 40 remain in the composite wafer 54. In bonding of the package components 32A and 32B to the metal pads 28, portions of the solder regions 40 flow to the sidewalls of the conductive posts 38A and 38B, according to some embodiments of the present invention. As shown in fig. 8, these portions of the solder regions 40 may or may not remain in the composite wafer 54. Fig. 24A shows an enlarged view of the area 56 in fig. 8. As shown in fig. 24A, the remaining portions of the solder regions 40 contact the sidewalls of the tops of the conductive posts 38A (or 38B) and do not contact the sidewalls of the bottoms of the respective conductive posts 38A (or 38B). Fig. 24B shows a top view of region 56. As shown in fig. 24B, in a top view, the remaining portions of the solder regions 40 may contact portions of the sidewalls and not other portions. As shown by the dashed lines, the remaining portions of the solder regions 40 may also form a ring around the conductive post 38A (or 38B). The pattern of solder areas 40 is random. For example, the remaining portions of the solder regions 40 may remain on some of the conductive pillars 38A and 38B, but not on other conductive pillars 38A and 38B.
Fig. 9 to 12 illustrate forming a front-side interconnect structure. The corresponding step is shown in the process flow shown in fig. 26 as step 218. Fig. 9 illustrates a first layer and a corresponding dielectric layer forming a redistribution line (RDL). A dielectric layer 60 is formed on top of the package assemblies 32A and 32B and the encapsulation material 46. According to some embodiments of the present invention, the dielectric layer 60 is formed of a polymer such as PBO, polyimide, or the like. The method of forming includes applying dielectric layer 60 in a flowable form and then curing dielectric layer 60. According to an alternative embodiment of the present invention, dielectric layer 60 is formed of an inorganic dielectric material such as silicon nitride, silicon oxide, or the like. The formation method may include Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Plasma Enhanced Chemical Vapor Deposition (PECVD), or other applicable deposition methods. Openings (occupied by features 62) are then formed in dielectric layer 60, for example by a photolithographic process, to expose underlying conductive pillars 38A and 38B. According to some embodiments, in which the dielectric layer 60 is formed of a photosensitive material such as PBO or polyimide, forming the opening involves a light exposure and development step using a photolithographic mask.
Next, as also shown in fig. 9, a redistribution line (RDL)62 is formed. RDL62 includes vias extending into dielectric layer 60 to connect to conductive pillars 38A and 38B and metal traces (metal lines) located over dielectric layer 60. According to some embodiments of the invention, RDL62 is formed in a plating process, where the plating process includes depositing a metal seed layer, forming and patterning a photoresist over the metal seed layer, and plating a metallic material, such as copper and/or aluminum, over the metal seed layer. The metal seed layer and the plated metal material may be formed of the same metal or different metals. The patterned photoresist is then removed, followed by etching the portion of the metal seed layer previously covered by the patterned photoresist.
Due to the plating process, the metal line portion of RDL 62 may not be flat, and the metal line portion of RDL 62 directly above the via portion may have a groove (recess), as schematically illustrated by dashed line 62A. Furthermore, there is no distinguishable interface between the via portion and the metal line portion of RDL 62. Although not shown, the subsequently formed RDLs 62, 66, and 70 shown in fig. 14 and 22 may have similar recesses, which indicate that the RDLs 62, 66, and 70 are formed after the sealant material 46 and underfill 42 are dispensed.
A dielectric layer 64 is formed over dielectric layer 60 and RDL 62. Dielectric layer 64 may be formed from a material selected from the same candidate materials used to form dielectric layer 60 and may include PBO, polyimide, BCB, or other organic or inorganic materials.
Openings may then be formed in dielectric layer 64 to expose portions of RDL 62. Referring to fig. 10, an RDL 66 is formed. RDL 66 also includes a via portion that extends into an opening located in dielectric layer 64 to contact RDL 62 and a metal line portion located over dielectric layer 64. Forming RDL 66 may be the same as forming RDL 62, including forming a seed layer, forming a patterned mask, plating RDL 66, and then removing the patterned mask and undesired portions of the seed layer. A dielectric layer 68 is then formed. Dielectric layer 68 may be formed from a material selected from the same group of candidate materials used to form dielectric layers 60 and 64.
Fig. 11 illustrates forming the RDL 70. The RDL 70 may also be formed from a metal or metal alloy including aluminum, copper, tungsten, or alloys thereof. It should be understood that although in the exemplary embodiment shown, three layers of RDLs (62, 66, and 70) are formed, the package may have any number of RDL layers such as one, two, or more than three layers.
Fig. 12 illustrates forming a dielectric layer 72, an Under Bump Metal (UBM)74, and an electrical connection 76, according to some example embodiments. Dielectric layer 72 may be formed from a material selected from the same group of candidate materials used to form dielectric layers 60, 64, 68. For example, the dielectric layer 72 may be formed using PBO, polyimide, or BCB. Openings are formed in the dielectric layer 72 to expose underlying metal pads that are part of the RDL 70 in the illustrative exemplary embodiment. According to some embodiments of the present invention, UBM74 is formed to extend into an opening located in dielectric layer 72. UBM74 may be formed of nickel, copper, titanium, or multilayers thereof. According to some exemplary embodiments, UBM74 includes a layer of titanium and a layer of copper over the layer of titanium.
Electrical connections 76 are then formed. Forming electrical connections 76 may include plating non-solder (such as copper) metal posts on exposed portions of UBM74, plating a solder layer, and then reflowing solder layer 76. In accordance with an alternative embodiment of the present invention, forming electrical connection 76 includes performing a plating step to form a solder region directly over UBM74, and then reflowing the solder region.
According to some embodiments of the present invention, the composite wafer 54 is debonded from the carrier 50 (fig. 12), wherein the resulting wafer 54 is shown in fig. 13. The composite wafer 54 may be attached to dicing tape. The composite wafer 54 includes a plurality of packages 54 'identical to one another, wherein each package 54' includes package components 32A and 32B. The composite wafer 54 is then diced by a die saw into a plurality of discrete packages 54'. The corresponding step is shown in the process flow shown in fig. 26 as step 220.
Fig. 14 shows the bonding of package 54' to package assembly 80, thus forming package 84. The corresponding step is shown in the process flow shown in fig. 26 as step 222. The bonding is effected by electrical connection 76 and bond pad 78. According to some embodiments of the invention, the package assembly 80 is a package substrate, which may be a coreless substrate or a substrate with a core. According to other embodiments of the present invention, the package assembly 80 includes a printed circuit board or package.
Fig. 25 shows an enlarged view of the region 86 in the package 84 as shown in fig. 14. According to some embodiments of the present invention, the sealing material 46 includes a substrate 46A and filler particles 46B disposed in the substrate 46A. Also, the underfill 42 may include a base material 42A and filler particles 42B located in the base material 42A. The filler particles 42B and 46B may have a spherical shape and may be formed of a dielectric material such as silicon dioxide. Since the portion of the underfill 42 facing the package assemblies 32A and 32B (including the conductive pillars 38A and 38B) is not planarized by CMP or mechanical grinding, the spherical particles 42B in contact with the illustrated top and vertical edges of the package assemblies 32A and 32B have spherical surfaces. In comparison, the portions of the sealing material 46 and the underfill 42 that are in contact with the dielectric layer 60 have been planarized in the step shown in fig. 8. Thus, the spherical particles 42B and 46B in contact with the dielectric layer 60 are partially cut during planarization, and thus will have a substantially flat top surface (rather than a rounded top surface) in contact with the dielectric layer 60. On the other hand, the inner spherical particles 42B and 46B that are not planarized retain the original shape having a non-flat (such as spherical) surface. Throughout the description, the particles 42B and 46B that have been polished in the planarization are referred to as partial particles. Further, the portion of the sealing material 46 at the bottom of the package 84 has been planarized in the step shown in fig. 6. Thus, the spherical particles 46B at the bottom surface of the package 84 are partially cut during the planarization process, and thus will have a substantially flat bottom surface (rather than a rounded bottom surface).
As also shown in fig. 14, the upper portion of the underfill 42 is wider than the corresponding lower portion of the underfill 42. According to some embodiments, the planarization may cause the portion of the underfill 42 adjacent to the package assembly 32A to be disconnected from the portion of the underfill 42 adjacent to the package assembly 32B, as indicated by the dashed line 42'. Also, if a sectional view of the underfill 42 is taken from a plane including the line B-B in fig. 14, the broken line 42' also shows what the underfill 42 looks like.
Fig. 15-22 illustrate cross-sectional views at intermediate stages in forming an InFO package according to some embodiments of the invention. The steps shown in fig. 15-22 are also schematically illustrated in the process flow 300 shown in fig. 27. These embodiments are similar to the embodiments shown in fig. 1-14, except that the conductive pillars of the package assembly are inserted into the film instead of being bonded on the metal pads. Unless otherwise stated, the materials and methods of formation of the components in these embodiments are substantially the same as the same components, which are identified by the same reference numerals in the embodiments shown in fig. 1-14. Accordingly, details regarding the formation processes and materials of the components shown in fig. 15-22 may be found in the discussion of the embodiments shown in fig. 1-14.
Referring to fig. 15, a template film 23 is formed or adhered over the support 20. The corresponding step is shown in the process flow shown in fig. 27 as step 302. The template film 23 may be a preformed film adhered over the carrier 20 or coated over the carrier 20. The template film 23 may be formed of a homogeneous material in which no conductive member, metal member, or the like is present. The template film 23 may be formed of an adhesive film, which may be a die attach film for attaching the device die to other surfaces. According to some embodiments of the invention, a LTHC layer 22 is coated on the carrier 20, and a template film 23 is formed over the LTHC layer 22 and may be in contact with the LTHC layer 22. According to an alternative embodiment of the present invention, the LTHC layer 22 is not formed, and the template film 23 is in contact with the support 20.
Referring to fig. 16, package assemblies 32A and 32B are picked up and placed on the template film 23. The corresponding step is shown in the process flow shown in fig. 27 as step 304. The conductive posts 38A and 38B are in contact with at least the template film 23. A light force may be applied to the encapsulation members 32A and 32B so that the conductive posts 38A and 38B extend into the template film 23, so that the positions of the encapsulation members 32A and 32B are fixed on the template film 23. For example, the conductive posts 38A and 38B may extend to about 20% to about 80% of the thickness of the stencil film 23. As shown in fig. 16, the length of conductive post 38A may be different than the length of conductive post 38B. By placing the package assemblies 32A and 32B face down, the bottom surfaces of the conductive posts 38A and 38B are aligned with substantially the same plane. The process step shown in fig. 16 is at the wafer level, according to some embodiments of the present invention. Therefore, there are a plurality of device groups identical to the device group including the package assemblies 32A and 32B placed on the template film 23. As shown in fig. 16, the top surfaces of the package assemblies 32A and 32B may or may not be in the same plane.
Referring to fig. 17, an underfill 42 is dispensed, for example, from one side of the device group. The corresponding step is shown in the process flow shown in fig. 27 as step 306. The underfill 42 flows into the gap between the template film 23, the package assembly 32A, and the package assembly 32B. As shown in fig. 25, the material and composition of the underfill 42 may be the same as discussed with respect to the illustrated embodiment of fig. 1-14, and may include a matrix 42A and filler particles 42B.
Next, as shown in fig. 18, the package assemblies 32A and 32B are sealed in the sealing material 46. The corresponding step is shown in the process flow shown in fig. 27 as step 308. In fig. 25, the sealing material 46 may also include a base material, which may be a polymer, resin, epoxy, or the like, and filler particles disposed in the base material, as shown at 46A and 46B, respectively.
In subsequent steps, as shown in fig. 19, a planarization step, such as a CMP step or a mechanical grinding step, is performed to thin the encapsulation material until one or both of the package assemblies 32A and 32B are exposed. The corresponding step is shown in the process flow shown in fig. 27 as step 310. According to an alternative embodiment, after planarization is completed, one of the package assemblies 32A and 32B is not exposed and is covered by the remaining layer of sealing material directly above it. According to some embodiments of the present invention, the substrates 34A and 34B, which are silicon substrates, may be exposed. Due to the planarization process, the top surfaces of the package assemblies 32A and 32B are substantially flush (coplanar) with the top surface of the encapsulation material 46. Thereby forming a composite wafer 54.
Figure 20 shows the exchange of vectors. The corresponding step is shown in the process flow shown in fig. 27 as step 312. During carrier exchange, a carrier 50 is attached to the illustrated surface of the composite wafer 54, for example by a release film 52. The carrier 50 is attached to the side of the composite wafer 54 opposite the carrier 20 (fig. 19). Next, the package members 32A and 32B and the sealing material 46 are detached from the carrier 20 (fig. 19). According to some embodiments of the invention, debonding includes decomposing the LTHC layer 22, which includes projecting heat carrying radiation, such as a laser beam, through the carrier 20 onto the LTHC layer 22. If the template film 23 is located directly on the carrier 50, the template film 23 may be formed of a heat release film that expands at an elevated temperature and is thus released from the carrier 20. As a result, the composite wafer 54 is debonded (detached) from the carrier 20. The resulting structure is shown in fig. 20.
The stencil film 23 may have some residual portions attached to the conductive posts 38A and 38B. Next, a planarization step such as CMP or mechanical polishing is performed to remove the remaining portion of the template film 23, and planarize the surfaces of the conductive pillars 38A and 38B. The corresponding step is shown in the process flow shown in fig. 27 as step 314. The top surfaces of the conductive posts 38A and 38B are thus coplanar with the top surfaces of the encapsulant 46 and the underfill 42.
Subsequent steps are substantially the same as those shown in fig. 9 to 13, in which a front-side interconnect structure is formed, and the resulting structure is shown in fig. 22. The corresponding step is shown in the process flow shown in fig. 27 as step 316. The composite wafer 54 shown in fig. 22 is similar to the composite wafer 54 shown in fig. 13, except that no solder residue is present on the sidewalls of the conductive pillars 38A and 38B, since no lands have been bonded to the conductive pillars 38A and 38B. In a subsequent step, the composite wafer 54 is singulated into a plurality of identical packages 54', one shown in fig. 14. The corresponding step is shown in the process flow shown in fig. 27 as step 318. Also, the package 54' may be bonded to the package assembly 80, and the resulting package 84 is also shown in fig. 14. The corresponding step is shown in the process flow shown in fig. 27 as step 320.
In the above exemplary embodiments, some exemplary processes and components are discussed in accordance with some embodiments of the present invention. Other components and processes may also be included. For example, test structures may be included to facilitate verification testing of three-dimensional (3D) packages or 3DIC devices. The test structure may include test pads formed in the redistribution layer or on the substrate to allow testing of the 3D package or the 3DIC device using a probe and/or a probe card, or the like. Verification tests may be performed on the intermediate structure and the final structure. Further, the structures and methods disclosed herein may be used in conjunction with testing methods that incorporate intermediate verification of known good dies to improve yield and reduce cost.
Embodiments of the present invention have some advantageous features. In conventional InFO package formation, the backside of the package assembly (such as a device die) is attached to the release film through a die attach film, and the conductive pillars in the device die face up. The package assembly is then encapsulated and the RDL is formed to connect to the conductive pillars. It should be appreciated that although the package components are intentionally manufactured to have the same thickness, there are process variations that result in variations in the thickness of the package components. For example, the thickness of the HBM cube may vary by + -25 μm. This variation leads to difficulties in forming RDLs. According to some embodiments of the invention, the conductive pillars of the package assembly are aligned with the same plane either by solder bonding to the metal pads or by attachment to the template film. Thereby compensating for differences in the length of the conductive pillars and differences in the thickness of the package assembly. Thus increasing the process window.
According to some embodiments of the invention, a method includes placing a first package component and a second package component over a carrier, wherein a first conductive pillar of the first package component and a second conductive pillar of the second package component face the carrier; sealing the first and second package components in a sealing material; the first and second package assemblies are debonded from the carrier; planarizing the first conductive pillars, the second conductive pillars, and the sealing material, and forming redistribution lines to electrically connect to the first conductive pillars and the second conductive pillars. In an embodiment, the surfaces of the first and second conductive posts are substantially aligned to the same plane when the sealing is performed. In an embodiment, the method further comprises dispensing an underfill between the carrier and the first package component and between the carrier and the second package component, wherein in the planarizing, the underfill is also planarized. In an embodiment, the method further comprises forming a plurality of metal pads over the carrier; bonding the first and second conductive pillars to a plurality of metal pads; and removing the plurality of metal pads from the first and second conductive pillars. In an embodiment, the removing comprises performing chemical mechanical polishing or mechanical grinding on the plurality of metal pads. In an embodiment, the method further comprises forming a template film over the carrier, wherein the first and second conductive pillars are inserted into the template film; and removing the template film. In an embodiment, removing the template film comprises subjecting the template film to chemical mechanical polishing or mechanical grinding.
According to some embodiments of the invention, a method comprises: forming a plurality of metal pads over a carrier; bonding the first conductive pillars of the first package assembly and the second conductive pillars of the second package assembly to the plurality of metal pads; dispensing an underfill under the first and second package components; encapsulating the first and second package components in an encapsulant material to form a composite wafer; debonding the composite wafer from the carrier; and performing first planarization on the first and second package assemblies, the underfill, and the sealing material to remove the plurality of metal pads. In an embodiment, the first and second conductive pillars are bonded to the plurality of metal pads by solder regions. In an embodiment, after the first planarization, the solder region is removed to expose surfaces of the first and second conductive pillars. In an embodiment, a residual portion of the solder region remains on a sidewall of one of the first and second conductive pillars after the first planarization. In an embodiment, the method further includes performing a second planarization on the encapsulation material to expose at least one of the first package component and the second package component prior to the debonding. In an embodiment, the method further comprises: when forming the plurality of metal pads, a plurality of guide belts are formed, wherein the plurality of guide belts guide the underfill to flow from the first package assembly to the second package assembly. In an embodiment, the method further comprises removing the plurality of bootstrap bands in a first planarization.
According to some embodiments of the present invention, a package includes a first package assembly and a second package assembly; a sealing material sealing the first and second package components therein; a dielectric layer over and contacting the sealing material; an underfill comprising: a first portion between the first package component and the dielectric layer, wherein the first conductive pillars of the first package component are located in the underfill, and an upper portion of the underfill is wider than a lower portion of the underfill; and a second portion between the second package component and the dielectric layer, wherein the second conductive pillars of the second package component are located in the underfill; and a redistribution line extending into the dielectric layer to contact the first and second conductive pillars. In an embodiment, the first conductive pillars and the second conductive pillars have different lengths. In an embodiment, the underfill comprises: a first spherical particle; and a first portion of particles contacting the dielectric layer. In an embodiment, the sealing material comprises: a second spherical particle; and a second portion of particles contacting the dielectric layer. In an embodiment, a first package assembly includes a device die. In an embodiment, the underfill extends laterally beyond an edge of the first package component.
The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (20)

1. A method of forming a package, comprising:
forming a first plurality of metal pads, a second plurality of metal pads, and a plurality of metal straps over a carrier, wherein the plurality of metal straps are located between the first and second plurality of metal pads;
placing a first package assembly and a second package assembly over the carrier, wherein first conductive pillars of the first package assembly and second conductive pillars of the second package assembly face the carrier and are respectively bonded to the plurality of metal pads;
Dispensing a sealing material from an outside of a package component group consisting of the first package component and the second package component, sealing the first package component and the second package component in the sealing material;
debonding the first and second encapsulation components from the carrier, wherein the debonding includes projecting light to break down a release film that bonds the first and second encapsulation components together with the carrier;
planarizing the first conductive pillar, the second conductive pillar, and the encapsulation material to remove the first plurality of metal pads and the second plurality of metal pads from the first conductive pillar and the second conductive pillar, and
a redistribution line is formed to be electrically connected to the first conductive pillars and the second conductive pillars.
2. The method of claim 1, wherein surfaces of the first and second conductive pillars are aligned to the same plane when the sealing is performed.
3. The method of claim 1, further comprising: an underfill is dispensed between the carrier and the first package component and between the carrier and the second package component, wherein in the planarizing, the underfill is also planarized.
4. The method of claim 1, further comprising:
forming a metal layer over the carrier;
patterning the metal layer to form the first plurality of metal pads, the second plurality of metal pads, and the plurality of metal bootstrap bands.
5. The method of claim 1, wherein the removing comprises performing chemical mechanical polishing or mechanical grinding on the plurality of metal pads.
6. The method of claim 4, wherein the plurality of metallic guide strips are discrete guide strips spaced from one another.
7. The method of claim 4, wherein the plurality of metal guide straps are located on three sides of the first package component, as viewed from top to bottom.
8. A method of forming a package, comprising:
forming a first plurality of metal pads, a second plurality of metal pads, and a plurality of metal straps over a carrier, wherein the plurality of metal straps are located between the first and second plurality of metal pads;
bonding first conductive pillars of a first package assembly and second conductive pillars of a second package assembly to the first and second pluralities of metal pads, respectively;
Dispensing underfill from outside and below a package component group consisting of the first package component and the second package component;
encapsulating the first and second package components in an encapsulant material to form a composite wafer;
debonding the composite wafer from the carrier, wherein the debonding includes projecting light to break down a release film attached to the carrier and lifting the carrier from the composite wafer; and
performing a first planarization of the first and second package components, the underfill, and the encapsulation material to remove the first and second plurality of metal pads,
wherein the plurality of guide tapes guide the underfill to flow from the first package assembly to the second package assembly.
9. The method of claim 8, wherein the first and second conductive pillars are bonded to the first and second pluralities of metal pads, respectively, by solder regions.
10. The method of claim 9, after the first planarization, removing the solder region to expose surfaces of the first and second conductive pillars.
11. The method of claim 9, wherein a residual portion of the solder region remains on a sidewall of one of the first and second conductive pillars after the first planarization.
12. The method of claim 9, further comprising performing a second planarization of the encapsulation material to expose at least one of the first package component and the second package component prior to the debonding.
13. The method of claim 8, further comprising: forming the plurality of bootstrap bands when forming the first plurality of metal pads and the second plurality of metal pads.
14. The method of claim 13, further comprising: removing the plurality of guide strips in the first planarization.
15. A package, comprising:
a first package assembly and a second package assembly;
a sealing material sealing the first package assembly and the second package assembly in the sealing material, wherein a bottom surface of the first package assembly, a bottom surface of the second package assembly, and a bottom surface of the sealing material are coplanar;
a dielectric layer over and contacting the encapsulation material;
An underfill comprising:
a first portion between the first package component and the dielectric layer and having a first thickness, wherein the first conductive pillar of the first package component is located in the underfill, and an upper portion of the underfill is wider than a lower portion of the underfill; and
a second portion between the second package component and the dielectric layer and having a second thickness, wherein the second conductive pillars of the second package component are in the underfill, wherein the first portion and the second portion are spaced apart from each other; and
a redistribution line extending into the dielectric layer to contact the first conductive pillars and the second conductive pillars,
wherein the first conductive post and the second conductive post are surrounded by a solder ring, the first thickness being greater than the second thickness.
16. The package of claim 15, wherein the first and second conductive pillars have different lengths.
17. The package of claim 15, wherein the underfill comprises:
a first spherical particle; and
a first portion of particles contacting the dielectric layer.
18. The package of claim 15, wherein the encapsulant material comprises:
a second spherical particle; and
a second portion of particles contacting the dielectric layer.
19. The package of claim 15, wherein the first package assembly comprises a device die.
20. The package of claim 15, wherein the underfill extends laterally beyond an edge of the first package component.
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