CN112420531B

CN112420531B - Semiconductor packaging method, semiconductor assembly and electronic equipment comprising semiconductor assembly

Info

Publication number: CN112420531B
Application number: CN202011353294.8A
Authority: CN
Inventors: 李维平
Original assignee: Shanghai Yibu Semiconductor Co ltd
Current assignee: Shanghai Yibu Semiconductor Co ltd
Priority date: 2020-11-27
Filing date: 2020-11-27
Publication date: 2021-11-30
Anticipated expiration: 2040-11-27
Also published as: KR20220074764A; TW202236444A; CN112420531A

Abstract

The application discloses a semiconductor packaging method, a semiconductor assembly and an electronic device comprising the semiconductor assembly, wherein the semiconductor packaging method comprises the following steps: providing at least one semiconductor device and a carrier plate, wherein a connecting terminal is formed on an active surface of the semiconductor device, a plurality of first alignment welding parts are formed on a passive surface of the semiconductor device, and a plurality of corresponding second alignment welding parts are formed on the carrier plate; placing the semiconductor device on the carrier plate such that the first alignment bond is substantially aligned with the second alignment bond; forming an alignment welding spot by welding the first alignment welding part and the second alignment welding part, so that the semiconductor device is accurately aligned and fixed to the carrier plate; forming a plastic package body for coating the semiconductor device by performing plastic package on the side of the carrier plate where the semiconductor device is located; exposing the connection terminal from the plastic package body; and sequentially forming an interconnection layer and an external terminal on a surface of the molding body where the connection terminal is exposed, such that the connection terminal is electrically connected to the external terminal through the interconnection layer.

Description

Semiconductor packaging method, semiconductor assembly and electronic equipment comprising semiconductor assembly

Technical Field

The embodiment of the application relates to the technical field of semiconductor manufacturing, in particular to a semiconductor packaging method, a semiconductor assembly and electronic equipment comprising the semiconductor assembly.

Background

Semiconductor packages and systems are constantly being sought for being compact, small, lightweight, and thin in design, while at the same time being sought for achieving high integration and versatility in function. Currently, various packaging technologies are proposed to meet the above-mentioned technical requirements, such as Fan-out (Fan-out) wafer level packaging, small chip packaging (chipset), heterogeneous integration (hetereogenous integration), and 2.5 dimensional/three dimensional (2.5D/3D) packaging. These packaging techniques have different advantages and characteristics, but all present some technical challenges. Taking the existing fan-out package as an example, it faces many technical problems, such as warpage (warp), chip shift (die shift), surface flatness (toporgraphy), non-coplanarity between the chip and the plastic package (chip-to-mold non-planarity), package Reliability (Reliability), etc. Although there is a continuous effort in the industry to improve these technical problems by improving the equipment, materials, process links, there is still no economical and effective solution to some technical problems, especially to warpage, chip drift and surface coplanarity between different chips.

In addition, there are common techniques involved in the fabrication of various high-end semiconductor packages and systems, often involving the placement and attachment of semiconductor devices with high precision. This process step is usually performed by a high precision mounting (pick and place or die binder) equipment, but the mounting speed is limited, so that the production speed is very slow, and the equipment cost is expensive, which becomes a bottleneck for the development and popularization of the technology.

The present application aims to solve several of the core technical problems mentioned above.

Disclosure of Invention

The present application is directed to a novel and novel semiconductor packaging method, semiconductor device and electronic device including the semiconductor device, which at least solve the above and other problems of the prior art.

An aspect of the present application provides a semiconductor packaging method, including: providing at least one semiconductor device and a carrier plate, wherein the at least one semiconductor device respectively has an active surface and a passive surface opposite to each other, the active surface is formed with a connecting terminal, the passive surface is formed with a plurality of first alignment welding parts, and the carrier plate is formed with a plurality of second alignment welding parts corresponding to the first alignment welding parts; placing the at least one semiconductor device on the carrier plate such that the plurality of first alignment bonds are substantially aligned with the plurality of second alignment bonds; forming a plurality of alignment pads by soldering the plurality of first alignment pads and the plurality of second alignment pads such that the at least one semiconductor device is precisely aligned and fixed to the carrier board; forming a plastic package body for coating the at least one semiconductor device by performing plastic package on the side of the carrier plate where the at least one semiconductor device is located; exposing the connection terminal from the molding body; and sequentially forming an interconnection layer and an external terminal on a surface of the molding body exposing the connection terminal such that the connection terminal is electrically connected to the external terminal through the interconnection layer.

Another aspect of the present application provides a semiconductor device packaged by the above semiconductor packaging method.

Yet another aspect of the present application provides an electronic device including the semiconductor device described above.

It should be understood that the above description is only an overview of the present application so that the technical solutions of the present application can be more clearly understood and implemented according to the contents of the specification. In order to make the aforementioned and other objects, features and advantages of the present application more comprehensible, embodiments of the present application are described in detail below.

Drawings

Fig. 1 is a schematic diagram illustrating a chip drift and a chip rotation phenomenon caused by a placement misalignment or a mold flow (mold flow) push during a chip-on-chip (chip-first) fan-out type package according to the related art.

Fig. 2 shows a state diagram of Under Bump Metallization (UBM) and redistribution layer (RDL) trace position mismatch (or misalignment) formed after chip drift and rotation as shown in fig. 1.

Fig. 3 shows a flow chart of a packaging method according to an embodiment of the application.

Fig. 4A to 4G show cross-sectional views for schematically illustrating a packaging method according to an exemplary embodiment of the present application.

Fig. 5A to 5G show cross-sectional views for schematically illustrating a packaging method according to another exemplary embodiment of the present application.

Detailed Description

The present application is intended in the following description to include at least one embodiment with reference to the accompanying drawings, in which like numerals represent the same or similar elements. Although the following description is based primarily on specific embodiments, it should be understood by those skilled in the art that the following description is intended to cover alternatives, modifications, and equivalents, which may be included within the spirit and scope of the present invention as defined by the appended claims and their equivalents, and as supported by the following description and drawings. In the following description, certain specific details are set forth, such as specific configurations, compositions, and processes, etc., in order to provide a thorough understanding of the present application. In other instances, well-known process and manufacturing techniques have not been described in detail in order to avoid unnecessarily obscuring the present application. Furthermore, the various embodiments shown in the figures are schematic representations and are not necessarily drawn to scale.

Semiconductor components (which may also be referred to as semiconductor packages) are a core component of modern electronic devices or products. Semiconductor components can be broadly classified in terms of device number and density into: discrete semiconductor devices, i.e., single chip devices, such as a single digital logic processor, diode, transistor; multi-chip components, such as a module of image sensors (CIS) and image processors (ASIC), a stack of a Central Processing Unit (CPU) and a dynamic memory (DRAM); and system level components, such as radio frequency Front End Modules (FEMs) in cell phones, display screen modules in cell phones and smart watches. Generally, a system-level component includes a wide variety of devices, including semiconductor devices, passive components (resistors, capacitors, inductors), other devices, and even components.

The semiconductor components herein may include active and passive devices including, but not limited to, active devices such as bipolar transistors, field effect transistors, integrated circuits, and passive devices such as chip resistors, capacitors, inductors, Integrated Passive Devices (IPDs), micro-electro-mechanical systems (MEMS), and the like. Various electrical connections are established between various active and passive devices to form circuits that enable the semiconductor assembly to perform high speed calculations and other useful functions.

Currently, semiconductor manufacturing typically involves two complex manufacturing processes, namely front-end wafer fabrication and back-end package fabrication, each of which may involve hundreds of steps. Previous wafer fabrication involves forming a plurality of chips (die) on the surface of the wafer. Each chip is generally identical and contains internally the circuits formed by the electrical connections of the active and/or passive elements. Subsequent package fabrication involves separating individual chips from the finished wafer and packaging them into semiconductor assemblies to provide electrical connections, structural support, and environmental isolation, while facilitating subsequent assembly of the electronic product.

An important goal of semiconductor manufacturing is to produce smaller semiconductor devices, packages, and assemblies. Smaller products, generally higher integration, less power consumption, higher performance and smaller area/volume, are important to market performance of the final product. On the one hand, smaller integrated circuits can be fabricated by improving the previous wafer process, thereby shrinking chips, increasing density and improving performance. On the other hand, the subsequent packaging process can further reduce the size, increase the density and improve the performance of the semiconductor assembly by improving the packaging design, process and packaging material.

In the back-end packaging process, a novel and efficient packaging method is fan-out packaging. Fan-out packages typically employ a packaging technique of encapsulating single or multiple qualified chips (die) from a diced wafer with a molding compound and routing interconnect traces from the connection pads of the chips to external solder balls via a redistribution layer (RDL) for higher I/O density and flexible integration. The fan-out type package may be mainly classified into a chip-first type package and a chip-last type package. chip-first type packages can be classified into a face-down type and a face-up type.

The chip-first/face-down type packaging mainstream process comprises the following main steps: picking up chips from the cut wafer and placing the chips on a carrier plate pasted with an adhesive film so that an active surface of the chips faces the adhesive film; plastically packaging one side provided with the chip by using a molding compound; removing the carrier plate (together with the adhesive film) to expose the active surface of the chip; forming an interconnection layer (including an RDL layer and Under Bump Metallization (UBM)) on an active surface of a chip; forming solder balls on the interconnection layer, wherein the interconnection pads or the interconnection bumps of the chip are electrically connected with the solder balls through the interconnection layer; and dicing to form individual semiconductor elements.

The chip-first/face-up type packaging process and the chip-first/face-down type packaging process can be approximately the same, and the main difference is as follows: picking up a chip and placing the chip on a carrier plate pasted with an adhesive film, wherein the active surface of the chip is opposite to the adhesive film; thinning the molding compound on one side of the active surface of the chip after plastic packaging to expose the interconnection bumps on the active surface of the chip; and the carrier plate may be removed after the formation of the interconnect layer and the solder balls.

In the technical problem faced by the fan-out package at present, the high-precision placement and position fixing of the chip still lack an efficient and economical method. The higher the chip placement accuracy, the higher the equipment cost, the lower the production efficiency, and the difficulty in breaking through the 0.5 micron limit of the chip mounting equipment. In addition, after the chip is placed on the adhesive film, the adhesive film is used for bonding and fixing the chip, but the adhesive film has deformability, and the flowing of the plastic packaging material pushes the chip in the plastic packaging process, so that the chip is displaced and rotated on the adhesive film. The higher temperatures used in the molding process further exacerbate this problem. Another source of chip displacement and rotation is internal stresses within the plastic encapsulant. Specifically, in the existing chip-first/face-up type packaging process, the plastic packaging process comprises three stages of heating and injection molding, partial curing of the plastic packaging material in high-temperature keeping and cooling. Usually followed by a constant temperature heating step to fully cure the molding compound. The thermal expansion coefficients of the chip, the molding compound, the adhesive film, the carrier plate, and the like are different, so that the mismatch of the thermal expansion coefficients of various materials and the curing shrinkage of the molding compound in the plastic packaging process cause the uneven internal stress of the molding compound, further causing the chip to drift and/or rotate (as shown in the chip arrangement at the lower right of fig. 1) and the warpage of the molding compound (in the form of the chip and the carrier plate being overmolded by the molding compound). Chip drift and/or rotation in turn causes subsequently formed Rewiring (RDL) traces and Under Bump Metallization (UBM) position mismatches or misalignments (as shown in the upper right-hand state of fig. 2, where chip drift and rotation occurs), which can result in significant yield degradation. The warpage of the plastic package body causes difficulty in subsequent packaging processes (including forming RDL and UBM), and even the subsequent processes cannot be continued in severe cases.

The present application aims to provide a novel and breakthrough packaging method that can at least solve the above technical problems.

The packaging method according to the embodiment of the application utilizes the self-alignment capability of the alignment solder joint (joint) between the semiconductor device and the carrier board in the state that the solder is molten or partially molten to automatically and precisely align the semiconductor device to the target position on the carrier board and achieve the position fixing of the semiconductor device after the solder is solidified, wherein a first alignment solder joint and a corresponding second alignment solder joint (for example, one of the alignment solder bump and the other of the alignment solder bump or both of the alignment solder bump are preformed on the passive surface (i.e. the opposite surface of the active surface) of the semiconductor device and one side of the carrier board respectively). The packaging method melts one (or both) of the first alignment solder part and the second alignment solder part to form an alignment solder joint after placing the semiconductor device at a target position on the carrier plate to contact the first alignment solder part and the second alignment solder part with each other, at which time, if the semiconductor device is not accurately aligned to the target position on the carrier plate (i.e., the first alignment solder part and the second alignment solder part are not aligned), the alignment solder joint in a molten or partially molten state (liquid or partially liquid) automatically and accurately introduces the semiconductor device to the target position based on the principle of minimum surface energy to achieve surface energy minimization, and the alignment solder joint keeps the semiconductor device firmly fixed at the target position after solidification. The first and second alignment welds are optimally designed (in terms including but not limited to volume, geometry, composition, location, distribution, and number, etc.) to enable the most accurate, efficient, and reliable self-alignment capability. Because the semiconductor device is fixed on the carrier plate by adopting the welding mode instead of the adhesive film bonding mode, the warping problem is improved, the possible drifting and rotating problems of the semiconductor device in the plastic packaging process are prevented by a firm welding mode, the placing deviation of a certain degree can be allowed when the semiconductor device is picked up and placed in view of the self-aligning capacity of the alignment welding point, the requirement on the placing precision of the semiconductor device (especially for a chip and place or die bonder) can be obviously reduced, the picking and placing operation speed of the semiconductor device can be obviously improved, the process efficiency is improved, and the process cost is reduced.

As used herein, the term "semiconductor device" may refer to a chip (also interchangeably referred to as die, integrated circuit) produced by a chip factory (fab), i.e., a chip that has not been packaged after wafer dicing and testing, and which may typically have only interconnect pads (pads) for external connection. The semiconductor device may also be a pre-processed (at least partially packaged) chip such as an interconnect bump (bump) formed on an interconnect pad, or the semiconductor device may have additional structures such as a stacked chip and a packaged chip, as desired.

The term "active surface" as used herein generally refers to a side surface of a semiconductor device having a circuit function, which has interconnect pads (or interconnect bumps formed on the interconnect pads) thereon, and may also be interchangeably referred to as a front surface or a functional surface. An active surface and the other side surface (which may be interchangeably referred to as a passive surface or a back surface) of the semiconductor device having no circuit function are opposed to each other.

The term "connection terminal" as used herein generally refers to an interconnect pad or an interconnect bump on the active surface of a semiconductor device.

The term "alignment weld" as used herein generally refers to a structure that may be welded to a corresponding other alignment weld for alignment by welding methods known in the art.

Fig. 3 shows a schematic flow diagram of a packaging method according to an embodiment of the present application. As shown in fig. 3, the packaging method includes the following steps:

s310: providing at least one semiconductor device and a carrier plate, wherein the semiconductor device respectively has an active surface and a passive surface opposite to each other, the active surface is formed with a connection terminal thereon, the passive surface is formed with a plurality of first alignment welding parts thereon, and the carrier plate is formed with a plurality of second alignment welding parts respectively corresponding to the plurality of first alignment welding parts thereon.

In some embodiments, the semiconductor device is a plurality. As an example, the plurality of semiconductor devices may be at least partially different from each other in function, size, or shape, and may be the same as each other. It should be understood that the type and specific number of the semiconductor devices may be appropriately selected according to specific process conditions or actual requirements (for example, the size and shape of the carrier board and the semiconductor devices, the placement pitch or package size and shape of the semiconductor devices, manufacturing process specifications, functional design of semiconductor assemblies, etc.), and the present application is not particularly limited thereto.

In some embodiments, the carrier is a glass carrier, a ceramic carrier, a metal carrier, an organic polymer material carrier, or a silicon wafer, or a combination of two or more of the above carriers.

In some embodiments, either one of the first and second alignment solder portions is an alignment solder bump and the other is an alignment pad corresponding to the alignment solder bump. In other embodiments, the first alignment welding part and the second alignment welding part are both alignment welding bumps, and the melting points of the first alignment welding part and the second alignment welding part can be the same or different. As an example, the alignment solder bumps may be pre-fabricated on a semiconductor device (e.g., a wafer) or a carrier using a bumping process (e.g., electroplating, ball-planting, stencil printing, evaporation/sputtering, etc.) known in the art. As an example, the alignment pad may be fabricated on a semiconductor device (e.g., a wafer) or a carrier board in advance using a deposition (e.g., metal layer) -photolithography-etching process. It should be understood that any other weld configuration or form may be used as long as the first and second alignment welds are capable of welding to each other for alignment purposes.

In some embodiments, the first alignment solder and the second alignment solder correspond to each other in volume, size, geometry, composition, distribution, location, and number, so that the semiconductor devices can be precisely aligned to the respective target positions on the carrier board by soldering to each other.

It should be understood that the specific volume, size, geometry, composition, distribution, location and number of the first alignment bond and/or the second alignment bond may be appropriately selected according to specific process conditions or actual requirements (for example, the size and shape of the carrier board and the semiconductor device, the placement pitch or package size and shape of the semiconductor device, etc.), and the present application is not particularly limited thereto. For example, the first alignment bonding parts may be formed in substantially the same volume, size, geometry or composition for all semiconductor devices regardless of whether functions, sizes or shapes are identical to each other, and the second alignment bonding parts on the carrier board may be formed in substantially the same volume, size, geometry or composition, so as to reduce the complexity of subsequent processes and improve the packaging efficiency. For another example, for semiconductor devices with different functions, sizes or shapes, the first alignment bond and the second alignment bond may be formed with different volumes, sizes, geometries or compositions so that different bond pad heights may be formed after subsequent bonding to achieve a particular function or to meet a particular requirement. In some embodiments, for a plurality of semiconductor devices, the first alignment bond and/or the second alignment bond are disposed such that active surfaces of the plurality of semiconductor devices are in a same plane parallel to the carrier board after subsequent formation of the alignment bond. In some embodiments, for a plurality of semiconductor devices, the first alignment bond and/or the second alignment bond are disposed such that passive surfaces of the plurality of semiconductor devices lie in a same plane parallel to the carrier board after formation of the alignment bond in a subsequent process. For another example, at least three first alignment bonding portions distributed substantially regularly may be formed on each of the semiconductor devices, so that the passive surface of the semiconductor device can be firmly and stably maintained in a plane substantially parallel to the carrier plate by the bonding of the first alignment bonding portions and the second alignment bonding portions.

In some embodiments, the connection terminals are interconnect bumps, as shown in fig. 4A. By way of example, the interconnect bumps may be pre-fabricated on interconnect pads on a semiconductor device (e.g., a wafer) using a bumping process known in the art (e.g., electroplating, ball-planting, stencil printing, evaporation/sputtering, etc.). For example, the interconnect bump may be in the form of a conductive pillar. In an alternative embodiment, the connection terminal is the interconnect pad itself, as shown in fig. 5A.

S320: placing the at least one semiconductor device on the carrier plate such that the plurality of first alignment bonds are substantially aligned with the plurality of second alignment bonds.

In some embodiments, the "substantial alignment" includes the first alignment bond and the second alignment bond contacting each other, respectively, but not being precisely centered in a direction perpendicular to the passive surface. By "centered" herein is generally meant that the centers of the first and second alignment welds are aligned in a direction perpendicular to the passive surface. It should be noted that "substantial alignment" of the first alignment weld with the second alignment weld means that there is at least contact between the first alignment weld and the second alignment weld to the extent that self-alignment is possible by virtue of the principle of minimum surface energy of the alignment weld in a molten or partially molten state during welding, as described below, and thus "substantial alignment" includes a state of imprecise alignment but at least physical contact, but may not exclude a state of exactness.

It should be understood that, when the semiconductor device is placed on the carrier board in step S320, the passive surface of the semiconductor device faces the carrier board (i.e., the surface on which the first alignment solder part is formed), and the active surface of the semiconductor device faces away from the carrier board.

S330: forming a plurality of alignment pads by soldering the plurality of first alignment pads and the plurality of second alignment pads so that the at least one semiconductor device is precisely aligned and fixed to the carrier board.

It should be noted that "precise alignment" indicates a state where a deviation between an actual position and a target position of the semiconductor device on the carrier board is within a tolerance in the art. It should be understood that the precise alignment is achieved using the principle of minimum surface energy exhibited by the weld points formed by welding the first and second alignment welds in a molten or partially molten state during welding. In particular, when the first alignment solder part and the second alignment solder part are in contact with each other but are not precisely centered in a direction perpendicular to the passive surface or carrier plate of the semiconductor device, in the welding process, one of the first alignment welding part and the second alignment welding part which is used as an alignment welding bump is melted or partially melted and wets the other one which is used as an alignment welding pad or another alignment welding bump, or both the first and second alignment welds melt or partially melt as alignment weld bumps, thereby forming an alignment weld in a molten or partially molten state, wherein the alignment weld in the molten or partially molten state tends to move in a deformation based on a minimum surface energy principle to bring the first alignment weld and the second alignment weld closer to a centered state, thereby driving the semiconductor device which is lighter relative to the carrier plate to be accurately aligned to the target position on the carrier plate.

It should be understood that after soldering the first alignment solder part and the second alignment solder part, the passive surface of the semiconductor device and the carrier board are spaced apart to form a space therebetween due to the height of the alignment solder point itself (in a direction perpendicular to the passive surface of the semiconductor device or the carrier board) thus formed.

In some embodiments, the alignment solder bump is made of solder, and the soldering may be performed by various means known in the art for melting solder, including but not limited to reflow soldering, laser soldering, high frequency soldering, infrared soldering, and the like.

In some embodiments, after S330, S331 is further included: and turning the semiconductor device and the carrier plate as a whole to enable the active surface of the semiconductor device to be downward, and cooling the alignment welding spot after melting or partially melting the alignment welding spot again to solidify the alignment welding spot. It will be appreciated that the alignment pads, which are re-melted or partially melted at this time, are moderately elongated by the weight of the semiconductor device, whereby the self-alignment accuracy can be further improved. It should be noted that the semiconductor device will not fall off the carrier plate due to its own weight because of the surface energy of the alignment solder in the molten state or the partially molten state. As an alternative embodiment, in S310, viscous flux is pre-coated on the plurality of first and/or second alignment solders, and S330 includes S330': before the soldering is performed, the semiconductor device and the carrier board are turned over as a whole so that the active surface of the semiconductor device faces downward. It should be appreciated that the alignment pads, which are melted or partially melted during soldering, are moderately elongated by the weight of the semiconductor device after being flipped at this time, whereby the self-alignment accuracy can be further improved. It should be noted that, since the viscous flux adheres the semiconductor device to the carrier, the semiconductor device will not fall off from the carrier due to its own weight after being turned over. It should be understood that before S340 described below, the semiconductor device and the carrier board as a whole need to be flipped again.

In some embodiments, when the semiconductor device is a plurality of, S330 includes S330 ": when the semiconductor devices and the carrier plate are precisely aligned and the alignment welding spots are still in a molten or partially molten state, flattening processing is performed on the active surfaces of the plurality of semiconductor devices by using a flattening plate (leveling plate), so that the active surfaces of the plurality of semiconductor devices are basically positioned in the same plane parallel to the carrier plate. As an example, S330 "includes: placing the platen over active surfaces of the plurality of semiconductor devices; pressing the platen toward the carrier plate such that the active surfaces of the plurality of semiconductor devices lie substantially in a same plane parallel to the carrier plate; while maintaining the pressing, cooling to substantially solidify the alignment weld; and removing the platen. As an alternative embodiment, when the semiconductor device is plural, after S330, S332 is further included: and after the alignment welding spots are melted or partially melted again, flattening the active surfaces of the plurality of semiconductor devices by using a flattening plate so that the active surfaces of the plurality of semiconductor devices are basically positioned in the same plane parallel to the carrier plate. As an example, the S332 includes: melting or partially melting the alignment welding spots again; placing the platen over active surfaces of the plurality of semiconductor devices; pressing the platen toward the carrier plate such that the active surfaces of the plurality of semiconductor devices lie substantially in a same plane parallel to the carrier plate; while maintaining the pressing, cooling to substantially solidify the alignment weld; and removing the platen. It will be appreciated that since the platen is not removed until the alignment pad has substantially solidified, the surface energy of the molten pad is prevented from restoring the semiconductor device to its original height prior to the platen.

Thus, the active surfaces of all semiconductor devices can be made precisely flush and at the same height. It will be appreciated that a suitable pressure needs to be applied to the platen such that the alignment pads in the molten or partially molten state are suitably deformed and the resulting vertical (with respect to the active surface of the semiconductor device or the carrier plate) displacement of the platen is suitable to prevent damage to the semiconductor device. As an example, a solder trap (solder trap) is formed in advance around the second alignment solder portion of the carrier plate, thereby preventing uncontrolled random flow of excess molten solder during the pressing process.

In some embodiments, the flattening process using a flattening plate described above is combined with the welding process or the remelting process after the inversion described above. As an example, S330 is performed after S330 'is performed in S330, or S332 is performed after S330 including S330' is performed, or S331 is performed after S330 including S330 "is performed, or S332 is performed when S331 is performed.

S340: and forming a plastic package body for coating the at least one semiconductor device by performing plastic package on the side of the carrier plate where the semiconductor device is located.

It should be understood that by the plastic encapsulation not only the active surface and the side faces of the semiconductor device are encapsulated, but also the space between the passive surface of the semiconductor device and the carrier plate is filled with the encapsulation.

In some embodiments, the plastic encapsulation is performed using a molding compound of a resinous material (e.g., epoxy).

In some embodiments, the plastic molding is performed using a molding process such as injection molding, printing, and optionally in combination with an underfill (underfil) process.

S350: and exposing the connecting terminal from the plastic package body.

In some embodiments, when the connection terminal is an interconnect bump, the interconnect bump is exposed by thinning (e.g., grinding, etching, or ablating, etc.) the molding compound.

In some embodiments, when the connection terminal is an interconnection pad, the interconnection pad is exposed by forming an opening on the molding body. By way of example, the openings may be formed using laser ablation (e.g., laser drilling). By way of example, the openings may be formed by mechanical drilling. As an example, prior to forming the opening, the plastic package may be thinned to meet product design requirements and/or to facilitate the opening.

S360: sequentially forming an interconnection layer and an external terminal on a surface of the molding body exposing the connection terminal such that the connection terminal is electrically connected to the external terminal through the interconnection layer.

In some embodiments, the interconnection layer includes a redistribution layer (RDL) and an Under Bump Metallurgy (UBM) in this order in a direction away from the connection terminal, thereby achieving conductive connection of the connection terminal with the external terminal. It should be understood that the interconnect layer further includes an insulating layer for achieving electrical insulation between the conductive paths, and the specific number and material of the insulating layer may be appropriately selected according to specific process conditions or needs, which is not particularly limited in the present application.

In some embodiments, the external terminals are solder balls.

In some embodiments, the external terminal is a pad.

In some embodiments, after S340, further comprising: and removing the carrier plate. As an example, the carrier is removed between S340 and S350 or between S350 and S360 or after S360.

In some embodiments, the carrier plate is removed by lift-off, etching, ablation, grinding, and the like, as known in the art. As an example, when a lift-off process is used, the solder between the carrier board and the semiconductor device (i.e. the alignment pads) may be desoldered to facilitate the lift-off of the carrier board from the plastic package body.

In some embodiments, some or all of the alignment pads are also removed while or after the carrier plate is removed. By way of example, some or all of the alignment pads may be removed by desoldering, etching, ablating, or grinding, among other processes known in the art. In some embodiments, some or all of the alignment pads are left as part of the final semiconductor assembly (i.e., the finished package) for electrical connections (e.g., power and ground), heat sinking, mechanical structures, etc.

In some embodiments, after removing the carrier plate, further comprising: and thinning (such as grinding, etching or ablating and the like) the surface of the plastic package body, from which the carrier plate is removed. As an example, it may be thinned to the passive surface of the semiconductor device, or the thinned portion comprises a portion of the passive surface side of the semiconductor device. It should be understood that the alignment pads remaining after the carrier board is removed are also removed by the thinning process. This can further reduce the thickness of the final semiconductor module.

In some embodiments, the passive device is packaged with the at least semiconductor device in substantially the same way as the above-described embodiments.

In some embodiments, after S360, further comprising: and (6) cutting.

It should be understood that the dicing process may be performed to fabricate individual semiconductor devices or not performed according to the packaging specifications of the semiconductor devices, including but not limited to wafer level packaging, chip level packaging, system level packaging.

Hereinafter, the packaging method according to the present application will be described in more detail with reference to exemplary embodiments.

As shown in fig. 4A, a plurality of semiconductor devices and a carrier plate 420 are provided. At least two of the semiconductor devices 410 (and/or 410') are different, e.g., different in size and/or function, among the plurality of semiconductor devices. A plurality of interconnection bumps 412 conductively connected to interconnection pads (not shown), respectively, are distributed on the active surface 411 of each semiconductor device 410 (and/or 410'), and a plurality of alignment solder bumps 414 are formed on the passive surface 413. A plurality of alignment pads 424 are formed on a surface of the carrier plate 420 in the same arrangement (or relative position) as the alignment bumps 414 on each semiconductor device 410 (and/or 410'). Alternatively, passive devices may be provided in a similar structure in addition to semiconductor devices. For example, reference numeral 410' as shown in fig. 4 may be replaced with a passive device.

As shown in fig. 4B, the semiconductor device 410 (and/or 410') is placed on the carrier board 420 such that the alignment solder bumps 414 are in contact with the corresponding alignment pads 424. At this point, alignment solder bump 414 is misaligned with alignment pad 424 (i.e., vertical centerline L1 of alignment solder bump 414 and vertical centerline L2 of alignment pad 424 are not coincident).

As shown in fig. 4C, alignment solder bumps 414 and alignment pads 424 are soldered (e.g., by reflow) to form alignment pads 416. During the soldering process, the alignment solder bump 414 in a molten state wets the alignment pad 424 and self-aligns with the alignment pad 424 based on its minimum surface energy principle (i.e., the vertical center line L1 of the alignment solder bump 414 coincides with the vertical center line L2 of the alignment pad 424), so that the semiconductor device 410 (and/or 410') is brought into precise alignment on the carrier board 420. After the soldering is completed, the passive surface 413 of the semiconductor device 410 (and/or 410') is spaced apart from the carrier plate 420 to form a space.

As shown in fig. 4D, the side of the carrier plate 420 to which the semiconductor device 410 (and/or 410') is bonded is subjected to plastic molding. The molding compound 430 encapsulates all surfaces of the semiconductor device 410 (and/or 410'), including the active surface 411 (and the interconnect bumps 412), the passive surface 413, and the side surfaces. The space below the passive surface 413 may employ an underfill (underfil) process.

As shown in fig. 4E, the side of the plastic package body 430 where the active surface 411 (or the interconnect bump 412) is located is thinned until the interconnect bump 412 is exposed.

As shown in fig. 4F, a redistribution layer (RDL) trace 442, a UBM 444, and a solder ball 450 are sequentially formed from bottom to top on the surface of the plastic package body 430 where the interconnect bump 412 is exposed, so as to form a conductive path from the interconnect bump 412 to the corresponding solder ball 450. In this process, a dielectric layer 446 is also formed to electrically insulate between the conductive paths, particularly when forming RDL traces 442 and/or UBM 444. Then, the carrier 420 is removed from the plastic package body 430. When the carrier board 420 is removed, a portion of the alignment pads 416 (including the alignment pads 424) may also be removed at the same time.

As shown in fig. 4G, the other surface of the molding compound 430 (i.e., the side where the carrier plate 420 is removed) is thinned to remove the remaining alignment pads 416 and a portion of the side of the inactive surface 413 of the semiconductor device 410 (and/or 410').

It should be understood that other processing (e.g., additional processing required for heterogeneous integrated packaging) may be further performed before, during, or after the steps of the packaging method described above, depending on the actual packaging needs.

Finally, although not shown, dicing (singulation) may be performed according to the packaging specifications of the semiconductor device to complete the fabrication of the individual semiconductor devices.

Fig. 5A to 5G show cross-sectional views for schematically illustrating a packaging method according to another exemplary embodiment of the present application. It is to be noted that the same or similar parts as those of the foregoing exemplary embodiment according to fig. 4A to 4G will not be described again hereinafter.

As shown in fig. 5A, a plurality of semiconductor devices and a carrier plate 520 are provided. A plurality of interconnect pads 512 are distributed on the active surface 511 of each semiconductor device 510 (and/or 510'), and a plurality of alignment solder bumps 514 are formed on the passive surface 513. A plurality of alignment pads 524 are formed on a surface of the carrier 520.

As shown in fig. 5B, semiconductor device 510 (and/or 510') is placed on carrier board 520 such that alignment solder bumps 514 contact corresponding alignment pads 524. At this point, the alignment solder bump 514 is misaligned with the alignment pad 524.

As shown in fig. 5C, alignment solder bumps 514 and alignment pads 520 are soldered to form alignment pads 516, thereby achieving precise alignment of semiconductor device 510 (and/or 510') on carrier board 520 based on the principle of minimum surface energy.

As shown in fig. 5D, after the pressing plate P is placed on the active surface 511 of the semiconductor device 510 (and/or 510 ') while the alignment pads 516 are still in a molten state, the pressing plate P is pressed (i.e., toward the carrier plate 520) to perform a pressing process such that the active surfaces of the plurality of semiconductor devices 510, 510' are in the same plane parallel to the carrier plate 520. Subsequently, the temperature is decreased while the pressing is maintained to solidify the alignment pads 516, and then the platen plate P is removed.

As shown in fig. 5E, the side of the carrier plate 520 to which the semiconductor devices 510 (and/or 510') are bonded is subjected to plastic molding. The molding compound 530 encapsulates all surfaces of the semiconductor device 510 (and/or 510').

As shown in fig. 5F, the carrier 520 is removed from the plastic package 530. The active surface 511 (or interconnect pad 512) side of the molding 530 is drilled (e.g., laser drilled) to expose the interconnect pad 512. Before drilling, the plastic package body 530 can be thinned as needed.

As shown in fig. 5G, redistribution layer (RDL) traces 542, UBM 544, and solder balls 550 are sequentially formed on the surface of the molding compound 530 where the interconnect pads 512 are exposed, to form conductive paths from the interconnect pads 512 to the corresponding solder balls 550. In this process, a dielectric layer 546 is also formed to electrically isolate the conductive paths, particularly when forming RDL traces 542 and/or UBMs 544.

Finally, although not shown, dicing may be performed according to the functional design specifications of the semiconductor device to complete the fabrication of individual semiconductor devices.

It is apparent that those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the application. Thus, to the extent that such modifications and variations fall within the scope of the claims and their equivalents, it is intended that the present disclosure encompass such modifications and variations as well.

Claims

1. A semiconductor packaging method, comprising:

s310: providing at least one semiconductor device and a carrier plate, wherein the at least one semiconductor device respectively has an active surface and a passive surface opposite to each other, the active surface is formed with a connecting terminal, the passive surface is formed with a plurality of first alignment welding parts, and the carrier plate is formed with a plurality of second alignment welding parts corresponding to the first alignment welding parts;

s320: placing the at least one semiconductor device on the carrier plate such that the plurality of first alignment bonds are substantially aligned with the plurality of second alignment bonds;

s330: forming a plurality of alignment pads by soldering the plurality of first alignment pads and the plurality of second alignment pads such that the at least one semiconductor device is precisely aligned and fixed to the carrier board;

s340: forming a plastic package body for coating the at least one semiconductor device by performing plastic package on the side of the carrier plate where the at least one semiconductor device is located;

s350: exposing the connection terminal from the molding body; and

s360: sequentially forming an interconnection layer and an external terminal on a surface of the molding body exposing the connection terminal such that the connection terminal is electrically connected to the external terminal through the interconnection layer;

the semiconductor packaging method further includes, after the S340 or after the S360: and removing the carrier plate and the alignment welding points.

2. A semiconductor packaging method according to claim 1, wherein either one of the plurality of first alignment lands and the plurality of second alignment lands has a form of an alignment bonding bump, and the other has a form of an alignment bonding pad corresponding to the alignment bonding bump; or the plurality of first alignment welds and the plurality of second alignment welds each have the form of an alignment weld bump.

3. A semiconductor packaging method according to claim 2, wherein the alignment solder bump is made of solder, and the soldering is performed by melting the solder.

4. The semiconductor packaging method of claim 1, wherein substantially aligning the plurality of first alignment bonds with the plurality of second alignment bonds comprises: such that the first and second plurality of alignment welds respectively contact each other, but are not precisely centered in a direction perpendicular to the passive surface.

5. The semiconductor packaging method according to claim 3, wherein in the S310, viscous flux is pre-coated on the plurality of first and/or second alignment-solder parts, and the S330 comprises S330': before the soldering is performed, the at least one semiconductor device is turned over as a whole with the carrier plate so that the active surface of the at least one semiconductor device is directed downwards.

6. The semiconductor packaging method according to claim 3, wherein after the S330, the semiconductor packaging method further comprises S331: and turning the at least one semiconductor device and the carrier plate as a whole to enable the active surface to face downwards, and melting the alignment welding spots or partially melting the alignment welding spots again and then cooling and solidifying the alignment welding spots.

7. A semiconductor packaging method according to claim 3, wherein when the at least one semiconductor device is plural, the S330 includes S330 ": when the plurality of semiconductor devices are precisely aligned with the carrier plate and the plurality of alignment welding spots are still in a molten or partially molten state, flattening the active surfaces of the plurality of semiconductor devices by using a flattening plate so that the active surfaces of the plurality of semiconductor devices are basically positioned in the same plane parallel to the carrier plate until the alignment welding spots are basically solidified, and then removing the flattening plate.

8. The semiconductor packaging method according to claim 3, wherein when the at least one semiconductor device is plural, the semiconductor packaging method further comprises, after the S330, S332: and after the alignment welding spots are melted or partially melted again, flattening the active surfaces of the plurality of semiconductor devices by using a flattening plate so that the active surfaces of the plurality of semiconductor devices are basically positioned in the same plane parallel to the carrier plate until the alignment welding spots are basically solidified, and then removing the flattening plate.

9. The semiconductor package method according to claim 3, wherein solder wells are pre-formed around the second alignment solder portions of the carrier.

10. A semiconductor packaging method according to claim 1, further comprising: and thinning the surface of the plastic package body, from which the carrier plate is removed.

11. A semiconductor packaging method according to claim 10, wherein the thinning is performed such that a portion of the side of the at least one semiconductor device on which the passive surface is located is removed.

12. A semiconductor packaging method according to claim 1, further comprising: after the interconnect layer and the external terminal are formed, dicing is performed.

13. The semiconductor packaging method according to claim 1, wherein the connection terminals are interconnection bumps, and exposing the connection terminals from the molding body comprises: the interconnection bumps are exposed by thinning the molding body.

14. The semiconductor packaging method according to claim 1, wherein the connection terminals are interconnection pads, and exposing the connection terminals from the molding body comprises: the interconnect pad is exposed by forming an opening in the molding compound.

15. A semiconductor packaging method according to claim 1, further comprising: and when the carrier plate is removed or after the carrier plate is removed, at least part of the alignment welding points are also removed.

16. The semiconductor packaging method according to claim 1, wherein the alignment pads are at least partially retained for at least one of heat dissipation and mechanical structure of the semiconductor component manufactured by the semiconductor packaging method when or after the carrier board is removed.

17. A semiconductor packaging method according to claim 1, wherein the interconnection layer comprises a re-wiring layer and an under bump metallurgy layer in this order in a direction away from the connection terminal.

18. A semiconductor component packaged by the semiconductor packaging method according to any one of claims 1 to 17.

19. An electronic device comprising the semiconductor assembly of claim 18.