TWI831089B - Semiconductor packaging method, semiconductor assembly, and electronic device including the same - Google Patents

Abstract

The invention discloses a semiconductor packaging method, a semiconductor assembly and an electronic device including the semiconductor assembly. The semiconductor packaging method comprises the steps: providing at least one semiconductor device and a carrier plate, forming a connection terminal on the active surface of the semiconductor device, forming a plurality of first alignment welding parts on a passive surface; forming a plurality of corresponding second alignment welding parts on the carrier plate; placing the semiconductor device on the carrier plate so that the first alignment welding parts are substantially aligned with the second alignment welding parts; forming an alignment welding spot by welding the first alignment welding parts and the second alignment welding parts so that the semiconductor device is accurately aligned and fixed to the carrier plate; carrying out plastic package on the side, where the semiconductor device is located, of the carrier plate to form a plastic package body wrapping the semiconductor device; exposing the connection terminal from the plastic package body; and sequentially forming an interconnection layer and an external terminal on the surface of the plastic package body so that the connection terminal is electrically connected to the external terminal through the interconnection layer, wherein the surface exposes the connection terminal.

Description

Semiconductor packaging method, semiconductor component and electronic device including same

Embodiments of the present application relate to the field of semiconductor manufacturing technology, and in particular to semiconductor packaging methods, semiconductor components, and electronic equipment including the semiconductor components.

Semiconductor packages and systems have always pursued density, smallness, lightness and thinness in design, while striving to achieve high integration and multi-functionality in terms of functionality. Currently, a variety of packaging technologies are proposed to meet the above technical requirements, such as fan-out wafer-level packaging, chiplet, heterogeneous integration, 2.5D/3D ) package. These packaging technologies have different advantages and characteristics, but there are also some technical challenges. Taking the existing fan-out package as an example, it faces many technical problems, such as warpage, die shift, surface flatness (toporgraphy), and non-coplanarity between the chip and the plastic package (chip). -to-mold non-planarity), packaging reliability (Reliability), etc. Although the industry continues to work hard to improve these technical problems by improving equipment, materials, and processes, there is still no economical and effective solution to some technical problems, especially warpage, wafer drift, and surface coplanarity between different wafers. plan.

In addition, there are some common technologies in the manufacturing process of various high-end semiconductor packaging and systems, which often involve high-precision placement and fixation of semiconductor devices. This process step is usually performed by high-precision pick and place or die bonder equipment, but its placement speed is limited, making the production speed very slow, and the equipment cost is expensive, which has become a major bottleneck in the development and popularization of technology.

This application aims to solve several core technical problems mentioned above.

The purpose of this application is to propose a new breakthrough semiconductor packaging method, a semiconductor component, and an electronic device containing the semiconductor component, so as to at least solve the above and other technical problems existing in the prior art.

One aspect of the present application provides a semiconductor packaging method, including: providing at least one semiconductor device and a carrier, wherein the at least one semiconductor device respectively has an active surface and a passive surface opposite to each other, and the active surface is formed with A connection terminal, a plurality of first alignment welding portions are formed on the passive surface, and a plurality of second alignment welding portions respectively corresponding to the plurality of first alignment welding portions are formed on the carrier board ; Place the at least one semiconductor device on the carrier board so that the plurality of first alignment soldering portions are substantially aligned with the plurality of second aligning soldering portions; by aligning the plurality of first alignment soldering portions; The alignment welding portion and the plurality of second alignment welding portions are welded to form a plurality of alignment welding points, so that the at least one semiconductor device is accurately aligned and fixed to the carrier board; by forming a plurality of alignment welding points on the carrier board Molding the side of the at least one semiconductor device to form a plastic encapsulation body covering the at least one semiconductor device; exposing the connection terminals from the plastic encapsulation body; and exposing the connection terminals on the surface of the plastic encapsulation body An interconnection layer and external terminals are sequentially formed on the substrate, so that the connection terminals are electrically connected to the external terminals through the interconnection layer.

Another aspect of the present application provides a semiconductor element packaged by the above semiconductor packaging method.

Another aspect of the present application provides an electronic device including the above-mentioned semiconductor element.

It should be understood that the above description is only an overview of the present application, so that the technical solution of the present application can be understood more clearly, so that it can be implemented according to the content of the description. In order to make the above and other objects, features and advantages of the present application more apparent and understandable, specific embodiments of the present application are described in detail below.

This application includes the following description of at least one embodiment with reference to the accompanying drawings, in which like numerals refer to the same or similar components. Although the following description is primarily based on specific embodiments, it will be understood by those of ordinary skill in the art that the following description is intended to cover all aspects of the application that may be included in the application as defined by the appended claims and their equivalents and as supported by the following description and drawings. Substitutions, modifications, and equivalent technical means or solutions within the concept and scope of the invention. In the following description, some specific details, such as specific configurations, compositions, processes, etc., are given in order to provide a full understanding of the present application. In other instances, specific details of well-known processes and manufacturing techniques have not been described in order to avoid unnecessarily obscuring the present application. Furthermore, the various embodiments shown in the drawings are schematic illustrations and not necessarily to scale.

Semiconductor components (also called semiconductor packages) are the core components of modern electronic equipment or products. Semiconductor components can be roughly divided in terms of device quantity and density: discrete semiconductor components, that is, single-chip components, such as a single digital logic processor, diode, transistor; multi-chip components, such as image sensors (CIS) and image processor (ASIC) modules, central processing unit (CPU) and dynamic memory device (DRAM) stack; and system-level components, such as RF front-end modules (FEM) in mobile phones, mobile phones and Display module in smart watch. Usually, system-level components include a wider range of devices. In addition to semiconductor devices, there are also passive components (resistors, capacitors, inductors) and other devices and even components.

Semiconductor components in this article may include active and passive components, including but not limited to bipolar transistors, field effect transistors, integrated circuits and other active components, and chip resistors, capacitors, inductors, integrated passive components ( IPD), microelectromechanical systems (MEMS) and other passive devices. Various electrical connections are established between various active and passive devices to form circuits that enable semiconductor components to perform high-speed calculations and other useful functions.

Currently, semiconductor manufacturing typically involves two complex manufacturing processes, front-end wafer manufacturing and back-end packaging manufacturing, each of which may involve hundreds of steps. Front-end wafer manufacturing involves forming multiple dies (dies) on the surface of a wafer. Each wafer is typically identical and contains circuitry formed by electrically connecting active and/or passive elements. Back-end packaging manufacturing involves separating individual wafers from completed wafers and packaging them into semiconductor components to provide electrical connections, structural support, and environmental isolation while facilitating subsequent assembly of electronic products.

An important goal of semiconductor manufacturing is to produce smaller semiconductor devices, packages, and components. Smaller products usually have higher integration, consume less power, have higher performance, and have smaller area/volume, which is very important for the market performance of the final product. On the one hand, smaller integrated circuits can be made by improving the front-end wafer process, thereby shrinking the wafer, increasing density and improving performance. On the other hand, the back-end packaging process can further reduce the size, increase density and improve performance of semiconductor components by improving packaging design, processes and packaging materials.

Currently, in the back-end packaging process, a relatively novel and efficient packaging method is fan-out packaging. Fan-out packaging typically uses molding compound to encapsulate single or multiple qualified dies (dies) from diced wafers and lead interconnect traces from the die's connection pads to the outside through a redistribution layer (RDL). Solder balls to achieve higher I/O density and flexible integration packaging technology. Fan-out packaging can be mainly divided into chip-first packaging and chip-last packaging. Chip-first packages can be divided into active surface-down (face-down) and active surface-up (face-up) types.

The mainstream process of chip-first/face-down packaging may include the following main steps: picking up the wafer from the diced wafer and placing it on a carrier plate with an adhesive film so that its active surface faces the adhesive film; applying molding compound Molding the side on which the chip is mounted; removing the carrier (together with the adhesive film) to expose the active surface of the chip; forming interconnect layers (including RDL layers and under-bump metallization (UBM) on the active surface of the chip )); forming solder balls on the interconnect layer, wherein the interconnect pads or interconnect bumps of the wafer are electrically connected to the solder balls through the interconnect layer; and cutting to form independent semiconductor components.

The chip-first/face-up packaging process can be roughly the same as the chip-first/face-down packaging process. The main difference is that when the chip is picked up and placed on the carrier plate with adhesive film, its active surface backing to the adhesive film; thinning the molding compound on the active surface side of the wafer after molding to expose the interconnect bumps on the active surface of the wafer; and the carrier board can be removed after the interconnect layers and solder balls are formed.

Among the technical problems currently faced by fan-out packaging, there is still a lack of efficient and economical methods for high-precision placement and position fixation of chips. Often, the higher the wafer placement accuracy, the higher the equipment cost and the lower the production efficiency. Moreover, it is difficult for the accuracy of wafer loading equipment to exceed the 0.5 micron limit. In addition, after the wafer is placed on the adhesive film, it is bonded and fixed in position by the adhesive film. However, the adhesive film is deformable. During the plastic sealing process, the flow of the plastic sealing material will push the wafer, causing the wafer to move on the adhesive film. Displacement and rotation. The higher temperatures used in the encapsulation process exacerbate this problem. Another source of wafer displacement and rotation is the internal stress within the plastic package. Specifically, in the existing chip-first/face-up packaging process, the plastic sealing process includes three stages: heating injection molding, partial solidification of the plastic sealant while maintaining high temperature, and cooling. This is usually followed by a constant-temperature heating step to completely cure the molding compound. There are differences in the thermal expansion coefficients of wafers, plastic packaging materials, plastic films, carrier boards, etc. Therefore, the mismatch of thermal expansion coefficients of various materials during the plastic packaging process and the curing shrinkage of the plastic packaging materials lead to uneven internal stress in the plastic packaging body, further causing chip drift and / Or rotation (as shown in the wafer arrangement in the lower right corner of Figure 1) and warping of the plastic package (a form in which the wafer and carrier are over-molded with plastic material). Wafer drift and/or rotation can cause subsequent mismatch or misalignment of redistribution traces (RDL) traces and under-bump metal (UBM) (as shown in the upper right corner of Figure 2 after wafer drift and rotation). shown), which may result in a significant decrease in yield. The warpage of the plastic package will cause difficulties in the subsequent packaging process (including the formation of RDL and UBM). In severe cases, it may even be impossible to continue the subsequent process.

This application aims to propose a new and breakthrough packaging method that can at least solve the above technical problems.

The packaging method according to the embodiment of the present application utilizes the self-alignment ability of the alignment solder joint (joint) between the semiconductor device and the carrier board when the solder is in a molten or partially molten state to automatically and accurately align the semiconductor device to a target on the carrier board. position and after the solder solidifies, the position of the semiconductor device is fixed, wherein a first alignment welding portion and a corresponding first alignment welding portion are pre-formed on the passive surface of the semiconductor device (that is, the opposite surface of the active surface) and on one side of the carrier board. The second alignment soldering portion (for example, one of them is an aligned soldering bump and the other is an aligned pad; or both are aligned soldering bumps). The packaging method causes the first and second alignment soldering parts to contact each other after placing the semiconductor device at a target position on the carrier board. One (or both) melts to form an alignment solder joint, and if the semiconductor device is not accurately aligned to the target position on the carrier (i.e., the first alignment solder portion and the second alignment solder portion are not aligned) When, the aligned solder joints in a molten or partially molten state (liquid or partially liquid state) will automatically and accurately introduce the semiconductor device to the target position based on the principle of minimum surface energy to minimize the surface energy, and the aligned solder joints will solidify Then keep the semiconductor device firmly fixed in the target position. The first alignment welding part and the second alignment welding part (in terms of including but not limited to volume, geometry, composition, location, distribution, quantity, etc.) are optimally designed to achieve the most accurate, effective, efficient and reliable automatic welding. Alignment capabilities. Since welding is used instead of film adhesion to fix the semiconductor device on the carrier board, it not only improves the warpage problem but also prevents possible drift and rotation problems of the semiconductor device during the molding process through strong welding. It can also align the solder joints. The self-alignment ability allows a certain degree of placement deviation when picking and placing semiconductor devices, which can significantly reduce the requirements for semiconductor device placement accuracy (especially the pick and place or die bonder), and can Significantly improves the speed of semiconductor device pick-up and placement operations, thereby improving process efficiency and reducing process costs.

As used herein, the term "semiconductor device" may refer to a wafer (also interchangeably referred to as a die, die, die, integrated circuit) produced in a fab (fab) that has been diced and A wafer that has not been packaged after testing. This wafer usually only has interconnect pads for external connections. If desired, the semiconductor device may also be a pre-processed (at least partially packaged) wafer, such as interconnect bumps formed on interconnect pads, or the semiconductor device may have additional structures, such as stacked wafers and packaged wafers.

The term "active surface" as used herein generally refers to the circuit-functional side surface of a semiconductor device having interconnect pads thereon (or interconnect bumps formed on interconnect pads), and may be used interchangeably The ground is called the front or functional surface. The active surface of a semiconductor device and the other side surface that does not have circuit functionality (interchangeably called the passive surface or backside) are opposite each other.

The term "connection terminal" as used herein generally refers to an interconnect pad or interconnect bump on an active surface of a semiconductor device.

The term "alignment weld" as used herein generally refers to a structure that can be welded to a corresponding another alignment weld for alignment by welding methods known in the art.

Figure 3 shows a schematic flowchart of a packaging method according to an embodiment of the present application. As shown in Figure 3, the packaging method includes the following steps:

S310: Provide at least one semiconductor device and a carrier board, wherein the semiconductor device respectively has an active surface and a passive surface opposite to each other, the active surface is formed with connection terminals, and the passive surface is formed with a plurality of A first alignment welding portion, and a plurality of second alignment welding portions respectively corresponding to the plurality of first alignment welding portions are formed on the carrier board.

In some embodiments, there are multiple semiconductor devices. As an example, the plurality of semiconductor devices may be at least partially different from each other in function, size or shape, or may be identical to each other. It should be understood that the process can be based on specific process conditions or actual needs (for example, the size and shape of the carrier board and the semiconductor device, the placement spacing or packaging size and shape of the semiconductor device, manufacturing process specifications, functional design of the semiconductor element, etc.) The type and specific number of the semiconductor devices are appropriately selected and are not specifically limited in this application.

In some embodiments, the carrier is a glass carrier, a ceramic carrier, a metal carrier, an organic polymer material carrier, a silicon wafer, or a combination of two or even more of the above carriers.

In some embodiments, any one of the first alignment welding portion and the second alignment welding portion is an alignment welding bump, and the other is an alignment welding bump corresponding to the alignment welding bump. Align pads. In other embodiments, the first alignment welding part and the second alignment welding part are both alignment welding bumps, and their melting points may be the same or different. As an example, the alignment soldering bumps can be pre-fabricated on the semiconductor device (e.g., using bump production processes known in the art (e.g., electroplating, ball planting, template printing, evaporation/sputtering, etc.)). wafer) or carrier board. As an example, the alignment pads may be pre-fabricated on the semiconductor device (eg, wafer) or carrier using a deposition (eg, metal layer)-photolithography-etching process. It should be understood that the first alignment welding part and the second alignment welding part may also adopt any other welding structure or form as long as they can be welded to each other for alignment purposes.

In some embodiments, the first alignment welding portions correspond to the second alignment welding portions in terms of volume, size, geometry, composition, distribution, location, number, etc., so that they can be made by welding to each other. The semiconductor devices are accurately aligned to corresponding target positions on the carrier board.

It should be understood that the first alignment welding can be appropriately selected according to specific process conditions or actual needs (for example, the size and shape of the carrier and the semiconductor device, the placement spacing of the semiconductor device, or the package size and shape, etc.) The specific volume, size, geometry, composition, distribution, location and quantity of the second alignment welding portion and/or the second alignment welding portion are not specifically limited in this application. For example, the first alignment bonding portions may be formed to have substantially the same volume, size, geometry, or composition for all semiconductor devices, regardless of whether the function, size, or shape is the same as each other, and the second alignment bonding portion on the carrier may be The aligned welding portions can all be formed with substantially the same volume, size, geometry or composition to reduce subsequent process complexity and improve packaging efficiency. For another example, for semiconductor devices with different functions, sizes or shapes, the first alignment welding part and the second alignment welding part may be formed into different volumes, sizes, geometries or compositions so that they can be welded later. Different solder joint heights are then formed to achieve specific functions or meet specific requirements. In some embodiments, for a plurality of semiconductor devices, the first alignment bonding portion and/or the second alignment bonding portion are configured such that after subsequent formation of alignment bonding points, the plurality of semiconductor devices have The source surface lies in the same plane parallel to the carrier plate. In some embodiments, for a plurality of semiconductor devices, the first alignment bonding portion and/or the second alignment bonding portion are configured such that after the alignment bonding points are formed in a subsequent process, the plurality of semiconductor devices The passive surfaces lie in the same plane parallel to the carrier plate. For another example, at least three substantially regularly distributed first alignment welding portions may be formed on each of the semiconductor devices, so that the passive surface of the semiconductor device can pass through the first alignment welding portions and all the first alignment welding portions. The welding of the second aligned welding portion is firmly and stably maintained in a plane substantially parallel to the carrier board.

In some embodiments, the connection terminals are interconnect bumps, as shown in Figure 4A. As an example, the interconnection bumps may be pre-fabricated on the semiconductor device (e.g., wafer) using bump manufacturing processes known in the art (e.g., electroplating, ball planting, template printing, evaporation/sputtering, etc.) circle) on the interconnect pads. For example, the interconnection bumps may be in the form of conductive pillars. In an alternative embodiment, the connection terminals are the interconnect pads themselves, as shown in Figure 5A.

S320: Place the at least one semiconductor device on the carrier board so that the plurality of first alignment welding portions and the plurality of second alignment welding portions are substantially aligned.

In some embodiments, the "substantially aligned" includes that the first alignment weld and the second alignment weld are respectively in contact with each other but are not precisely aligned in a direction perpendicular to the passive surface. middle. "Centered" herein generally means that the centers of the first alignment weld and the second alignment weld are aligned in a direction perpendicular to the passive surface. It should be noted that the “basic alignment” of the first alignment welding part and the second alignment welding part means that there is at least a gap between the first alignment welding part and the second alignment welding part. contact to such an extent that self-alignment is possible as described below by means of the minimum surface energy principle of the aligned solder joints in the molten or partially molten state during the welding process, so "substantially aligned" includes not exactly aligned but at least There is a state of physical contact, but the state of precise alignment is not excluded.

It should be understood that when the semiconductor device is placed on the carrier in step S320, the passive surface of the semiconductor device faces the carrier (ie, the surface on which the first alignment soldering portion is formed), and the active surface of the semiconductor device faces away from the carrier. plate.

S330: Form a plurality of alignment welding spots by welding the plurality of first alignment welding parts and the plurality of second alignment welding parts, so that the at least one semiconductor device is accurately aligned and fixed to the Describe the carrier board.

It should be noted that "precise alignment" means a state in which the deviation between the actual position and the target position of the semiconductor device on the carrier board is within the tolerance range of this field. It should be understood that the precise alignment is achieved by utilizing the principle of minimum surface energy that the solder joint formed by welding the first alignment welding part and the second alignment welding part exhibits in a molten or partially molten state during the welding process. Specifically, when the first alignment bonding portion and the second alignment bonding portion contact each other but are not accurately aligned in a direction perpendicular to the passive surface of the semiconductor device or the carrier board, during the bonding process, the first alignment bonding portion One of the alignment welding portion and the second alignment welding portion as the alignment welding bump melts or partially melts and wets the other as the alignment pad or another alignment welding bump, or the first The alignment welding part and the second alignment welding part are both melted or partially melted as alignment welding bumps, thereby forming an alignment welding point in a molten or partially molten state. At this time, based on the principle of minimum surface energy, the alignment welding point is in a molten state. Or the alignment solder joints in the partially molten state will tend to deform and move so that the first alignment soldering portion and the second aligning soldering portion are close to a centered state, thereby driving the semiconductor device that is lighter relative to the carrier board to Accurately align to target location on carrier plate.

It should be understood that after welding the first alignment welding part and the second alignment welding part, due to the height of the alignment welding point itself formed thereby (perpendicular to the passive surface of the semiconductor device or the direction of the carrier), the passive surface of the semiconductor device and the carrier are spaced apart to form a certain space between them.

In some embodiments, the alignment soldering bumps are made of solder, and the soldering can use various molten solder soldering methods known in the art, including but not limited to reflow soldering, laser soldering, high-frequency soldering, Infrared welding, etc.

In some embodiments, after S330, S331 is also included: flipping the semiconductor device and the carrier as a whole so that the active surface of the semiconductor device faces downward, and aligning the semiconductor device again. After the solder joints are melted or partially melted, the temperature is lowered to solidify the aligned solder joints. It should be understood that at this time, the re-melted or partially melted alignment solder joints are moderately elongated due to the weight of the semiconductor device, thereby further improving the self-alignment accuracy. It should be noted that due to the surface energy of the alignment solder joints in the molten or partially molten state, the semiconductor device will not fall off the carrier due to its own weight. As an alternative embodiment, in S310, the plurality of first alignment welding parts and/or the second alignment welding parts are pre-coated with adhesive flux, and S330 includes S330': performing the welding Previously, the semiconductor device and the carrier board were turned over as a whole, so that the active surface of the semiconductor device faced downwards. It should be understood that after flipping over at this time, the alignment solder joints that were melted or partially melted during the welding process are moderately elongated due to the weight of the semiconductor device, thereby further improving the self-alignment accuracy. It should be noted that since the sticky flux adheres the semiconductor device to the carrier board, the semiconductor device will not fall off from the carrier board due to its own weight after being turned over. It should be understood that before S340 described below, the semiconductor device and the carrier board need to be turned over again as a whole.

In some embodiments, when there are multiple semiconductor devices, S330 includes S330'': when the semiconductor device and the carrier are accurately aligned and the alignment solder joints are still in a molten or partially molten state. When using a leveling plate, the active surfaces of the plurality of semiconductor devices are flattened, so that the active surfaces of the plurality of semiconductor devices are substantially located in the same plane parallel to the carrier plate. . As an example, S330'' includes: placing the platen over active surfaces of the plurality of semiconductor devices; pressing the platen toward the carrier such that the active surfaces of the plurality of semiconductor devices substantially in the same plane parallel to the carrier plate; while maintaining the pressing, the temperature is lowered so that the alignment solder joints are substantially solidified; and the pressing plate is removed. As an alternative embodiment, when there are multiple semiconductor devices, S332 is also included after S330: after melting or partially melting the alignment solder joints again, using a pressing plate to conduct The surface is flattened so that the active surfaces of the plurality of semiconductor devices are substantially located in the same plane parallel to the carrier board. As an example, the S332 includes: melting or partially melting the alignment solder joints again; placing the platen above the active surfaces of the plurality of semiconductor devices; pressing the platen toward the carrier board, so that the active surfaces of the plurality of semiconductor devices are substantially located in the same plane parallel to the carrier; while maintaining pressing, cooling is performed to allow the alignment solder joints to substantially solidify; and removing the Press the plate. It can be understood that since the pressing plate is kept pressed until the alignment solder joint is substantially solidified and then the pressing plate is removed, the surface energy of the molten solder joint can be prevented from returning the semiconductor device to its original height before flattening.

This enables the active surfaces of all semiconductor devices to be precisely flush and at the same height. It will be appreciated that appropriate pressure needs to be exerted on the platen so that the alignment pads in a molten or partially molten state are properly deformed and the resulting vertical (relative to the active surface of the semiconductor device or carrier) displacement of the platen is appropriate. , to prevent damage to semiconductor devices. As an example, a solder trap is preformed around the second alignment welding portion of the carrier board, thereby preventing excess molten solder from flowing uncontrollably during the pressing process.

In some embodiments, the above-mentioned flattening process using a pressing plate is combined with the above-mentioned welding process or re-melting process after flipping. As an example, S330'' is executed after S330' is executed in S330, or S332 is executed after S330 including S330' is executed, or S331 is executed after S330 including S330'' is executed, or S332 is executed when S331 is executed.

S340: Form a plastic encapsulation body covering the at least one semiconductor device by performing plastic encapsulation on the side of the carrier board where the semiconductor device is located.

It should be understood that through the molding, not only the active surface and side surfaces of the semiconductor device are covered, but also the space between the passive surface of the semiconductor device and the carrier is filled and covered.

In some embodiments, a molding compound of a resinous material (eg, epoxy resin) is used for molding.

In some embodiments, molding processes such as injection molding, pressure injection, and printing are used for plastic sealing, and optionally combined with an underfill process.

S350: Expose the connection terminal from the plastic package.

In some embodiments, when the connection terminals are interconnection bumps, the interconnection bumps are exposed by thinning (for example, grinding, etching or ablation) the plastic encapsulation body.

In some embodiments, when the connection terminal is an interconnection pad, the interconnection pad is exposed by forming an opening on the plastic package. As an example, laser ablation (eg, laser drilling) may be used to form the opening. As an example, the opening may be formed by mechanical drilling. As an example, before forming the opening, the plastic package may be thinned to meet product design requirements and/or to facilitate the opening.

S360: Sequentially form an interconnection layer and an external terminal on the surface of the plastic package where the connection terminal is exposed, so that the connection terminal is electrically connected to the external terminal through the interconnection layer.

In some embodiments, the interconnection layer includes a redistribution layer (RDL) and an under-bump metal (UBM) in order away from the connection terminal, thereby achieving conductive connection between the connection terminal and the external terminal. . It should be understood that the interconnection layer also includes an insulating layer for achieving electrical insulation between conductive paths, and the specific number and material of the insulating layer can be appropriately selected according to specific process conditions or needs, and this application is not particularly limited. .

In some embodiments, the external terminals are solder balls.

In some embodiments, the external terminals are solder pads.

In some embodiments, after S340, the method further includes: removing the carrier board. As an example, between S340 and S350 or between S350 and S360 or after S360, the carrier board is removed.

In some embodiments, the carrier is removed by processes known in the art such as stripping, etching, ablation, and grinding. As an example, when using a stripping process, the soldering between the carrier board and the semiconductor device (ie, the alignment solder joints) can be desoldered to facilitate peeling off the carrier board from the plastic package. .

In some embodiments, some or all of the alignment solder joints are also removed when or after the carrier board is removed. As an example, some or all of the alignment solder joints may be removed by processes known in the art such as desoldering, etching, ablation, or grinding. In some embodiments, some or all of the alignment pads are retained as part of the final semiconductor component (i.e., the finished package) for electrical connections (eg, power and ground), heat dissipation, mechanical structure, etc.

In some embodiments, after removing the carrier plate, the method further includes: thinning (such as grinding, etching or ablation, etc.) the surface of the plastic package from which the carrier plate has been removed. As an example, the thickness may be thinned to the passive surface of the semiconductor device, or the thinned portion may include a portion of the passive surface side of the semiconductor device. It should be understood that the alignment solder joints remaining after the carrier board is removed are also removed through this thinning process. As a result, the thickness of the final semiconductor element can be further reduced.

In some embodiments, the passive device is packaged together with the at least semiconductor device in substantially the same manner as in the embodiments described above.

In some embodiments, after S360, it further includes: performing cutting.

It should be understood that the dicing process may be performed to produce independent semiconductor components according to the packaging specifications of the semiconductor components (including but not limited to wafer level packaging, wafer level packaging, system level packaging), or the dicing process may not be performed.

Below, the packaging method according to the present application will be described in more detail with reference to exemplary embodiments.

4A to 4G show cross-sectional views for schematically illustrating a packaging method according to an exemplary embodiment of the present application.

As shown in Figure 4A, a plurality of semiconductor devices and a carrier board 420 are provided. Among the plurality of semiconductor devices, at least two semiconductor devices 410 (and/or 410') are different, such as different sizes and/or functions. A plurality of interconnection bumps 412 conductively connected to interconnection pads (not shown) are distributed on the active surface 411 of each semiconductor device 410 (and/or 410'), and on the passive surface 413 A plurality of alignment solder bumps 414 are formed. A plurality of corresponding alignment pads 424 are formed on one surface of the carrier board 420 in the same arrangement (or relative positional relationship) as the alignment soldering bumps 414 on each semiconductor device 410 (and/or 410'). Alternatively, in addition to the semiconductor devices, passive devices may be provided in a similar structure. For example, reference numeral 410' shown in Figure 4 may be replaced with a passive component.

As shown in FIG. 4B , the semiconductor device 410 (and/or 410') is placed on the carrier 420 such that the alignment solder bumps 414 are in contact with the corresponding alignment pads 424. At this time, the alignment solder bump 414 and the alignment pad 424 are not aligned (ie, the vertical centerline L1 of the alignment solder bump 414 and the vertical centerline L2 of the alignment pad 424 do not coincide).

As shown in FIG. 4C , the alignment solder bumps 414 and the alignment pads 424 are soldered (eg, by reflow soldering) to form the alignment solder joints 416 . During the soldering process, the alignment solder bumps 414 in the molten state will wet the alignment pads 424 and perform self-alignment with the alignment pads 424 based on their own minimum surface energy principle (i.e., the alignment solder bumps The vertical centerline L1 of the alignment pad 414 coincides with the vertical centerline L2 of the alignment pad 424 ), so that the semiconductor device 410 (and/or 410 ′) is driven to achieve precise alignment on the carrier board 420 . After the soldering is completed, the passive surface 413 of the semiconductor device 410 (and/or 410') is spaced apart from the carrier 420 to form a space.

As shown in FIG. 4D , plastic packaging is performed on the side of the carrier board 420 on which the semiconductor device 410 (and/or 410′) is soldered. The plastic encapsulation body 430 covers all surfaces of the semiconductor device 410 (and/or 410'), including the active surface 411 (and the interconnection bumps 412), the passive surface 413, and the side surfaces. The space below the passive surface 413 may be underfilled.

As shown in FIG. 4E , the side of the plastic package 430 where the active surface 411 (or the interconnection bumps 412 ) is located is thinned until the interconnection bumps 412 are exposed.

As shown in FIG. 4F , redistribution layer (RDL) traces 442 , UBM 444 , and solder balls 450 are formed in sequence from bottom to top on the surface of the plastic package 430 where the interconnection bumps 412 are exposed, to form the interconnection bumps 412 A conductive path to the corresponding solder ball 450. During this process, particularly when forming RDL traces 442 and/or UBM 444, a dielectric layer 446 is also formed to achieve electrical isolation between conductive paths. Then, the carrier board 420 is removed from the plastic package 430 . When the carrier board 420 is removed, a portion of the alignment pads 416 (including the alignment pads 424) may also be removed at the same time.

As shown in FIG. 4G , the other surface of the plastic package 430 (ie, the side from which the carrier board 420 is removed) is thinned to remove the remaining alignment solder joints 416 and the semiconductor device 410 (and/or 410 ′). A portion of the passive surface 413 side.

It should be understood that before, during or after each step of the above packaging method, other processing (for example, additional processing required for heterogeneous integrated packaging) may be further performed according to actual packaging needs.

Finally, although not shown in the figure, singulation can be performed according to the packaging specifications of the semiconductor component to complete the production of independent semiconductor components.

5A to 5G show cross-sectional views for schematically illustrating a packaging method according to another exemplary embodiment of the present application. It should be noted that the parts that are the same or similar to the previous exemplary embodiment according to FIGS. 4A to 4G will not be described again.

As shown in Figure 5A, a plurality of semiconductor devices and a carrier board 520 are provided. A plurality of interconnection pads 512 are distributed on the active surface 511 of each semiconductor device 510 (and /510'), and a plurality of alignment solder bumps 514 are formed on the passive surface 513. A plurality of corresponding alignment pads 524 are formed on a surface of the carrier board 520 .

As shown in FIG. 5B , the semiconductor device 510 (and/or 510 ′) is placed on the carrier 520 so that the alignment solder bumps 514 are in contact with the corresponding alignment pads 524 . At this time, the alignment solder bumps 514 and the alignment pads 524 are misaligned.

As shown in FIG. 5C , the alignment solder bumps 514 and the alignment pads 520 are soldered to form the alignment solder joints 516 , thereby realizing the semiconductor device 510 (and/or 510 ′) on the carrier board 520 based on the minimum surface energy principle. precise alignment.

As shown in FIG. 5D , when the alignment solder joints 516 are still in a molten state, after placing the pressure plate P on the active surface 511 of the semiconductor device 510 (and/or 510 ′), press (i.e., toward the carrier board 520 ) The plate P is flattened so that the active surfaces of the plurality of semiconductor devices 510 and 510' are in the same plane parallel to the carrier plate 520. Subsequently, the temperature is lowered while maintaining pressing to solidify the alignment solder joints 516, and then the platen P is removed.

As shown in FIG. 5E , plastic packaging is performed on the side of the carrier board 520 on which the semiconductor device 510 (and/or 510′) is soldered. The plastic encapsulation 530 covers all surfaces of the semiconductor device 510 (and/or 510′).

As shown in FIG. 5F , the carrier board 520 is removed from the plastic package 530 . Drilling (eg, laser drilling) is performed on the side of the plastic package 530 where the active surface 511 (or the interconnection pad 512 ) is located, to expose the interconnection pad 512 . Before drilling, the plastic encapsulation body 530 can be thinned as needed.

As shown in FIG. 5G , redistribution layer (RDL) traces 542 , UBM 544 , and solder balls 550 are sequentially formed on the surface of the plastic package 530 with the interconnection pads 512 exposed, so as to form the interconnection pads 512 to the corresponding solder balls. 550 conductive path. During this process, particularly when forming RDL traces 542 and/or UBM 544, a dielectric layer 546 is also formed to achieve electrical isolation between conductive paths.

Finally, although not shown, cutting can be performed according to the functional design specifications of the semiconductor device to complete the production of independent semiconductor devices.

Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the concept and scope of the present application. In this way, if these changes and modifications of this application fall within the scope of the claims of this application and their equivalent technical solutions, the description of this application is also intended to include these changes and modifications.

S310: Provide at least one semiconductor device and a carrier board, wherein the semiconductor device respectively has an active surface and a passive surface opposite to each other, the active surface is formed with connection terminals, and the passive surface is formed with a plurality of a first alignment welding portion, and a plurality of second alignment welding portions respectively corresponding to the plurality of first alignment welding portions are formed on the carrier board S320: Place the at least one semiconductor device on the carrier such that the plurality of first alignment welding portions and the plurality of second alignment welding portions are substantially aligned S330: Form a plurality of alignment welding spots by welding the plurality of first alignment welding parts and the plurality of second alignment welding parts, so that the at least one semiconductor device is accurately aligned and fixed to the carrier board S340: Form a plastic encapsulation body covering the at least one semiconductor device by performing plastic encapsulation on the side of the carrier board where the semiconductor device is located. S350: Exposing the connection terminal from the plastic package S360: Sequentially form an interconnection layer and an external terminal on the surface of the plastic package where the connection terminal is exposed, so that the connection terminal is electrically connected to the external terminal through the interconnection layer. L1: vertical center line L2: vertical center line 410, 410’: Semiconductor devices 411:Active surface 412:Interconnect bumps 413: Passive surface 414:Align soldering bumps 416:Align solder joints 420: Carrier board 424: Align pad 430:Plastic sealing body 442:RDL trace 444:UBM 446:Dielectric layer 450: Solder ball 510, 510’: semiconductor devices 511:Active surface 512:Interconnect pad 513: Passive surface 514:Align soldering bumps 516:Align solder joints 520: Carrier board 524: Align pad 530:Plastic sealing body 542:RDL trace 544:UBM 546:Dielectric layer 550: Solder ball

[Fig. 1] Schematic diagram illustrating wafer drift and wafer rotation phenomena caused by misplacement positioning or mold flow pushing during a chip-first fan-out packaging process according to the prior art. . [Figure 2] A schematic diagram showing a state of mismatch (or misalignment) of under-bump metal (UBM) and redistribution layer (RDL) trace positions formed after wafer drift and rotation as shown in Figure 1 occurs. [Fig. 3] A flowchart showing a packaging method according to an embodiment of the present application. [Figs. 4A to 4G] show cross-sectional views for schematically explaining a packaging method according to an exemplary embodiment of the present application. [Figs. 5A to 5G] Show cross-sectional views for schematically explaining a packaging method according to another exemplary embodiment of the present application.

S310: Provide at least one semiconductor device and a carrier board, wherein the semiconductor device respectively has an active surface and a passive surface opposite to each other, the active surface is formed with connection terminals, and the passive surface is formed with a plurality of a first alignment welding portion, and a plurality of second alignment welding portions respectively corresponding to the plurality of first alignment welding portions are formed on the carrier board

S320: Place the at least one semiconductor device on the carrier such that the plurality of first alignment welding portions and the plurality of second alignment welding portions are substantially aligned

S330: Form a plurality of alignment welding spots by welding the plurality of first alignment welding parts and the plurality of second alignment welding parts, so that the at least one semiconductor device is accurately aligned and fixed to the carrier board

S340: Form a plastic encapsulation body covering the at least one semiconductor device by performing plastic encapsulation on the side of the carrier board where the semiconductor device is located.

S350: Exposing the connection terminal from the plastic package

S360: Sequentially form an interconnection layer and an external terminal on the surface of the plastic package where the connection terminal is exposed, so that the connection terminal is electrically connected to the external terminal through the interconnection layer.

Claims (17)

A semiconductor packaging method, including: S310: providing at least one semiconductor device and a carrier board, wherein the at least one semiconductor device respectively has an active surface and a passive surface opposite to each other, and connection terminals are formed on the active surface, so A plurality of first alignment welding parts are formed on the passive surface, and a plurality of second alignment welding parts respectively corresponding to the plurality of first alignment welding parts are formed on the carrier board; S320: The at least one semiconductor device is placed on the carrier such that the plurality of first alignment welding portions are substantially aligned with the plurality of second alignment welding portions; S330: By aligning the plurality of first alignment welding portions The alignment welding part and the plurality of second alignment welding parts are welded to form a plurality of alignment welding points, so that the at least one semiconductor device is accurately aligned and fixed to the carrier board; S340: by The side of the carrier board where the at least one semiconductor device is located is plastic-sealed to form a plastic packaging body covering the at least one semiconductor device; S350: Expose the connection terminals from the plastic packaging body; and S360: Expose the plastic packaging body An interconnection layer and an external terminal are sequentially formed on the surface of the connection terminal, so that the connection terminal is electrically connected to the external terminal through the interconnection layer; wherein the plurality of first alignment welding portions and the Each of the plurality of second alignment soldering parts has the form of aligned soldering bumps; wherein the semiconductor packaging method further includes removing the carrier board after S340 or after S360. The semiconductor packaging method of claim 1, wherein the alignment soldering bumps are made of solder, and the soldering is performed by molten solder. The semiconductor packaging method of claim 1, wherein substantially aligning the plurality of first alignment welding portions with the plurality of second alignment welding portions includes: causing the plurality of first alignment welding portions The plurality of second alignment welding portions are respectively in contact with each other but are not precisely aligned in a direction perpendicular to the passive surface. The semiconductor packaging method according to claim 2, wherein in the S310, the plurality of first alignment welding parts and/or the second alignment welding parts are pre-coated with adhesive flux. The semiconductor packaging method according to claim 2, wherein when the at least one semiconductor device is multiple, the S330 includes S330″: forming precise alignment between the multiple semiconductor devices and the carrier board but the When the plurality of alignment solder joints are still in a molten or partially molten state, a pressing plate is used to flatten the active surfaces of the plurality of semiconductor devices, so that the active surfaces of the plurality of semiconductor devices are substantially located between The carrier plate is parallel to the same plane until the alignment solder joints are substantially solidified, and then the pressing plate is removed. The semiconductor packaging method according to claim 2, wherein when the at least one semiconductor device is multiple, the semiconductor packaging method further includes S332 after the S330: melting or partially melting the alignment solder joints again Finally, a pressing plate is used to flatten the active surfaces of the plurality of semiconductor devices, so that the active surfaces of the plurality of semiconductor devices are substantially located in the same plane parallel to the carrier board until the The alignment solder joints are substantially solidified, and then the platen is removed. The semiconductor packaging method according to claim 2, wherein solder wells are respectively pre-formed around the plurality of second alignment welding portions of the carrier board. The semiconductor packaging method according to claim 1, further comprising: thinning the surface of the plastic package body from which the carrier board is removed. The semiconductor packaging method according to claim 8, wherein the thinning is performed such that a portion of the side of the at least one semiconductor device where the passive surface is located is removed. The semiconductor packaging method according to claim 1, further comprising: performing cutting after forming the interconnection layer and the external terminal. The semiconductor packaging method according to claim 1, wherein the connection terminals are interconnection bumps, and exposing the connection terminals from the plastic package includes: thinning the plastic package to make the interconnection bumps point exposed. The semiconductor packaging method of claim 1, wherein the connection terminal is an interconnection pad, and exposing the connection terminal from the plastic package includes: forming an opening on the plastic package to expose the interconnection pad. Even the pads are exposed. The semiconductor packaging method according to claim 1, further comprising: when removing the carrier board or after removing the carrier board, also removing at least part of the alignment solder joints. The semiconductor packaging method of claim 1, when the carrier board is removed or after the carrier board is removed, the alignment solder joints are at least partially retained for manufacturing by the semiconductor packaging method. At least one of the electrical connection, heat dissipation and mechanical structure of the semiconductor component. The semiconductor packaging method according to claim 1, wherein the interconnection layer includes a redistribution layer and an under-bump metal layer in order away from the connection terminals. A semiconductor element packaged by the semiconductor packaging method according to any one of claims 1 to 16. An electronic device including the semiconductor element according to claim 16.