TWI793933B - Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly - Google Patents

Abstract

The invention discloses a semiconductor packaging method, a semiconductor assembly and an electronic device, and the semiconductor packaging method comprises the steps: providing at least one semiconductor device and a first carrier plate, and enabling the semiconductor device to respectively have an active surface with a connection terminal and a passive surface with a plurality of first alignment welding parts, forming second alignment welding parts respectively corresponding to the first alignment welding parts on the first carrier plate; placing the semiconductor device on the first carrier plate, so that the first alignment welding part is basically aligned with the second alignment welding part; forming an alignment welding point by welding the first alignment welding part and the second alignment welding part, so that the semiconductor device is accurately aligned and fixed to the first carrier plate; attaching a second carrier plate on the active surface of the semiconductor device and then removing the first carrier plate; performing plastic package on the side, where the semiconductor device is located, of the second carrier plate to form a plastic package body wrapping the semiconductor device; and removing the second carrier plate to enable the plastic package body to expose the connecting terminal.

Description

Semiconductor packaging method, semiconductor element, and electronic device including same

The embodiments of the present application relate to the technical field of semiconductor manufacturing, and in particular, to a semiconductor packaging method, a semiconductor element, and an electronic device including the semiconductor element.

Semiconductor packages and systems have been pursuing dense, small, light, and thin designs, while striving to achieve high integration and multi-functionality in terms of functions. At present, a variety of packaging technologies have been proposed to meet the above technical requirements, such as fan-out (Fan-out) wafer-level packaging, small chip packaging (chiplet), heterogeneous integration (heterogeneous integration), 2.5D/3D (2.5D/3D ) package. These packaging technologies have different advantages and characteristics, but there are some technical challenges. Taking the existing fan-out packaging as an example, it faces many technical problems, such as warpage, die shift, toporgraphy, non-coplanarity between the chip and the plastic package (chip -to-mold non-planarity), package reliability (Reliability), etc. Although the industry continues to make efforts to improve these technical problems by improving equipment, materials, and process links, there is still no economical and effective solution to some technical problems, especially for warpage, wafer drift, and surface coplanarity between different wafers. plan.

In addition, in the manufacturing process of various high-end semiconductor packages and systems, there are also some common technologies, which often involve high-precision placement and fixing of semiconductor devices. This process step is usually carried out by high-precision pick and place (die bonder) equipment, but its placement speed is limited, making the production speed very slow, and the equipment cost is expensive, which has become a major bottleneck for technology development and popularization.

The present application aims to solve the above-mentioned several core technical problems.

The present application aims to propose a new breakthrough semiconductor packaging method, semiconductor element and electronic equipment including the semiconductor element, so as to at least solve the above-mentioned and other technical problems existing in the prior art.

One aspect of the present application provides a semiconductor packaging method, including: providing at least one semiconductor device and a first carrier, wherein the semiconductor devices respectively have an active surface and a passive surface opposite to each other, and the active surface is formed with Connecting terminals, a plurality of first alignment soldering portions are formed on the passive surface, and a plurality of second alignment soldering portions respectively corresponding to the plurality of first alignment soldering portions are formed on the first carrier. soldering portion; placing the at least one semiconductor device on the first carrier such that the plurality of first alignment soldering portions are substantially aligned with the plurality of second alignment soldering portions; Soldering the plurality of first alignment soldering parts and the plurality of second alignment soldering parts to form a plurality of alignment soldering points, so that the at least one semiconductor device is precisely aligned and fixed to the first carrier; After attaching the second carrier on the active surface of the at least one semiconductor device, remove the first carrier; perform plastic encapsulation on the side of the second carrier where the at least one semiconductor device is located to forming a plastic package covering the at least one semiconductor device; and removing the second carrier to expose the connection terminals to the plastic package. .

Another aspect of the present application provides a semiconductor element packaged by the above semiconductor packaging method.

Yet another aspect of the present application provides an electronic device including the above-mentioned semiconductor element.

It should be understood that the above description is only an overview of the present application, so that the technical solutions of the present application can be understood more clearly, so that they can be implemented according to the contents of the description. In order to make the above and other objects, features and advantages of the present application more comprehensible, specific embodiments of the present application are described in detail below.

The following description of this application contains reference to at least one embodiment of the accompanying drawings, wherein like numerals in these drawings indicate the same or similar components. Although the following description is primarily based on specific embodiments, those of ordinary skill in the art should understand that the following description is intended to cover the present application as defined by the appended claims and their equivalents and as supported by the following description and accompanying drawings. Alternatives, modifications, and equivalent technical means or solutions within the concept and scope of the invention. In the following description, some specific details are given in order to provide a sufficient understanding of the present application, such as specific configurations, compositions, and processes. In other instances, well known processes and manufacturing techniques have not been described with specific details in order to avoid unnecessarily obscuring the application. Furthermore, the various embodiments shown in the figures are schematic and not necessarily drawn to scale.

Semiconductor components (also known as semiconductor packages) are the core components of modern electronic devices or products. Semiconductor components can be roughly divided into: discrete semiconductor components, that is, single-chip components, such as single digital logic processors, diodes, and triodes; multi-chip components, such as image sensors (CIS) and image processor (ASIC) modules, central processing unit (CPU) and dynamic memory device (DRAM) stacking; and system-level components, such as radio frequency front-end modules (FEM) in mobile phones, mobile phones and A display module in a smart watch. Usually, system-level components include a wide range of devices. In addition to semiconductor devices, there are also passive components (resistors, capacitors, inductors) and other devices and even components.

The semiconductor components herein may include active and passive devices, including but not limited to bipolar transistors, field effect transistors, integrated circuits and other active devices and chip resistors, capacitors, inductors, integrated passive components ( IPD), microelectromechanical systems (MEMS) and other passive devices. Establish various electrical connections between various active and passive devices to form circuits that enable semiconductor components to perform high-speed calculations and other useful functions.

Currently, semiconductor manufacturing usually consists of two complex manufacturing processes, front-end wafer manufacturing and back-end packaging manufacturing, each of which may involve hundreds of steps. Front-end wafer fabrication involves forming multiple dies on the surface of a wafer. Each die is usually identical and internally contains circuitry formed by electrically connecting active and/or passive cells. Back-end packaging manufacturing involves separating individual chips from finished wafers and packaging them into semiconductor components to provide electrical connections, structural support, and environmental isolation, while facilitating subsequent assembly of electronic products.

An important goal of semiconductor manufacturing is to produce smaller semiconductor devices, packages and components. Smaller products usually have higher integration, consume less power, have higher performance and have smaller area/volume, which is very important for the market performance of the final product. On the one hand, smaller integrated circuits can be made by improving the front-end wafer process, thereby shrinking the chip, increasing density and improving performance. On the other hand, the subsequent packaging process can further reduce the size, increase the density and improve the performance of semiconductor components by improving the packaging design, process and packaging materials.

At present, in the back-end packaging process, a relatively novel and efficient packaging method is fan-out packaging. Fan-out packaging typically uses molding compound to encapsulate single or multiple dies from a diced wafer and redistribution layers (RDL) to bring the interconnect traces from the die's connection pads to the external Solder balls to achieve higher I/O density and flexible integration packaging technology. Fan-out packaging can be mainly divided into chip-first packaging and chip-last packaging. The chip-first package can be divided into active surface-down (face-down) type and active surface-up (face-up) type.

The mainstream process of chip-first/face-down packaging can include the following main steps: picking up the chip from the diced wafer and placing it on the carrier with the adhesive film so that its active surface faces the adhesive film; Molding the side where the die is mounted; removing the carrier (together with the adhesive film) to expose the active surface of the die; forming the interconnection layers (including the RDL layer and UBM )); forming solder balls on the interconnection layer, wherein the interconnection pads or interconnection bumps of the wafer are electrically connected to the solder balls through the interconnection layer; and performing dicing to form individual semiconductor elements.

The chip-first/face-up packaging process can be roughly the same as the chip-first/face-down packaging process. The main difference is that when the chip is picked up and placed on the carrier plate with adhesive film, make its active surface facing away from the adhesive film; thinning the mold compound on the active surface side of the wafer after molding to expose the interconnect bumps on the active surface of the wafer; and removing the carrier after formation of the interconnect layers and solder balls.

Among the technical problems currently faced by fan-out packaging, there is still a lack of efficient and economical methods for high-precision placement and position fixing of chips. Often the higher the accuracy of wafer placement, the higher the equipment cost and the lower the production efficiency, and it is difficult for the accuracy of wafer loading equipment to break through the 0.5 micron limit. In addition, after the chip is placed on the adhesive film, the position is fixed by the adhesive film, but the adhesive film is deformable, and the flow of the molding compound will push the chip during the molding process, resulting in the chip being stuck on the adhesive film. displacement and rotation. This problem is exacerbated by the higher temperatures used in the molding process. Another source of die displacement and rotation is internal stress within the plastic package. Specifically, in the existing chip-first/face-up packaging process, the molding process includes three stages: heating injection molding, partial curing of the molding compound at high temperature, and cooling. This is usually followed by a constant temperature heating step to fully cure the molding compound. There are differences in the thermal expansion coefficients of the chip, molding compound, adhesive film, carrier board, etc., so the mismatch of the thermal expansion coefficients of various materials during the molding process and the curing shrinkage of the molding compound lead to uneven internal stress of the plastic packaging body, which further causes chip drift and / or rotation (as shown in the chip arrangement in the bottom right of Figure 1) and warping of the molded body (the chip and the carrier are overmolded by the molding compound). Wafer drift and/or rotation causes subsequently formed redistribution (RDL) traces and under-bump metallurgy (UBM) position mismatch or misalignment (as shown in the upper right of Figure 2 after wafer drift and rotation shown), which may result in a significant drop in yield. The warping of the plastic package will cause difficulties to the subsequent packaging process (including the formation of RDL and UBM), and even the subsequent process cannot be continued in severe cases.

The present application aims to propose a new and breakthrough packaging method that can at least solve the above-mentioned technical problems.

The packaging method according to the embodiment of the present application makes use of the self-alignment ability of the alignment pad (joint) between the semiconductor device and the first carrier when the solder is molten or partially molten to automatically and accurately align the semiconductor device to the first carrier. The target position on the board and after the solder is solidified, the position of the semiconductor device is fixed, wherein the passive surface of the semiconductor device (that is, the opposite side of the active surface) and the side of the first carrier are pre-formed with first Alignment pads and corresponding second alignment pads (eg, one of which is an alignment bump and the other is an alignment pad; or both are alignment bumps). In the packaging method, after placing the semiconductor device at a target position on the first carrier so that the first alignment pads and the second alignment pads are in contact with each other, the first alignment pads and the second alignment pads One of them (or both) is melted to form an alignment pad. At this time, if the semiconductor device is not accurately aligned to the target position on the first carrier (ie, the first alignment pad and the second alignment pad misalignment), the molten or partially molten state (liquid or partially liquid) alignment solder joints will automatically introduce the semiconductor device to the target position precisely based on the principle of minimum surface energy to minimize the surface energy, and the alignment The solder joints hold the semiconductor device securely in place after curing. The first alignment welds and the second alignment welds (in terms including but not limited to volume, geometry, composition, location, distribution, and quantity) are optimally designed to enable the most accurate, effective, efficient, and reliable self- Alignment ability. Since the semiconductor device is fixed on the first carrier by welding instead of adhesive film bonding, it not only improves the warpage problem, but also prevents the possible drift and rotation of the semiconductor device during the plastic packaging process through a firm welding method, and can also take into account the alignment. The self-alignment ability of solder joints allows a certain degree of placement deviation when picking and placing semiconductor devices, which can significantly reduce the requirements for semiconductor device placement accuracy (especially for pick and place or die bonder), Moreover, the speed of picking and placing operations of semiconductor devices can be significantly improved, thereby improving process efficiency and reducing process cost.

In addition, according to the packaging method of the embodiment of the present application, on the basis of aligning and fixing the semiconductor device on the first carrier board by means of the alignment pad as described above, the second side of the semiconductor device (ie, the active surface) is pasted After the second carrier, the first carrier is removed and the plastic encapsulation process is performed, so that the active surface of the semiconductor device can be independently fixed and hermetically protected by the second carrier when the plastic encapsulation process is performed, so it is different from the existing chip-first/ Compared with the face-up type packaging process, it is not necessary to thin the mold body (such as grinding) or drill holes to expose the interconnection bumps or interconnection pads after performing the molding process, which can not only improve the efficiency of the molding process , and can also avoid accidental damage to the active surface of semiconductor devices caused by processes such as thinning (eg, grinding) or drilling, thereby improving yield.

As used herein, the term "semiconductor device" may refer to a wafer (also interchangeably called a die, die, die, integrated circuit) produced in a wafer factory (fab), that is, after wafer dicing and Chips that have not yet been packaged after testing, usually only have interconnection pads (pads) for external connections. If desired, the semiconductor device may also be a preprocessed (at least partially packaged) wafer, for example with interconnection bumps formed on the interconnection pads, or the semiconductor device may also have additional structures, for example stacked Chips and Packaged Chips.

As used herein, the term "active surface" generally refers to the side surface of a semiconductor device that has a circuit function and has interconnect pads (or interconnect bumps formed on the interconnect pads) thereon, and can also be used interchangeably It is called the front or functional side. An active surface of a semiconductor device and another side surface having no circuit function (which may be interchangeably referred to as a passive surface or a back surface) face each other.

The term "connection terminal" as used herein generally refers to an interconnection pad or an interconnection bump on an active surface of a semiconductor device.

The term "alignment weld" as used herein generally refers to a structure that can be welded to a corresponding other alignment weld for alignment by welding methods known in the art.

Fig. 3 shows a schematic flowchart of a packaging method according to an embodiment of the present application. As shown in Figure 3, the packaging method includes the following steps:

S310: Provide at least one semiconductor device and a first carrier, wherein the semiconductor device respectively has an active surface and a passive surface opposite to each other, a connection terminal is formed on the active surface, and a connection terminal is formed on the passive surface A plurality of first alignment welding parts, and a plurality of second alignment welding parts respectively corresponding to the plurality of first alignment welding parts are formed on the first carrier.

In some embodiments, there are multiple semiconductor devices. As an example, the plurality of semiconductor devices may be at least partially different from each other in function, size or shape, or may be the same as each other. It should be understood that, according to specific process conditions or actual requirements (for example, the size and shape of the first carrier and the semiconductor device, the placement pitch or package size and shape of the semiconductor device, manufacturing process specifications, functional design of the semiconductor element etc.) to appropriately select the type and specific quantity of the semiconductor device, and the present application does not specifically limit this.

In some embodiments, the first carrier is a glass carrier, a ceramic carrier, a metal carrier, an organic polymer material carrier, or a silicon wafer, or a combination of two or more of the above materials.

In some embodiments, any one of the first alignment solder portion and the second alignment solder portion is an alignment solder bump, and the other is an alignment solder bump corresponding to the alignment solder bump. Align the pads. In some other embodiments, the first alignment soldering portion and the second alignment soldering portion are both alignment soldering bumps, and their melting points may be the same or different. As an example, the alignment solder bumps can be prefabricated on semiconductor devices (eg, electroplating, ball planting, template printing, evaporation/sputtering, etc.) wafer) and/or the first carrier. As an example, the alignment pads may be pre-fabricated on the semiconductor device (eg, wafer) and the first carrier using a deposition (eg, metal layer)-photolithography-etching process. It should be understood that, as long as the first alignment welding portion and the second alignment welding portion can be welded to each other for alignment purpose, any other welding structure or form may also be adopted.

In some embodiments, the first alignment welds and the second alignment welds correspond to each other in terms of volume, size, geometry, composition, distribution, location, and number, such that they can be made by welding each other. The semiconductor devices are precisely aligned to corresponding target positions on the first carrier.

It should be understood that the first pair can be appropriately selected according to specific process conditions or actual requirements (for example, the size and shape of the first carrier and the semiconductor device, the placement pitch of the semiconductor device or the size and shape of the package, etc.). The specific volume, size, geometric shape, composition, distribution, position and quantity of the quasi-welding portion and/or the second alignment-welding portion are not particularly limited in this application. For example, for all semiconductor devices, regardless of whether the function, size or shape is the same as each other, the first alignment pads can be formed to substantially the same volume, size, geometry or composition, and the The second alignment soldering portions can all be formed to have substantially the same volume, size, geometric shape or composition, so as to reduce the complexity of subsequent processes and improve packaging efficiency. For another example, for semiconductor devices with different functions, sizes or shapes, the first alignment soldering portion and the second alignment soldering portion can be formed in different volumes, sizes, geometries or compositions, so that they can be soldered in subsequent Finally, different solder joint heights are formed to achieve specific functions or meet specific requirements. In some embodiments, for a plurality of semiconductor devices, the first alignment soldering portion and/or the second alignment soldering portion are configured such that after alignment pads are subsequently formed, the plurality of semiconductor devices have The source surface lies in the same plane parallel to the first carrier.

In some embodiments, the connection terminal is the interconnection pad itself. In an alternative embodiment, the connection terminals are interconnection bumps. As an example, the interconnection bumps can be prefabricated on a semiconductor device (eg, wafer circle) on the interconnect pad. For example, the interconnection bumps may be in the form of conductive pillars.

As an exemplary embodiment, as shown in FIG. 4A , a plurality of semiconductor devices and a first carrier 420 are provided. Among the plurality of semiconductor devices, at least two semiconductor devices 410, 410' are different, e.g. different in size and/or function. Interconnect pads 412 are distributed and formed on the active surface 411 of each semiconductor device 410 (and/or 410′), and a plurality of alignment solder bumps 414 are formed on the passive surface 413 . A plurality of corresponding alignment pads are formed on one surface of the first carrier 420 in the same arrangement (or relative positional relationship) as the alignment soldering bumps 414 on each semiconductor device 410 (and/or 410'). 424. Alternatively, in addition to semiconductor devices, passive devices may also be provided in a similar structure. For example, reference numeral 410' as shown in FIG. 4 may be replaced with a passive device.

S320: Place the at least one semiconductor device on the first carrier, so that the plurality of first alignment soldering portions are substantially aligned with the plurality of second alignment soldering portions.

In some embodiments, the "substantial alignment" includes that the first alignment soldering portion and the second alignment soldering portion are respectively in contact with each other, but are not precisely aligned in a direction perpendicular to the passive surface. middle. "Centering" herein generally means that the centers of the first alignment soldering portion and the second alignment soldering portion are aligned in a direction perpendicular to the passive surface. It should be noted that the "substantial alignment" of the first alignment welding part and the second alignment welding part means that there is at least a gap between the first alignment welding part and the second alignment welding part. so as to be self-aligning as described below by means of the principle of minimum surface energy of aligned pads in a molten or partially molten state during soldering, therefore "substantially aligned" includes not being exactly centered but at least The state of physical contact, but the state of precise alignment may not be excluded.

It should be understood that when the semiconductor device is placed on the first carrier in step S320, the passive surface of the semiconductor device faces the first carrier (that is, the surface on which the first alignment soldering portion is formed), and the active surface of the semiconductor device faces the first carrier. The surface faces away from the first carrier.

As an exemplary embodiment, as shown in FIG. 4B , semiconductor device 410 (and/or 410′) is placed on first carrier 420 such that alignment solder bumps 414 are in contact with corresponding alignment pads 424 . At this time, the alignment soldering bump 414 is not aligned with the alignment pad 424 , that is, the vertical centerline L1 of the alignment soldering bump 414 and the vertical centerline L2 of the alignment pad 424 do not coincide.

S330: Form a plurality of alignment pads by welding the plurality of first alignment soldering portions and the plurality of second alignment soldering portions, so that the at least one semiconductor device is accurately aligned and fixed to the at least one semiconductor device. Describe the first carrier board.

It should be noted that "precise alignment" means that the deviation between the actual position of the semiconductor device on the first carrier and the target position is within the tolerance range in the art. It should be understood that the precise alignment is achieved by utilizing the principle of minimum surface energy present in a molten or partially molten state of the solder joints formed by welding the first alignment soldering portion and the second alignment soldering portion during the soldering process. Specifically, when the first alignment soldering portion and the second alignment soldering portion are in contact with each other but are not precisely centered in a direction perpendicular to the passive surface of the semiconductor device or the first carrier, during the soldering process, the One of the first alignment soldering portion and the second alignment soldering portion as an alignment soldering bump melts or partially melts and infiltrates the other as an alignment pad or another alignment soldering bump, or the Both the first alignment soldering portion and the second alignment soldering portion are melted or partially melted as alignment soldering bumps, thereby forming an alignment soldering point in a melted or partially melted state. At this time, based on the principle of minimum surface energy, Alignment pads in a molten or partially molten state tend to distort and move to bring the first and second alignment solders closer to centered, thereby entraining the lighter relative to the first carrier plate. The semiconductor device is precisely aligned to the target position on the first carrier.

It should be understood that after soldering the first alignment soldering portion and the second alignment soldering portion, due to the height of the alignment solder joint itself (perpendicular to the passive surface of the semiconductor device or the direction of the first carrier), the inactive surface of the semiconductor device is spaced apart from the first carrier to form a certain space therebetween.

In some embodiments, the alignment soldering bumps are made of solder, and the soldering can be performed by various molten soldering methods known in the art, including but not limited to reflow soldering, laser soldering, high frequency soldering, Infrared welding etc. As an example, flux or solder paste can be used for soldering.

As an exemplary embodiment, as shown in FIG. 4C , alignment solder bumps 414 and alignment pads 424 are soldered to form alignment solder joints 416 . During the soldering process, the alignment solder bump 414 in the molten state will wet the alignment pad 424 and self-align with the alignment pad 424 based on its own minimum surface energy principle (that is, the alignment solder bump 414 coincides with the vertical centerline L2 of the alignment pad 424 ), so as to drive the semiconductor device 410 (and/or 410 ′) to achieve precise alignment on the first carrier 420 . After the soldering is completed, the inactive surface 413 of the semiconductor device 410 (and/or 410') is separated from the first carrier 420 to form a space.

In some embodiments, after S330, S331 is further included: turning over the semiconductor device and the first carrier as a whole, so that the active surface of the semiconductor device faces downward, and turning the semiconductor device again After the alignment pads are melted or partially melted, the temperature is lowered to solidify the alignment pads. It should be understood that the re-melted or partially melted alignment pads at this time are moderately elongated due to the weight of the semiconductor device, thereby further improving self-alignment accuracy. It should be noted that due to the surface energy of the alignment solder joints in a molten state or a partially molten state, the semiconductor device will not fall off from the first carrier due to its own weight. As an alternative embodiment, in S310, adhesive flux is pre-coated on the plurality of first alignment soldering parts and/or second alignment soldering parts, and S330 includes S330': performing the soldering Before, the semiconductor device and the first carrier are turned over as a whole, so that the active surface of the semiconductor device faces downward. It should be understood that at this time, after turning over, the alignment pads melted or partially melted during the soldering process are moderately elongated due to the weight of the semiconductor device, thereby further improving the self-alignment accuracy. It should be noted that, since the semiconductor device is bonded to the first carrier by the viscous flux, the semiconductor device will not fall off from the first carrier due to its own weight after being turned over. It should be understood that before S340 described below, it is necessary to turn over the semiconductor device and the first carrier as a whole again.

In some embodiments, when there are multiple semiconductor devices, S330 includes S330'': when the semiconductor device is precisely aligned with the first carrier and the alignment pads are still melted or partially In a molten state, the active surfaces of the plurality of semiconductor devices are flattened by using a leveling plate, so that the active surfaces of the plurality of semiconductor devices are substantially parallel to the first carrier in the same plane. As an example, S330'' includes: placing the pressing plate over the active surfaces of the plurality of semiconductor devices; pressing the pressing plate toward the first carrier, so that the active surfaces of the plurality of semiconductor devices The source surface is located substantially in the same plane parallel to the first carrier plate; while the pressing is maintained, the temperature is lowered to substantially solidify the alignment pads; and the pressing plate is removed. As an alternative embodiment, when there are multiple semiconductor devices, after S330, S332 is further included: after melting or partially melting the alignment pads again, using a pressing plate to activate active parts of the multiple semiconductor devices. The surface is flattened so that the active surfaces of the plurality of semiconductor devices are substantially located in the same plane parallel to the first carrier. As an example, the S332 includes: melting or partially melting the alignment pads again; placing the pressing plate over the active surfaces of the plurality of semiconductor devices; pressing the pressing plate toward the first carrier plate. a flat plate, so that the active surfaces of the plurality of semiconductor devices are substantially located in the same plane parallel to the first carrier; while keeping the pressure, cooling is performed to substantially solidify the alignment pads; and Remove the platen. It can be understood that since the pressing plate is kept pressed until the alignment solder joints are substantially solidified, the surface energy of the molten solder joints can be prevented from restoring the semiconductor device to its original height before being flattened.

As an exemplary embodiment, as shown in FIG. 4D , after the alignment pads 416 are melted or partially melted again by heating, and the pressing plate P is placed on the active surfaces 411 of the plurality of semiconductor devices 410, 410 ′, The plate P is pressed (ie facing the first carrier 420 ) to perform a flattening process, so that the active surfaces of the plurality of semiconductor devices 410 , 410 ′ are in the same plane parallel to the first carrier 420 . Subsequently, the temperature is lowered while the pressing is maintained to solidify the alignment pad 416 , and then the pressing plate P is removed.

As a result, the active surfaces of all semiconductor devices can be precisely flush and at the same height. It should be understood that proper pressure needs to be applied to the platen so that the alignment pads in the molten or partially molten state are properly deformed and the resulting perpendicularity of the platen (relative to the active surface of the semiconductor device or the first carrier) Displacement is appropriate to prevent damage to semiconductor devices. As an example, a solder trap is pre-formed around the second alignment soldering portion of the first carrier, thereby preventing uncontrolled and random flow of excess molten solder during the pressing process.

In some embodiments, the above-mentioned flattening process using a flattening plate is combined with the above-mentioned post-inverting welding process or remelting process. As an example, after performing S330' in S330', perform S330'', or perform S332 after performing S330 including S330', or perform S331 after performing S330 including S330'', or perform S332 when performing S331.

S340: After attaching the second carrier on the active surface of the at least one semiconductor device, remove the first carrier.

It should be understood that the second carrier is mainly used to keep the at least one semiconductor device fixed in place after the first carrier is removed, so as to facilitate subsequent plastic packaging. In some embodiments, an adhesive film is used to attach the second carrier. However, it can be understood that as long as the at least one semiconductor device can be fixed relative to the second carrier, any attachment method can be used for the second carrier, which is not particularly limited in the present application.

In some embodiments, the second carrier is made of glass, ceramics, metal, organic polymer material, or silicon wafer, or a combination of two or more of the above materials.

In some embodiments, the first carrier is removed by stripping, etching, ablation, grinding, etc. known in the art. As an example, when the lift-off process is used, the welding between the first carrier and the semiconductor device (that is, the alignment pad) can be desoldered, so as to facilitate the passive connection of the semiconductor device. Surface peeling the first carrier.

In some embodiments, when removing the first carrier or after removing the first carrier, some or all of the alignment pads are also removed. As examples, some or all of the alignment pads may be removed by processes known in the art such as desoldering, etching, ablation, or grinding. In some embodiments, some or all of the alignment pads are reserved as part of the final semiconductor device (ie, packaged product) for electrical connections (such as power and ground), heat dissipation, mechanical structures, and the like.

As an exemplary embodiment, as shown in FIG. 4E , after attaching the second substrate 430 on the active surface 411 of the semiconductor device 410 (and/or 410 ′), as shown in FIG. 4F , by aligning the solder joints 416 performs desoldering to remove the first carrier 420 and alignment pads 416 from the inactive surface 413 side of the semiconductor device 410 (and/or 410 ′).

S350: Perform plastic encapsulation on the side of the second carrier where the at least one semiconductor device is located to form a plastic encapsulation covering the at least one semiconductor device.

It should be understood that through the plastic encapsulation, the passive surface and side surfaces of the semiconductor device are covered.

In some embodiments, S340 includes: before removing the first carrier, turning over the at least one semiconductor device, the first carrier and the second carrier as a whole. In some embodiments, S350 includes: before performing plastic encapsulation, turning over the at least one semiconductor device and the second carrier as a whole.

In some embodiments, molding compound of resinous material (eg, epoxy resin) is used for molding.

As an exemplary embodiment, as shown in FIG. 4G , the semiconductor device 410 (and/or 410 ′) and the second carrier 430 are turned over as a whole, so that the inactive surface 413 of the semiconductor device 410 (and/or 410 ′) upward and the second carrier 430 is located below the semiconductor device 410 (and/or 410'), and then above the second carrier 430 (ie, the side where the semiconductor device 410 (and/or 410') is attached) Plastic encapsulation is performed so that the plastic encapsulation body 440 covers the passive surface and side surfaces of the semiconductor device 410 (and/or 410 ′).

S360: Remove the second carrier board to expose the connection terminals from the plastic package.

In some embodiments, the second carrier is removed by stripping, etching, ablation, grinding, etc. known in the art.

As an exemplary embodiment, as shown in FIG. 4H , by removing the second carrier 430 , the plastic package 440 exposes the active surface 411 of the semiconductor device 410 (and/or 410'), that is, the interconnection pad 412 .

In some embodiments, after S360, S370 is further included: sequentially forming an interconnect layer and an external terminal on the surface of the plastic package where the connection terminal is exposed, so that the connection terminal is electrically connected to the described external terminals.

In some embodiments, S360 includes: before removing the second carrier, turning over the plastic package covered with at least one semiconductor device and the second carrier as a whole. In some embodiments, S370 includes: before forming the interconnection layer and the external terminal, turning over the plastic package covered with at least one semiconductor device.

In some embodiments, the interconnection layer includes a redistribution layer (RDL) and an under-bump metallization (UBM) sequentially in a direction away from the connection terminal, so as to realize the conductive connection between the connection terminal and the external terminal . It should be understood that the interconnection layer also includes an insulating layer for realizing electrical insulation between conductive paths, and the specific number and material of the insulating layer can be appropriately selected according to specific process conditions or needs, and the present application does not specifically limit this .

In some embodiments, the external terminals are solder balls or pads.

As an exemplary embodiment, as shown in FIG. 4I , the plastic package 440 covered with the semiconductor device 410 (and/or 410 ′) is turned over, so that the exposed active part of the semiconductor device 410 (and/or 410 ′) The surface 413 (that is, the interconnection pad 412 ) faces upward, and then on the surface of the plastic package 440 where the interconnection pad 412 is exposed, redistribution layer (RDL) traces 452 , UBM 454 , and solder balls are sequentially formed from bottom to top. 460 to form a conductive path from the interconnection pad 412 to the corresponding solder ball 460 . During this process, particularly when forming RDL traces 452 and/or UBM 454 , a dielectric layer 456 is also formed to provide electrical isolation between the conductive paths.

In some embodiments, the packaging method further includes: thinning (such as grinding, etching or ablation, etc.) a side of the plastic package covering the passive surface of the at least one semiconductor device. As an example, between S350 and S360 or after S360, further includes: thinning a side of the plastic package that covers the passive surface of the at least one semiconductor device. For example, the thinning may be performed between S360 and S370. For another example, the thinning may be performed after S370. As an example, it may be thinned down to the inactive surface of the semiconductor device, or the thinned portion includes a part of the inactive surface side of the semiconductor device. It should be understood that the remaining alignment solder joints after the first carrier is removed are also removed through the thinning process. Thereby, the thickness of the final semiconductor element can be further reduced.

In some embodiments, the passive components are packaged together with the at least semiconductor device in substantially the same way as the above-described embodiments.

In some embodiments, when there are multiple at least one semiconductor device, after S370, the method further includes: cutting.

It should be understood that the dicing process may be performed according to the packaging specification of the semiconductor component (including but not limited to wafer-level package, wafer-level package, system-in-package) to produce independent semiconductor components, or the dicing process may not be performed.

Apparently, those skilled in the art can make various changes and modifications to the embodiments of the application without departing from the spirit and scope of the application. In this way, if these changes and modifications of this application fall within the scope of the claims of this application and their equivalent technical solutions, the contents of this application are also intended to include these changes and modifications.

S310: Provide at least one semiconductor device and a first carrier, wherein the semiconductor device respectively has an active surface and a passive surface opposite to each other, connecting terminals are formed on the active surface, and a plurality of first alignments are formed on the passive surface Welding parts, and a plurality of second alignment welding parts respectively corresponding to the plurality of first alignment welding parts are formed on the first carrier S320: Place at least one semiconductor device on the first carrier, so that the plurality of first alignment soldering portions are substantially aligned with the plurality of second alignment soldering portions S330: Form a plurality of alignment pads by welding a plurality of first alignment pads and a plurality of second alignment pads, so that at least one semiconductor device is accurately aligned and fixed to the first carrier S340: After attaching the second carrier on the active surface of at least one semiconductor device, remove the first carrier S350: Perform plastic encapsulation on the side where at least one semiconductor device is located on the second carrier to form a plastic encapsulation covering at least one semiconductor device S360: Remove the second carrier board to expose the connection terminals of the plastic package 410, 410': Semiconductor devices 411: active surface 412: Interconnect Pad 413:Passive surface 414: Alignment Solder Bumps 416: Alignment solder joints 420: The first carrier board 424: Align pad 430: Second carrier board 440: plastic package 452:Trace 454:UBM 456:Dielectric layer 460: solder ball L1, L2: vertical centerline P: flat plate

[FIG. 1] A schematic diagram showing the phenomenon of chip drift and chip rotation caused by placement misalignment or mold flow jostling during chip-first fan-out packaging according to the prior art . [FIG. 2] A schematic diagram showing the state of under-bump metallurgy (UBM) and redistribution layer (RDL) trace position mismatch (or misalignment) formed after wafer drift and rotation as shown in FIG. 1 occurs. [ Fig. 3 ] A flowchart showing a packaging method according to an embodiment of the present application. [ FIGS. 4A to 4I ] Show cross-sectional views for schematically explaining a packaging method according to an exemplary embodiment of the present application.

S310: Provide at least one semiconductor device and a first carrier, wherein the semiconductor device respectively has an active surface and a passive surface opposite to each other, connecting terminals are formed on the active surface, and a plurality of first alignments are formed on the passive surface Welding parts, and a plurality of second alignment welding parts respectively corresponding to the plurality of first alignment welding parts are formed on the first carrier

S320: Place at least one semiconductor device on the first carrier, so that the plurality of first alignment soldering portions are substantially aligned with the plurality of second alignment soldering portions

S330: Form a plurality of alignment pads by welding a plurality of first alignment pads and a plurality of second alignment pads, so that at least one semiconductor device is accurately aligned and fixed to the first carrier

S340: After attaching the second carrier on the active surface of at least one semiconductor device, remove the first carrier

S350: Perform plastic encapsulation on the side where at least one semiconductor device is located on the second carrier to form a plastic encapsulation covering at least one semiconductor device

S360: Remove the second carrier board to expose the connection terminals of the plastic package

Claims (16)

A semiconductor packaging method, comprising: S310: providing at least one semiconductor device and a first carrier, wherein the semiconductor devices respectively have an active surface and a passive surface opposite to each other, and connection terminals are formed on the active surface, so A plurality of first alignment welding parts are formed on the passive surface, and a plurality of second alignment welding parts respectively corresponding to the plurality of first alignment welding parts are formed on the first carrier; S320 : placing the at least one semiconductor device on the first carrier so that the plurality of first alignment soldering portions are substantially aligned with the plurality of second alignment soldering portions; S330: by aligning the Soldering the plurality of first alignment soldering parts and the plurality of second alignment soldering parts to form a plurality of alignment soldering points, so that the at least one semiconductor device is precisely aligned and fixed to the first carrier; S340: After attaching the second carrier on the active surface of the at least one semiconductor device, remove the first carrier; S350: place the at least one semiconductor device on the second carrier The side is plastic-encapsulated to form a plastic package covering the at least one semiconductor device; and S360: removing the second carrier board so that the plastic package exposes the connection terminals. The semiconductor packaging method according to claim 1, wherein when the at least one semiconductor device is a plurality of semiconductor devices, the S330 includes: forming precise alignment between the plurality of semiconductor devices and the first carrier but When the plurality of alignment pads are still in a molten or partially molten state, using a pressing plate to flatten the active surfaces of the plurality of semiconductor devices, so that the active surfaces of the plurality of semiconductor devices The surface lies substantially in the same plane parallel to the first carrier until the alignment pads are substantially solidified, and then the press plate is removed. The semiconductor packaging method according to claim 1, wherein when the at least one semiconductor device is a plurality of semiconductor devices, the semiconductor packaging method further includes between the S330 and the S340: again aligning the After the solder joints are melted or partially melted, the active surfaces of the plurality of semiconductor devices are flattened by using a pressing plate, so that the active surfaces of the plurality of semiconductor devices are basically located in the same position as the first carrier. plate parallel to the same plane until the alignment solder joints are substantially solidified, then remove the press plate. The semiconductor packaging method according to claim 1, wherein the S340 includes: before removing the first carrier, using the at least one semiconductor device, the first carrier and the second carrier as Flip the whole. The semiconductor packaging method according to claim 1, wherein said S350 includes: turning over said at least one semiconductor device and said second carrier as a whole before performing plastic packaging. The semiconductor packaging method according to claim 1, wherein the S360 includes: before removing the second carrier, integrating the plastic package covered with at least one semiconductor device and the second carrier to flip. The semiconductor packaging method according to claim 1, further comprising S370 after S360: sequentially forming an interconnection layer and external terminals on the surface of the plastic package where the connection terminals are exposed, so that the connection terminals pass through the The interconnection layer is electrically connected to the external terminal. The semiconductor packaging method according to claim 7, wherein the S370 includes: before forming the interconnection layer and the external terminals, turning over the plastic package covered with at least one semiconductor device. The semiconductor packaging method as claimed in claim 1, wherein any one of the plurality of first alignment soldering portions and the plurality of second alignment soldering portions has a shape of an alignment solder bump, and the other or have alignment pads corresponding to the alignment soldering bumps; or the plurality of first alignment soldering portions and the plurality of second alignment soldering portions each have alignment soldering bumps . The semiconductor packaging method according to claim 9, wherein the alignment solder bumps are made of solder, and the soldering is performed by melting the solder. The semiconductor packaging method according to claim 10, wherein in said S310, adhesive flux is pre-coated on said plurality of first alignment soldering portions and/or second alignment soldering portions, and said S330 includes: before performing the welding, turning over the whole including the at least one semiconductor device and the first carrier, so that the active surface of the at least one semiconductor device faces downward. The semiconductor packaging method according to claim 10, wherein after S330, the semiconductor packaging method further includes: turning over the whole including the at least one semiconductor device and the first carrier, so that the The source surface faces downward, and the plurality of alignment pads are melted or partially melted again and then cooled and solidified. The semiconductor packaging method according to claim 1, further comprising: thinning the side of the plastic package covering the passive surface of the at least one semiconductor device. The semiconductor packaging method according to claim 7, further comprising: performing dicing after forming the interconnection layer and the external terminals. The semiconductor packaging method according to claim 1, further comprising: removing at least part of the alignment pads when removing the first carrier or after removing the first carrier. The semiconductor packaging method according to claim 7, wherein the interconnection layer includes a redistribution layer and an under-bump metal layer in sequence in a direction away from the connection terminal.

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