TWI821899B - Semiconductor packaging method, semiconductor assembly and electronic equipment comprising semiconductor assembly - Google Patents

Abstract

The invention discloses a semiconductor packaging method, a semiconductor assembly and electronic equipment comprising the semiconductor assembly. The semiconductor packaging method comprises the following steps: enabling a first-stage device to be automatically and accurately aligned and fixed to a target position on a carrier plate by utilizing the self-alignment capability of a first-stage alignment welding spot between the first-stage device and the carrier plate; automatically and accurately aligning and fixing the second-stage device to a target position on the first-stage assembly by utilizing the self-alignment capability of a second-stage alignment welding spot between the first-stage assembly and the second-stage device, so that the speed of picking and placing the first-stage device and the second-stage device is remarkably improved, the process efficiency is improved; and the process cost is reduced.

Description

Semiconductor packaging method, semiconductor component and electronic device including same

Embodiments of the present application relate to the field of semiconductor manufacturing technology, and in particular to semiconductor packaging methods, semiconductor components, and electronic equipment including the semiconductor components.

Semiconductor packages and systems have always pursued density, smallness, lightness and thinness in design, while striving to achieve high integration and multi-functionality in terms of functionality. Currently, a variety of packaging technologies are proposed to meet the above technical requirements, such as fan-out wafer-level packaging, chiplet, heterogeneous integration, 2.5D/3D ) package. These packaging technologies have different advantages and characteristics, but there are also some technical challenges. Taking the existing fan-out package as an example, it faces many technical problems, such as warpage, die shift, surface flatness (toporgraphy), and non-coplanarity between the chip and the plastic package (chip). -to-mold non-planarity), packaging reliability (Reliability), etc. Although the industry continues to work hard to improve these technical problems by improving equipment, materials, and processes, there is still no economical and effective solution to some technical problems, especially warpage, wafer drift, and surface coplanarity between different wafers. plan.

In addition, there are some common technologies in the manufacturing process of various high-end semiconductor packaging and systems, which often involve high-precision placement and fixation of semiconductor devices. This process step is usually performed by high-precision pick and place or die bonder equipment, but its placement speed is limited, making the production speed very slow, and the equipment cost is expensive, which has become a major bottleneck in the development and popularization of technology.

This application aims to solve several core technical problems mentioned above.

The purpose of this application is to propose a new breakthrough semiconductor packaging method, a semiconductor component, and an electronic device containing the semiconductor component, so as to at least solve the above and other technical problems existing in the prior art.

One aspect of the present application provides a semiconductor packaging method, including:

S310: Provide at least one first-level device, at least one second-level device and a carrier board, wherein the first-level device has a plurality of first-level interconnection terminals formed on the first-level first surface and is in contact with the first-level device. A plurality of first-level first alignment welding portions are formed on a first-level second surface opposite the first-level first surface, and the at least one second-level device has a plurality of second-level first alignment welding portions formed on the second-level first surface. level interconnection terminals and a plurality of second-level first alignment welding portions, and a plurality of first-level and second pairs respectively corresponding to the plurality of first-level first alignment welding portions are formed on the carrier board Quasi-welding department;

S320: Place the at least one first-level device on the carrier board so that the plurality of first-level first alignment welding portions and the plurality of first-level second alignment welding portions are substantially aligned ;

S330: Form a plurality of first-level alignment welding spots by welding the plurality of first-level first alignment welding parts and the plurality of first-level second alignment welding parts, so that the at least one The first-level device is accurately aligned and fixed to the carrier board;

S340: Perform plastic sealing on the side of the carrier board where the at least one first-level device is located to form a plastic package covering the at least one first-level device;

S350: Expose the plurality of first-level interconnection terminals from the plastic package;

S360: Sequentially form an interconnection layer and a plurality of transfer terminals respectively corresponding to the plurality of second-level interconnection terminals on the side of the plastic package where the first-level interconnection terminals are exposed, so that the At least a portion of the plurality of first-level interconnection terminals are electrically connected to the plurality of transfer terminals respectively through the interconnection layer, and a connection with the plurality of second-level first-level interconnection terminals is also formed on the interconnection layer. The alignment welding portions correspond to a plurality of second-level second alignment welding portions respectively, thereby forming first-level components;

S370: Place the at least one second-level device on the first-level component such that the plurality of second-level first alignment welding portions and the plurality of second-level second alignment welding portions are substantially Alignment;

S380: Form a plurality of second-level alignment welding spots by welding the plurality of second-level first alignment welding parts and the plurality of second-level second alignment welding parts, so that the at least one The second-level device is accurately aligned to the first-level component, and the at least one second-level device and the first-level component are connected to each other in an at least partially molten state of the plurality of second-level alignment solder joints. respectively engaging the plurality of second-level interconnect terminals and the plurality of transfer terminals while pressing the stage elements toward each other to form a plurality of interconnect junctions; and

S390: Release the pressing.

Another aspect of the present application provides a semiconductor packaging method, including:

S410: Provide at least one first-level device, at least one second-level device and a carrier board, wherein the first-level device has a plurality of first-level interconnection bumps formed on the first-level first surface and is in contact with the first-level device. A plurality of first-level first alignment welding portions are formed on the first-level second surface opposite to the first-level first surface, and the at least one second-level device is formed with multiple first-level first surface on the second-level first surface. second-level interconnection bumps and a plurality of second-level first alignment soldering portions, wherein the plurality of second-level interconnection bumps and at least a portion of the first-level interconnection bumps are respectively Correspondingly; a plurality of first-level second alignment welding portions respectively corresponding to the plurality of first-level first alignment welding portions are formed on the carrier board;

S420: Place the at least one first-level device on the carrier board so that the plurality of first-level first alignment welding portions and the plurality of first-level second alignment welding portions are substantially aligned ;

S430: Form a plurality of first-level alignment welding spots by welding the plurality of first-level first alignment welding parts and the plurality of first-level second alignment welding parts, so that the at least one The first-level device is accurately aligned and fixed to the carrier board;

S440: Perform plastic sealing on the side of the carrier board where the at least one first-level device is located to form a plastic package covering the at least one first-level device;

S450: Exposing the plurality of first-level interconnect bumps from the plastic package to form first-level components;

S460: Place the at least one second-level device on the first-level component such that the plurality of second-level first alignment welding portions are aligned with the plurality of second-level first components on the first-level component. Two alignment soldering portions are substantially aligned, wherein the plurality of second-level second alignment soldering portions are preformed on a side of the first-level component that exposes the plurality of first-level interconnection bumps and Corresponding respectively to the plurality of second-level first alignment welding parts;

S470: Form a plurality of second-level alignment welding spots by welding the plurality of second-level first alignment welding parts and the plurality of second-level second alignment welding parts, so that the at least one The second-level device is accurately aligned to the first-level component, and the at least one second-level device and the first-level component are connected to each other in an at least partially molten state of the plurality of second-level alignment solder joints. The plurality of second-level interconnection bumps are respectively engaged with corresponding first-level interconnection bumps while pressing the level elements toward each other to form a plurality of interconnection joints; and

S480: Release the pressing.

Another aspect of the present application provides a semiconductor element, which is packaged by the above-mentioned semiconductor packaging method.

Another aspect of the present application provides an electronic device including the above-mentioned semiconductor element.

It should be understood that the above description is only an overview of the present application, so that the technical solution of the present application can be understood more clearly, so that it can be implemented according to the content of the description. In order to make the above and other objects, features and advantages of the present application more apparent and understandable, specific embodiments of the present application are described in detail below.

This application includes the following description of at least one embodiment with reference to the accompanying drawings, in which like numerals refer to the same or similar components. Although the following description is primarily based on specific embodiments, it will be understood by those of ordinary skill in the art that the following description is intended to cover all aspects of the application that may be included in the application as defined by the appended claims and their equivalents and as supported by the following description and drawings. Substitutions, modifications, and equivalent technical means or solutions within the concept and scope of the invention. In the following description, some specific details, such as specific configurations, compositions, processes, etc., are given in order to provide a full understanding of the present application. In other instances, specific details of well-known processes and manufacturing techniques have not been described in order to avoid unnecessarily obscuring the present application. Furthermore, the various embodiments shown in the drawings are schematic illustrations and not necessarily to scale.

Semiconductor components (also called semiconductor packages) are the core components of modern electronic equipment or products. Semiconductor components can be roughly divided in terms of device quantity and density: discrete semiconductor components, that is, single-chip components, such as a single digital logic processor, diode, and transistor; multi-chip components, such as image sensors (CIS) and image processor (ASIC) modules, central processing unit (CPU) and dynamic memory device (DRAM) stack; and system-level components, such as RF front-end modules (FEM) in mobile phones, mobile phones and Display module in smart watch. Usually, system-level components include a wider range of devices. In addition to semiconductor devices, there are also passive components (resistors, capacitors, inductors) and other devices and even components.

Semiconductor components in this article may include active and passive components, including but not limited to bipolar transistors, field effect transistors, integrated circuits and other active components, and chip resistors, capacitors, inductors, integrated passive components ( IPD), microelectromechanical systems (MEMS) and other passive devices. Various electrical connections are established between various active and passive devices to form circuits that enable semiconductor components to perform high-speed calculations and other useful functions.

Currently, semiconductor manufacturing typically involves two complex manufacturing processes, front-end wafer manufacturing and back-end packaging manufacturing, each of which may involve hundreds of steps. Front-end wafer manufacturing involves forming multiple dies (dies) on the surface of a wafer. Each wafer is typically identical and contains circuitry formed by electrically connecting active and/or passive elements. Back-end packaging manufacturing involves separating individual wafers from completed wafers and packaging them into semiconductor components to provide electrical connections, structural support, and environmental isolation while facilitating subsequent assembly of electronic products.

An important goal of semiconductor manufacturing is to produce smaller semiconductor devices, packages, and components. Smaller products usually have higher integration, consume less power, have higher performance, and have smaller area/volume, which is very important for the market performance of the final product. On the one hand, smaller integrated circuits can be made by improving the front-end wafer process, thereby shrinking the wafer, increasing density and improving performance. On the other hand, the back-end packaging process can further reduce the size, increase density and improve performance of semiconductor components by improving packaging design, processes and packaging materials.

Currently, in the back-end packaging process, a relatively novel and efficient packaging method is fan-out packaging. Fan-out packaging typically uses molding compound to encapsulate single or multiple qualified dies (dies) from diced wafers and lead interconnect traces from the die's connection pads to the outside through a redistribution layer (RDL). Solder balls to achieve higher I/O density and flexible integration packaging technology. Fan-out packaging can be mainly divided into chip-first packaging and chip-last packaging. Chip-first packages can be divided into active surface-down (face-down) and active surface-up (face-up) types.

The mainstream process of chip-first/face-down packaging may include the following main steps: picking up the wafer from the diced wafer and placing it on a carrier plate with an adhesive film so that its active surface faces the adhesive film; applying molding compound Molding the side on which the chip is mounted; removing the carrier (together with the adhesive film) to expose the active surface of the chip; forming interconnect layers (including RDL layers and under-bump metallization (UBM) on the active surface of the chip )); forming solder balls on the interconnect layer, wherein the interconnect pads or interconnect bumps of the wafer are electrically connected to the solder balls through the interconnect layer; and cutting to form independent semiconductor components.

The chip-first/face-up packaging process can be roughly the same as the chip-first/face-down packaging process. The main difference is that when the chip is picked up and placed on the carrier plate with adhesive film, its active surface facing away from the adhesive film; thinning the molding compound on one side of the active surface of the wafer after molding to expose the interconnect bumps on the active surface of the wafer; and the carrier board can be removed after the interconnect layers and solder balls are formed.

Among the technical problems currently faced by fan-out packaging, there is still a lack of efficient and economical methods for high-precision placement and position fixation of chips. Often, the higher the wafer placement accuracy, the higher the equipment cost and the lower the production efficiency. Moreover, it is difficult for the accuracy of wafer loading equipment to exceed the 0.5 micron limit. In addition, after the wafer is placed on the adhesive film, it is bonded and fixed in position by the adhesive film. However, the adhesive film is deformable. During the plastic sealing process, the flow of the plastic sealing material will push the wafer, causing the wafer to move on the adhesive film. Displacement and rotation. The higher temperatures used in the encapsulation process exacerbate this problem. Another source of wafer displacement and rotation is the internal stress within the plastic package. Specifically, in the existing chip-first/face-up packaging process, the plastic sealing process includes three stages: heating injection molding, partial solidification of the plastic sealant while maintaining high temperature, and cooling. This is usually followed by a constant-temperature heating step to completely cure the molding compound. There are differences in the thermal expansion coefficients of wafers, plastic packaging materials, plastic films, carrier boards, etc. Therefore, the mismatch of thermal expansion coefficients of various materials during the plastic packaging process and the curing shrinkage of the plastic packaging materials lead to uneven internal stress in the plastic packaging body, further causing chip drift and / Or rotation (as shown in the wafer arrangement in the lower right corner of Figure 1) and warping of the plastic package (a form in which the wafer and carrier are over-molded with plastic material). Wafer drift and/or rotation can cause subsequent mismatch or misalignment of redistribution traces (RDL) traces and under-bump metal (UBM) (as shown in the upper right corner of Figure 2 after wafer drift and rotation). shown), which may result in a significant decrease in yield. The warpage of the plastic package will cause difficulties in the subsequent packaging process (including the formation of RDL and UBM). In severe cases, it may even be impossible to continue the subsequent process.

In addition, in the back-end packaging process, it may be necessary to further realize the substrate in the Z-axis direction based on the two-dimensional integration of the X-Y plane (for example, a plane parallel to the active surface or passive surface of the chip) according to the specific packaging specifications. (e.g., in a system-in-package), an interposer (e.g., in a 2.5D package), or interconnect integration on another layer of die (e.g., in a 3D package). At this time, similar to the aforementioned fan-out packaging, at least there is a lack of efficient and economical methods for high-precision placement and position fixation of upper-layer devices on lower-layer devices. In addition, as for the interconnection between upper and lower devices in 3D packaging (for example, TSMC's InFO (Integrated Fan-Out), CoWoS (Chip on Wafer on Substrate), SoIC (System Integrated Chip)), as the current mainstream One key technology is hybrid bonding. However, there are also many technical difficulties in hybrid bonding. In addition to common problems such as high cost and low production efficiency, there are also many other problems. For example, it is difficult for chemical mechanical polishing (CMP) to meet the strict requirements for pad recesses, and on wafers. The difference in pad density in different areas affects the depth of the recess, the pad (metal copper) is easily oxidized at high temperatures, and the wafer is easily contaminated in die-to-wafer hybrid bonding.

This application aims to propose a new and breakthrough packaging method that can at least solve the above technical problems.

The packaging method according to the embodiment of the present application utilizes the first-level alignment solder joints ( joint) The self-alignment ability when the solder is at least partially melted to enable the first-level device to automatically and accurately align the target position on the carrier board and achieve a fixed position of the first-level device after the solder solidifies, in which the first-level device A first-level first alignment welding part and a corresponding first-level second alignment welding part are pre-formed on the second surface of the first level (that is, the opposite surface of the first level first surface) and on one side of the carrier board respectively. parts (for example, one of them has a form aligned with solder bumps, the other has a form aligned with pads; or both have forms aligned with solder bumps). The packaging method places the first-level device at a target position on the carrier board so that the first-level first alignment soldering portion and the first-level second alignment soldering portion contact each other. One (or both) of the welding part and the first-level and second-level alignment welding parts are melted to form the first-level alignment welding point. At this time, if the first-level device is not accurately aligned to the target position on the carrier board (That is, the first-level first alignment welding part and the first-level second alignment welding part are not centered), then the first-level alignment welding point is in an at least partially molten state (liquid or partially liquid state) based on the minimum surface energy The principle automatically introduces the first-level device precisely to the target position to minimize surface energy, and the first-level alignment solder joints keep the first-level device firmly fixed at the target position after curing. The first-stage first alignment welding part and the first-stage second alignment welding part (in terms of including but not limited to volume, geometry, composition, location, distribution, quantity, etc.) are optimally designed to achieve the most accurate and effective , efficient and reliable self-alignment capabilities. Since welding is used instead of film adhesion to fix the first-level device on the carrier board, it not only improves the warpage problem but also prevents possible drift and rotation problems of the first-level device during the plastic packaging process through strong welding. It can also take into account the The self-alignment capability of the first-level alignment solder joint allows a certain degree of placement deviation when picking and placing the first-level device, which can significantly reduce the placement accuracy of the first-level device (especially for the chip loader (pick and place or die bonder)), and can significantly increase the speed of first-level device pick-up and placement operations, thereby improving process efficiency and reducing process costs.

Secondly, according to the packaging method of the embodiment of the present application, after the first-level component including the first-level device is processed into a second-level device (interconnect board (for example, substrate (substrate) or interposer)) or semiconductor device ) Z-axis direction interconnection integration also utilizes the self-alignment ability of the second-level alignment solder joints between them when the solder is at least partially melted to enable the second-level device to automatically and accurately align the target on the first-level component position and after the solder solidifies, the position of the second-level device is fixed, wherein the second-level first alignment welding is preformed on the second-level first surface of the second-level device and on the corresponding surface of the first-level component. and a corresponding second-level second alignment solder portion (for example, one of them has the form of an aligned solder bump and the other has the form of a second-level alignment pad; or both have a second-level Align the shape of the solder bumps). Similarly, due to the self-alignment capability of the second-level alignment solder joints, a certain degree of placement deviation can be tolerated when the second-level devices are picked up and stacked on the first-level components, thereby significantly reducing the need for second-level components. Device placement accuracy (especially for pick and place or die bonder) requirements, and can significantly increase the speed of second-level device pick-up and placement operations, thereby further improving process efficiency and reducing process costs. In addition, by replacing the hybrid bonding method, many of the aforementioned technical difficulties in hybrid bonding can be avoided, thereby achieving simple and efficient 3D packaging.

As used herein, the term "semiconductor device" may refer to a wafer (also interchangeably referred to as a die, die, die, integrated circuit) produced in a fab (fab) that has been diced and A wafer that has not been packaged after testing. This wafer usually only has interconnect pads for external connections. If desired, the semiconductor device may also be a pre-processed (at least partially packaged) wafer, such as with interconnect bumps formed on interconnect pads, or the semiconductor device may also have additional structures, such as stacked Wafers or packaged wafers or semiconductor components.

The term "active surface" as used herein generally refers to the circuit-functional side surface of a semiconductor device having interconnect pads thereon (or interconnect bumps formed on interconnect pads), and may be used interchangeably The ground is called the front or functional surface. The active surface of a semiconductor device and the other side surface that does not have circuit functionality (interchangeably called the passive surface or backside) are opposite each other.

The term "interconnect terminal" as used herein generally refers to an interconnect pad or interconnect bump on an active surface of a semiconductor device.

The term "alignment weld" as used herein generally refers to a structure that can be welded to a corresponding another alignment weld for alignment by welding methods known in the art.

FIG. 3 shows a schematic flowchart of a packaging method according to an embodiment of the present application. As shown in Figure 3, the packaging method includes the following steps:

S310: Provide at least one first-level device, at least one second-level device and a carrier board, wherein the first-level device has a plurality of first-level interconnection terminals formed on the first-level first surface and is in contact with the first-level device. A plurality of first-level first alignment welding portions are formed on a first-level second surface opposite the first-level first surface, and the at least one second-level device has a plurality of second-level first alignment welding portions formed on the second-level first surface. level interconnection terminals and a plurality of second-level first alignment welding portions, and a plurality of first-level and second pairs respectively corresponding to the plurality of first-level first alignment welding portions are formed on the carrier board Quasi-welding department.

In some embodiments, there are multiple first-level devices. As an example, the plurality of first-level devices may be at least partially different from each other in function, size or shape, or may be identical to each other. In some embodiments, there are multiple second-level devices. As an example, a plurality of second-level devices may at least partially differ from each other in function, size, or shape, or may be identical to each other. It should be understood that the size or shape of the carrier board, the first-level device and the second-level device, the first-level device and the second-level device can be determined according to specific process conditions or actual needs (for example, the size or shape of the carrier board, the first-level device and the second-level device). placement spacing, package size or shape, manufacturing process specifications, or functional design of the final semiconductor component, etc.) to appropriately select the type and specific number of the first-level devices and the second-level devices, and this application does not make any Specially limited.

In some embodiments, the carrier is a glass carrier, a ceramic carrier, a metal carrier, an organic polymer material carrier or a silicon wafer or is made of a combination of two or even more of the above materials. Optionally, the carrier board has an interconnect structure or product function. As an example, an interconnection board is used as the carrier board, and the interconnection board is a substrate (such as a packaging substrate) or an interposer. For example, the adapter board provides horizontal and/or vertical interconnections. As an example, the first level second alignment solder portion serves as an interconnection terminal of the interconnection board.

In some embodiments, the first-level device is a first-level semiconductor device. When the first-level device is a first-level semiconductor device, the plurality of first-level interconnection terminals are formed on the active surface of the first-level semiconductor device and the first-level interconnection terminals are formed on the passive surface. A plurality of first-level first alignment welds. In other embodiments, the first level device is an interconnect board. As an example, the interconnection board is a substrate (such as a packaging substrate) or an interposer. For example, the adapter board provides horizontal and/or vertical interconnections.

In some embodiments, any one of the first-level first alignment welding portion and the first-level second alignment welding portion has the form of an aligned welding bump, and the other has a shape similar to that of the first-level first alignment welding portion. The shape of the alignment pad corresponding to the alignment soldering bump is described. In other embodiments, the first-level first alignment welding part and the first-level second alignment welding part both have the form of aligned welding bumps, and their melting points may be the same or different. As an example, the alignment solder bumps can be pre-fabricated on the first-level device and the device using bump production processes known in the art (for example, electroplating, ball planting, template printing, evaporation/sputtering, etc.) /or carrier board. As an example, the alignment pads may be pre-fabricated on the first-level device or carrier using a deposition (eg, metal layer)-photolithography-etching process. It should be understood that the first-level first alignment welding portion and the first-level second alignment welding portion can also adopt any other structure or form as long as they can be welded to each other for alignment purposes.

In some embodiments, the first-level first alignment welding portions correspond to the first-level second alignment welding portions in terms of volume, size, geometry, composition, distribution, location, quantity, etc., such that The first-level devices can be accurately aligned to corresponding target positions on the carrier board by soldering to each other.

It should be understood that the selection can be appropriately selected according to specific process conditions or actual needs (for example, the size or shape of the carrier board and the first-level device, the placement spacing of the first-level device, the package size or shape, etc.) The specific volume, size, geometry, composition, distribution, location and quantity of the first-level first alignment welding part and/or the first-level second alignment welding part are not specifically limited in this application. For example, for a plurality of first-level devices, the first-level first alignment bonding portions may be formed to have substantially the same volume, size, geometry, or composition, regardless of whether the function, size, or shape is the same as each other, and the carrier board The first-level and second-level alignment welding portions can be formed with substantially the same volume, size, geometry or composition, so as to reduce subsequent process complexity and improve packaging efficiency. For another example, for multiple first-level devices with different functions, sizes or shapes, the first-level first alignment welding portion and the first-level second alignment welding portion can be formed into different volumes, sizes, Geometry or composition so that different solder joint heights can be formed after subsequent welding to achieve a specific function or meet specific requirements. In some embodiments, for a plurality of first-level devices, the first-level first alignment welding portion and/or the first-level second alignment welding portion are configured such that a first-level alignment is formed during subsequent welding. After the quasi-solder joints are formed, the first-level first surfaces of the plurality of first-level devices can be located in the same plane parallel to the carrier board. For another example, at least three first-level first alignment welding portions that are substantially regularly distributed may be formed on each first-level device, so that the first-level second surface of the first-level device can pass through The welding of the first-level first alignment welding portion and the first-level second alignment welding portion is firmly and stably maintained in a plane substantially parallel to the carrier board. For another example, on each of the first-level devices, the first-level first alignment welding portions can be distributed and formed in an area close to the edge on the first-level second surface so as not to affect subsequent processes and products. Application.

In some embodiments, the first level interconnect terminals have the form of interconnect bumps. As an example, the interconnection bumps can be pre-fabricated on the interconnects of the first-level device using bump production processes known in the art (for example, electroplating, ball planting, template printing, evaporation/sputtering, etc.). Connect to the pad. For example, the interconnection bumps may be in the form of conductive pillars. In an alternative embodiment, the first level interconnect terminals are in the form of interconnect pads. Optionally, the first-level device is also provided with at least one through-electrode for vertical interconnection. For example, for the first level semiconductor device, the through electrode is a through silicon via (TSV). For another example, for the adapter board, the through electrode is a TSV or a through glass via (TGV). For another example, for the substrate, the through electrode is a plated through hole (PTH) or a via hole (via). It can be understood that at this time, the first-level device may also have additional interconnection terminals (for example, the first-level first surface) formed on the first-level second surface opposite to the first-level first surface. The alignment welding portion may also serve as at least a part thereof), and one end of the at least one through-electrode is electrically connected to at least a part of the plurality of first-level interconnection terminals, and the other end of the at least one through-electrode is respectively electrically connected to the additional interconnection terminal.

In some embodiments, the second-level device is a second-level semiconductor device. When the second-level device is a second-level semiconductor device, the plurality of second-level interconnection terminals and the plurality of second-level first-level interconnection terminals are formed on an active surface of the second-level semiconductor device. Align the welding part. In other embodiments, the second level device is an interconnect board. As an example, the interconnection board is a substrate (such as a packaging substrate) or an interposer. For example, the adapter board provides horizontal and/or vertical interconnections.

As an illustrative embodiment, at least one of the at least one first-level device and the at least one second-level device includes at least one semiconductor device.

In some embodiments, the second-level first alignment soldering portion has the form of an aligned soldering bump or an alignment pad. As an example, the alignment solder bumps can be pre-fabricated on the second-level device using bump production processes known in the art (for example, electroplating, ball planting, template printing, evaporation/sputtering, etc.) . As an example, the alignment pads may be pre-fabricated on the second-level device using a deposition (eg, metal layer)-lithography-etch process.

It should be understood that the size or shape of the first-level device and the second-level device, the placement spacing of the first-level device and the second-level device, packaging Size or shape, etc.) The specific volume, size, geometry, composition, distribution, location and quantity of the second-level first alignment welding portion are appropriately selected, and this application does not specifically limit this. For example, for a plurality of second-level devices, regardless of whether the functions, sizes, or shapes are the same as each other, the second-level first alignment bonding portions may be formed to have substantially the same volume, size, geometry, or composition, so as to reduce subsequent process complexity and improve packaging efficiency. For another example, for multiple second-level devices with different functions, sizes, or shapes, the second-level first alignment welding portions can be formed into different volumes, sizes, geometries, or compositions so that they can be formed after subsequent welding. Different solder joint heights to achieve specific functions or meet specific requirements. For another example, at least three second-level first alignment welding portions that are substantially regularly distributed may be formed on each of the second-level devices, so that the second-level first surface of the second-level device can pass through The second-level alignment solder joints formed by welding described later are firmly and stably maintained in a plane substantially parallel to the carrier board. For another example, on each of the second-level devices, the second-level first alignment soldering portions may be distributed and formed on edges sufficiently far away from the second-level interconnection terminals so as not to affect subsequent processes and Product Application.

In some embodiments, the second level interconnect terminals have the form of interconnect bumps. As an example, the interconnection bumps can be pre-fabricated on the interconnects of the second-level device using bump production processes known in the art (for example, electroplating, ball planting, template printing, evaporation/sputtering, etc.). Connect to the pad. For example, the interconnection bumps may be in the form of conductive pillars. In an alternative embodiment, the second level interconnect terminals are in the form of interconnect pads. Optionally, the second-level device is also provided with at least one through-electrode for vertical interconnection. For example, for the second-level semiconductor device, the through electrode is a through silicon via (TSV). For another example, for the adapter board, the through electrode is a TSV or a through glass via (TGV). For another example, for the substrate, the through electrode is a plated through hole (PTH) or a via hole (via). It can be understood that at this time, the second-level device may also have additional interconnection terminals formed on the second-level second surface opposite to the second-level first surface, and one end of the at least one through-electrode They are respectively electrically connected to at least part of the plurality of second-level interconnection terminals, and the other end of the at least one through-electrode is electrically connected to the other interconnection terminals respectively.

As an exemplary embodiment, as shown in FIG. 4A, two first-level semiconductor devices 410, 410', a second-level semiconductor device 450, and a carrier board 420 are provided. The two first level semiconductor devices 410, 410' are not identical, for example in size and/or functionality. It can be understood that, although in FIG. 4A (and FIGS. 4B to 4K described later), for the purpose of convenience of explanation, only the reference numerals of the relevant parts of the left first-level semiconductor device 410 are shown and are described in conjunction with them below, This description also applies to corresponding similar parts of the first-level semiconductor device 410' on the right. Each first-level semiconductor device 410, 410' has a plurality of first-level interconnect bumps 412 distributed on the active surface 411, and a plurality of first-level alignment solder bumps 414 formed on the passive surface 413. . The second-level semiconductor device 450 has a plurality of second-level interconnection bumps 452 and a plurality of second-level alignment solder bumps 454 distributed on the active surface 451 . On one surface of the carrier board 420, a plurality of corresponding first-level ones are formed in the same arrangement (or relative positional relationship) as the first-level alignment soldering bumps 414 on each of the first-level semiconductor devices 410 and 410'. Align pad 424.

S320: Place the at least one first-level device on the carrier board so that the plurality of first-level first alignment welding portions and the plurality of first-level second alignment welding portions are substantially aligned .

In some embodiments, the "substantially aligned" includes that the first level first alignment welding portion and the first level second alignment welding portion are in contact with each other respectively, but are not in contact with each other perpendicular to the first level. The stage is precisely aligned in the direction of the second surface. "Centered" herein generally means that the centers of the first level first alignment welds and the first level second alignment welds are aligned in a direction perpendicular to the first level second surface. It should be noted that the "basic alignment" of the first-level first alignment welding portion and the first-level second alignment welding portion means that there is at least the first-level first alignment welding portion and all the first-level first alignment welding portions. The contact between the first-level and second-level alignment welds is such that self-alignment can be performed as described below by means of the principle of minimum surface energy of the first-level alignment welds that are in an at least partially molten state during the welding process. degree, so "substantially aligned" includes a state that is not precisely aligned but at least has physical contact, but does not exclude a state of precise alignment.

It should be understood that when the first-level device is placed on the carrier board in step S320, the first-level second surface of the first-level device faces the carrier board (ie, the surface on which the first-level first alignment soldering portion is formed) , the first level first surface of the first level device faces away from the carrier board.

As an exemplary embodiment, as shown in FIG. 4B , the first-level semiconductor devices 410 , 410 ′ are placed on the carrier 420 such that the first-level alignment solder bumps 414 are aligned with the corresponding first-level alignment pads 424 contact. At this time, the first-level alignment welding bump 414 and the first-level alignment pad 424 are not aligned, that is, the vertical centerline L1 of the first-level alignment welding bump 414 and the first-level alignment pad 424 are not aligned. The vertical center lines L2 do not coincide.

S330: Form a plurality of first-level alignment welding spots by welding the plurality of first-level first alignment welding parts and the plurality of first-level second alignment welding parts, so that the at least one The first level devices are precisely aligned and fixed to the carrier board.

It should be noted that "precise alignment" means a state in which the deviation between the actual position and the target position of the first-level device on the carrier board is within the tolerance range of the art. It should be understood that the precise alignment is the minimum surface of the solder joint formed by welding the first-level first alignment welding part and the first-level second alignment welding part in an at least partially molten state during the welding process. It can be realized based on the principle. Specifically, when the first-level first alignment solder portion and the first-level second alignment solder portion contact each other but are not accurately aligned in a direction perpendicular to the first-level second surface of the first-level device or the carrier board When, during the welding process, one of the first-level first alignment welding portion and the first-level second alignment welding portion serving as the first-level alignment welding bump is at least partially melted and wetted as the first-level alignment welding bump. The other side of the first-level alignment pad or another first-level alignment solder bump, or the first-level first alignment solder portion and the first-level second alignment solder portion both serve as the first-level alignment solder bump. The quasi-welding bumps are at least partially melted, thereby forming first-level alignment solder joints in an at least partially molten state. At this time, based on the principle of minimum surface energy, the first-level alignment solder joints in an at least partially molten state will tend to The deformation movement brings the first-level first alignment welding part and the first-level second alignment welding part close to a centered state, thereby driving the first-level device, which is lighter relative to the carrier board, to precise alignment. to the target location on the carrier board.

It should be understood that after welding the first-level first alignment welding part and the first-level second alignment welding part, due to the height of the first-level alignment welding point itself (perpendicular to the (in the direction of the first-level second surface of the first-level device or the carrier board), the first-level second surface of the first-level device and the carrier board are spaced apart to form a certain gap between them. space.

In some embodiments, the alignment soldering bumps contain solder, and the soldering can use various molten solder soldering methods known in the art, including but not limited to reflow soldering, laser soldering, high-frequency soldering, and infrared soldering. wait. As an example, soldering can be done using flux or solder paste.

As an exemplary embodiment, as shown in FIG. 4C , the first-level alignment solder bumps 414 and the first-level alignment pads 424 are soldered to form the first-level alignment solder joints 416 . During the soldering process, the first-level alignment solder bumps 414 in the molten state will wet the first-level alignment pads 424 and self-align with the first-level alignment pads 424 based on their own minimum surface energy principle. alignment (that is, the vertical centerline L1 of the first-level alignment soldering bump 414 coincides with the vertical centerline L2 of the first-level alignment pad 424), so that the first-level semiconductor devices 410, 410' are driven to be implemented on the carrier board Precise alignment on the 420. After the soldering is completed, the passive surface 413 of the first-level semiconductor device 410, 410' is spaced apart from the carrier 420 to form a space.

In some embodiments, after S330, S331 is also included: flipping the first-level device and the carrier board as a whole, so that the first-level first surface of the first-level device is downward, And again, the first-level alignment solder joints are at least partially melted and then cooled to solidify the first-level alignment solder joints. It should be understood that the first-level alignment solder joints that are at least partially melted again at this time are moderately elongated due to the weight of the first-level device, thereby further improving the self-alignment accuracy. It should be noted that due to the surface energy of the first-level alignment solder joints in an at least partially molten state, the first-level device will not fall off the carrier board due to its own weight. As an alternative embodiment, in S310, viscous flux is pre-coated on the plurality of first-level first alignment welding parts and/or the first-level second alignment welding parts, and S330 includes S330' : Before performing the welding, the first-level device and the carrier board are turned over as a whole, so that the first-level first surface of the first-level device is downward. It should be understood that after flipping over at this time, the first-level alignment solder joints that were at least partially melted during the welding process are moderately elongated due to the weight of the first-level device, thereby further improving the self-alignment accuracy. It should be noted that since the sticky flux adheres the first-level device to the carrier board, the first-level device will not fall off from the carrier board due to its own weight after flipping over. It should be understood that before S340 described below, the first-level device and the carrier board as a whole can be turned over again as needed.

In some embodiments, when there are multiple first-level devices, S330 includes S330'': forming precise alignment between the first-level device and the carrier board and aligning the first-level solder joints While still in an at least partially molten state, a leveling plate is used to flatten the first surfaces of the plurality of first-level devices, so that the first surfaces of the plurality of first-level devices are The primary first surface lies substantially in the same plane parallel to the carrier plate. As an example, S330'' includes: placing the platen above the first-level first surface of the plurality of first-level devices; pressing the platen toward the carrier board such that the plurality of first-level devices The first-level first surface of the device is substantially located in the same plane parallel to the carrier board; while maintaining the pressure, the temperature is cooled so that the first-level alignment solder joints are substantially solidified; and the first-level alignment solder joints are substantially solidified; and the Press the plate. As an alternative embodiment, when there are multiple first-level devices, S332 is further included after S330: after at least partially melting the first-level alignment solder joints again, using a pressing plate to press the plurality of first-level devices. The first-level first surface of the first-level device is flattened, so that the first-level first surfaces of the plurality of first-level devices are substantially located in the same plane parallel to the carrier board. As an example, S332 includes: at least partially melting the first-level alignment solder joints again; placing the pressing plate above the first-level first surface of the plurality of first-level devices; facing the carrier; The plate presses the pressing plate so that the first-level first surfaces of the plurality of first-level devices are substantially located in the same plane parallel to the carrier plate; while maintaining the pressing, the temperature is lowered to make the The first level alignment solder joints are substantially solidified; and the pressure plate is removed. It can be understood that since the pressing is maintained until the first-level alignment solder joint is substantially solidified and then the pressing plate is removed, it is possible to prevent the surface of the molten solder joint from returning to the original height of the first-level device before flattening.

As an exemplary embodiment, as shown in FIG. 4D , after the first-level alignment solder joints 416 are again in an at least partially molten state by heating, a press is placed on the active surfaces 411 of the first-level semiconductor devices 410 and 410 ′. The flat plate P is pressed (ie, toward the carrier board 420 ) to perform a flattening process, so that the active surfaces of the first-level semiconductor devices 410 , 410 ′ are in the same plane parallel to the carrier board 420 . Subsequently, the temperature is lowered while maintaining pressing to solidify the first-level alignment solder joint 416, and then the pressing plate P is removed.

Therefore, the first-level first surfaces of all first-level devices can be precisely flush and at the same height. It should be understood that appropriate pressure needs to be exerted on the platen so that the first-level alignment solder joints in an at least partially molten state are properly deformed and the resulting verticality of the platen (relative to the first-level first-level device) surface or carrier) is displaced appropriately to prevent damage to the first-level device. As an example, a solder trap is preformed around the first-level second alignment welding portion of the carrier board, thereby preventing excess molten solder from flowing uncontrollably during the pressing process.

In some embodiments, the above-mentioned flattening process using a pressing plate is combined with the above-mentioned welding process or re-melting process after flipping. As an example, S330'' is executed after S330' is executed in S330, or S332 is executed after S330 including S330' is executed, or S331 is executed after S330 including S330'' is executed, or S332 is executed when S331 is executed.

S340: Molding is performed on the side of the carrier board where the at least one first-level device is located to form a plastic encapsulation body covering the at least one first-level device.

It should be understood that through the plastic packaging, not only the first-level first surface (including the first-level interconnection terminals) and side surfaces of the first-level device are covered, but the first-level second surface of the first-level device is also covered. The space between the carrier plate and the carrier plate is also filled with cladding.

In some embodiments, a molding compound of a resinous material (eg, epoxy resin) is used for molding.

In some embodiments, molding processes such as injection molding, pressure injection, and printing are used for plastic sealing, and optionally combined with an underfill process.

As an exemplary embodiment, as shown in FIG. 4E , plastic packaging is performed on the side of the carrier board 420 on which the first-level semiconductor devices 410 and 410' are soldered. Therefore, the plastic encapsulation body 430 covers all surfaces of the first-level semiconductor devices 410 and 410', including the active surface 411 (including the first-level interconnection bumps 412), the passive surface 413, and the side surfaces. Optionally, an underfill process is used in the space between the passive surface 413 of the first-level semiconductor device 410, 410' and the carrier board 420.

S350: Expose the plurality of first-level interconnection terminals from the plastic package.

In some embodiments, when the first-level interconnection terminals have the form of interconnection bumps, the interconnection bumps are exposed by thinning (such as grinding, etching or ablation, etc.) the plastic encapsulation body. . It should be understood that a portion of the top end of the interconnect bump may be removed along with this thinning.

In some embodiments, when the first-level interconnection terminal has the form of an interconnection pad, the interconnection pad is exposed by forming an opening on the plastic encapsulation body. As an example, laser ablation (eg, laser drilling) may be used to form the opening. As an example, the opening may be formed by mechanical drilling. As an example, before forming the opening, the plastic package may be thinned to meet product design requirements and/or to facilitate the opening.

As an exemplary embodiment, as shown in FIG. 4F , the side of the plastic package 430 where the active surface 411 (or the first-level interconnection bumps 412 ) is located is thinned until the first-level interconnection bumps 412 are exposed.

S360: Sequentially form an interconnection layer and a plurality of transfer terminals respectively corresponding to the plurality of second-level interconnection terminals on the side of the plastic package where the first-level interconnection terminals are exposed, so that the At least a portion of the plurality of first-level interconnection terminals are electrically connected to the plurality of transfer terminals respectively through the interconnection layer, and a connection with the plurality of second-level first-level interconnection terminals is also formed on the interconnection layer. The alignment welding parts respectively correspond to a plurality of second-level second alignment welding parts, thereby forming a first-level component.

In some embodiments, the interconnect layer includes a redistribution layer (RDL) to implement a conductive path between the first-level interconnect terminal and the transfer terminal. It should be understood that the interconnection layer also includes an insulating layer for achieving electrical insulation between conductive paths, and the specific number and material of the insulating layer can be appropriately selected according to specific process conditions or needs, and this application does not make a special statement in this regard. limited.

In some embodiments, any one of the second-level first alignment welding portion and the second-level second alignment welding portion has the form of an alignment welding bump, and the other has a shape similar to that of the second-level first alignment welding portion. The shape of the alignment pad corresponding to the alignment soldering bump is described. In other embodiments, the second-level first alignment welding part and the second-level second alignment welding part both have the form of aligned welding bumps, and their melting points may be the same or different. As an example, as the second-level second alignment welding part, the alignment welding bumps may use bump manufacturing processes known in the art (for example, electroplating, ball planting, template printing, evaporation/ sputtering method, etc.). As an example, as the second-level second alignment welding portion, the alignment pad may adopt a deposition (eg, metal layer)-photolithography-etching process. It should be understood that the second-level first alignment welding portion and the second-level second alignment welding portion can also adopt any other structure or form as long as they can be welded to each other for alignment purposes.

In some embodiments, the second-level second alignment welding portions correspond to the second-level first alignment welding portions in terms of volume, size, geometry, composition, distribution, location, quantity, etc., such that The second-level devices can be precisely aligned to corresponding target positions on the first-level components by welding to each other.

It should be understood that the size or shape of the first-level device and the second-level device, the placement spacing of the first-level device and the second-level device, packaging Size or shape, etc.) The specific volume, size, geometry, composition, distribution, location and quantity of the second-level second alignment welding portion are appropriately selected, and this application does not specifically limit this. For example, the second-level second alignment welding portions on the first-level component can all be formed to have substantially the same volume, size, geometry, or composition, so as to reduce subsequent process complexity and improve packaging efficiency. For another example, for multiple second-level devices with different functions, sizes, or shapes, the second-level second alignment welding portions can be formed into different volumes, sizes, geometries, or compositions so that they can be formed after subsequent welding. Different solder joint heights to achieve specific functions or meet specific requirements.

In some embodiments, when the second-level interconnect terminals are in the form of interconnect bumps, the transfer terminals are in the form of interconnect bumps or interconnect pads. In some other embodiments, when the second-level interconnection terminal is in the form of an interconnection pad, the transfer terminal is in the form of an interconnection bump. As an example, when the transfer terminal has the form of interconnection bumps, bump production processes known in the art can be used (for example, electroplating, ball planting, template printing, evaporation/sputtering, etc.) , when the transfer terminal has the form of an interconnection pad, a deposition (for example, metal layer)-photolithography-etching process known in the art can be used, which is not particularly limited in this application.

In some embodiments, the transfer terminals correspond to the second-level interconnection terminals in terms of volume, size, geometry, composition, distribution, location, number, etc., such that when the second-level device is located When the first-level component is accurately aligned to the corresponding target position, the transfer terminal and the second-level interconnection terminal can be accurately aligned for the later-described second-level device and the third-level interconnection terminal. Stacked interconnections between first-level components.

It should be understood that in a direction perpendicular to the second-level first surface of the at least one second-level device (or the interconnection layer of the first-level element), the second-level interconnect terminals and the switch The sum of the heights of the connecting terminals is sufficiently smaller than the sum of the heights of the second-level first alignment welding portion and the second-level second level welding portion, so that the second-level interconnection terminal and the transition The terminals are also spaced apart from each other after the second-level first alignment welding portion and the second-level second alignment welding portion subsequently form second-level alignment welding points to avoid affecting the second-level first pair. subsequent welding of the quasi-welding portion and the second-level second alignment welding portion, and prevents the second-level interconnect terminal and the transfer terminal from connecting between the second-level first alignment welding portion and the The second level second alignment welding portions were damaged by pressing against each other during subsequent welding.

As an exemplary embodiment, as shown in FIG. 4G , the active surface 411 (including the first-level interconnection bump 412 ) of the first-level semiconductor device 410 , 410 ′ is exposed on the side of the plastic package 430 from bottom to top. Redistribution layer (RDL) traces 448 are formed first, and then transfer pads 442 respectively corresponding to the second-level interconnection bumps 452 of the second-level semiconductor device 450 are formed to form the first-level interconnection bumps 412 to A conductive path corresponding to transfer pad 442 . During this process, particularly when forming RDL traces 448 and/or transfer pads 442, a dielectric layer 445 is also formed to provide electrical isolation between conductive paths. In addition, a plurality of second-level alignment pads 444 respectively corresponding to the plurality of second-level alignment soldering bumps 454 are also formed on the dielectric layer 445 . Thus, the first-level semiconductor element 440 is formed.

In some embodiments, external interconnection terminals are further formed on the interconnection layer, such that a portion of the plurality of first-level interconnection terminals and/or the plurality of transfer terminals pass through the interconnection layer. electrically connected to the external interconnection terminals. As an example, the conductive paths between them are also implemented through the aforementioned RDL. It should be understood that at this time, among the plurality of first-level interconnection terminals, the first-level interconnection terminal electrically connected to the transfer terminal and the first-level interconnection terminal electrically connected to the external interconnection terminal They may be independent of each other or may at least partially overlap (i.e., be electrically connected to both the transfer terminal and the external interconnection terminal at the same time). It can be understood that the external interconnect terminals are used to connect the final package (ie, the integrated package including at least the first-level device and the second-level device) to another level device (eg, a semiconductor device, an interconnect board, or a PCB board). of interconnection. Therefore, it can be applied to scenarios where the second-level device does not have a through-electrode (such as TSV, TGV, PTH or via), but it is not excluded from being applied to scenarios where the second-level device has a through-electrode. For example, the external interconnection terminals may be together with the aforementioned additional interconnection terminals formed on the second surface of the second-level device (hereinafter referred to as "first external connection terminals" and "second external connection terminals" for ease of distinction). "Connecting terminal") provides interconnection with another level of device. It should be understood that at this time, the first external connecting terminal needs to be high enough (for example, when the first external connecting terminal adopts the form of a solder ball, the size of the solder ball is larger), so that As described later, after the second-level device is aligned and fixed to the first-level component, the first external connection terminal and the second external connection terminal are basically in the same parallel plane (that is, relative to the first-level component), so as to realize the connection with the other-level device. of interconnection. As an example, the external interconnection terminals are distributed and formed to be sufficiently spaced from the second level second alignment soldering portions so that after the plurality of second level devices are accurately aligned to the first level components, no The vertical projection of the plurality of second-level devices on the interconnection layer is covered so as not to affect the stacking of subsequent second-level devices on the interconnection layer.

As an exemplary embodiment, as shown in FIG. 4G', on the basis of FIG. 4G, the external interconnection terminal 446 is further formed so as to be sufficiently far away from the second-level alignment pad 444, and is formed with part of the first level through the RDL trace. conductive paths for level interconnect bumps 412 .

S370: Place the at least one second-level device on the first-level component such that the plurality of second-level first alignment welding portions and the plurality of second-level second alignment welding portions are substantially Align.

The “basic alignment” here may optionally refer to the aforementioned “basic alignment” between the first-level first alignment welding portion and the first-level second alignment welding portion in S320. explanation, so I won’t go into details here.

It should be understood that when the second-level device is placed on the first-level component in step S370, the second-level first surface of the second-level device faces the first-level component (ie, the second-level second alignment welding is formed) surface).

As an exemplary embodiment, as shown in FIG. 4H , the second-level semiconductor device 450 is placed on the first-level semiconductor element 440 such that the second-level alignment solder bumps 454 are aligned with the corresponding second-level alignment pads 444 contact. At this time, the second-level alignment solder bumps 454 and the second-level alignment pads 444 are misaligned.

S380: Form a plurality of second-level alignment welding spots by welding the plurality of second-level first alignment welding parts and the plurality of second-level second alignment welding parts, so that the at least one The second-level device is accurately aligned to the first-level component, and the at least one second-level device and the first-level component are connected to each other in an at least partially molten state of the plurality of second-level alignment solder joints. The plurality of second-level interconnection terminals and the plurality of transfer terminals are respectively joined to form a plurality of interconnection joints while the stage elements are pressed toward each other.

Here “a plurality of second-level alignment welding spots are formed by welding the plurality of second-level first alignment welding parts and the plurality of second-level second alignment welding parts, so that the "At least one second-level device is precisely aligned with the first-level component" can optionally refer to the foregoing description of S330, so it will not be described again here.

It should be understood that after welding the second-level first alignment welding part and the second-level second alignment welding part, due to the height of the second-level alignment welding point itself (perpendicular to the in the direction of the second-level first surface of the second-level device), the second-level first surface of the second-level device (including the second-level interconnect terminals) and the first-level component are spaced apart to A certain space is formed between them.

In some embodiments, in S380, when the at least one second-level device is accurately aligned with the first-level component and the plurality of second-level alignment solder joints are still in an at least partially molten state , engaging the plurality of second-level interconnect terminals and the transfer terminals respectively while pressing the at least one second-level device and the first-level element toward each other. In other embodiments, in S380, after the at least one second-level device is accurately aligned and fixed to the first-level component, the second-level alignment solder joint is at least partially melted again, and The plurality of second-level interconnect terminals and the transfer terminal are respectively engaged while pressing the at least one second-level device and the first-level element toward each other.

In some embodiments, when the second-level interconnection terminals and/or the transfer terminals have the form of interconnection bumps and contain solder, in S380, the plurality of second-level interconnection terminals and The transfer terminals are soldered to form interconnection solder joints. In some embodiments, when the second-level interconnection terminals and/or the transfer terminals have the form of interconnection bumps and do not contain solder, in S380, the plurality of second-level interconnection terminals are Perform thermal compression bonding (TCB) with the transfer terminal.

As an exemplary embodiment, as shown in FIG. 4I , the second-level alignment solder bumps 454 and the second-level alignment pads 444 are soldered to form the second-level alignment solder joints 456 . During the soldering process, the second-level alignment solder bumps 454 in the molten state will wet the second-level alignment pad 444 and self-align with the second-level alignment pad 444 based on its own minimum surface energy principle. The second-level semiconductor device 450 is driven to achieve precise alignment on the first-level semiconductor element 440 . After the soldering is completed, the active surface 451 of the second-level semiconductor device 450 is spaced apart from the first-level semiconductor element 440 to form a space. Then, as shown in FIG. 4J , the second-level semiconductor device 450 and the first-level semiconductor element 440 are pressed toward each other while being heated. At this time, the second-level alignment pads 456 are again at least partially molten and further flattened, and the second-level interconnect bumps 452 (also in an at least partially molten state) subsequently come into contact with the transfer pads 442 and Second level interconnect pads 458 are formed.

In some embodiments, the method further includes: after the whole body is turned over, the second-level alignment solder joints in an at least partially molten state utilize the weight of the second-level device to further improve the self-alignment accuracy. As an example, reference may be made to the aforementioned S331 or S330'.

S390: Release the pressing.

In some embodiments, after the second-level alignment pads and/or the interconnect joints are at least partially solidified to secure the at least one second-level device to the first-level component, all Describe pressing. It should be understood that the time required for the second level alignment solder joints and/or the interconnection joints to at least partially solidify to secure the at least one second level device to the first level component is based on theory and Predictable by experience or measurable by prior experiments, and with the option of releasing the compression after a certain period of time.

In some embodiments, when the carrier board does not have an interconnect structure or product function, the packaging method further includes: removing the carrier board. As an example, in any one of steps S340 to S390 or between any two steps, the carrier board is removed.

In some embodiments, the carrier is removed by processes known in the art such as stripping, etching, ablation, and grinding. As an example, when using the stripping process, the welding between the carrier board and the first-level device (that is, the first-level alignment solder joint) can be desoldered to facilitate removal of the plastic package from the Peel off the carrier.

In some embodiments, some or all of the first level alignment solder joints are also removed when or after the carrier board is removed. As an example, some or all of the first level alignment solder joints may be removed by processes known in the art such as desoldering, etching, ablation, or grinding. In some embodiments, some or all of the first level alignment pads are retained as part of the final semiconductor component (i.e., the final package) for electrical connections (eg, power and ground), heat dissipation, mechanical structure, etc.

In some embodiments, after removing the carrier plate, the method further includes: thinning (such as grinding, etching or ablation, etc.) the surface of the plastic package from which the carrier plate has been removed. As an example, thinning to remove a part of the plastic package on the first-level second surface side of the first-level device (including a part of the remaining first-level alignment solder joints), or thinning to the first-level The first-level second surface of the first-level device, or the thinned portion, includes a portion on one side of the first-level second surface of the first-level device. It should be understood that the first-level alignment solder joints remaining after the carrier board is removed are also removed through this thinning process. As a result, the thickness of the final semiconductor element can be further reduced.

As an exemplary embodiment, as shown in FIG. 4K , heating is released until the second-level alignment solder joints 456 and the second-level interconnect solder joints 458 are substantially solidified, and then the pressing is released. Then, the carrier 420 (and the first-level alignment pads) is removed by desoldering the first-level alignment pads 416, thereby forming the semiconductor device 400.

It will be appreciated that due to the height of the second level alignment pads and/or the interconnect joints themselves, some space is created between the second level devices and the first level components. In some embodiments, the method further includes: underfilling the space formed between the second-level device and the first-level component.

In some embodiments, the passive device is packaged into a first-level component together with the at least first-level device in substantially the same method as the above-mentioned embodiments.

In some embodiments, after S390, it further includes: performing cutting.

It should be understood that the dicing process may be performed to produce individual semiconductor components according to package specifications, or the dicing process may not be performed.

Based on a similar inventive concept, this application also provides a packaging method according to another embodiment. Compared with the aforementioned packaging method according to the embodiment shown in Figure 3, the main difference is that: the first-level interconnection of the first-level device The connection terminals and at least part of the second-level interconnection terminals of the second-level device adopt the form of interconnection bumps, and fan-out of the first-level interconnection terminals of the first-level device is not performed (that is, no interconnection is formed). layer), interconnection is made between the first-level interconnection terminals of the first-level device and the second-level interconnection terminals of the second-level device. Therefore, in order to avoid unnecessarily confusing the inventive concept, the description of the packaging method according to this embodiment will be omitted in the following description of the parts that are basically the same or have no substantial changes compared to the embodiment shown in FIG. 3, For this, please refer to the corresponding description of the embodiment shown in FIG. 3 .

Figure 5 shows a flow chart of a packaging method according to another embodiment of the present application. As shown in Figure 5, the packaging method includes the following steps:

S410: Provide at least one first-level device, at least one second-level device and a carrier board, wherein the first-level device has a plurality of first-level interconnection bumps formed on the first-level first surface and is in contact with the first-level device. A plurality of first-level first alignment welding portions are formed on the first-level second surface opposite to the first-level first surface, and the at least one second-level device is formed with multiple first-level first surface on the second-level first surface. second-level interconnection bumps and a plurality of second-level first alignment soldering portions, wherein the plurality of second-level interconnection bumps and at least a portion of the first-level interconnection bumps are respectively Correspondingly; a plurality of first-level second alignment welding portions respectively corresponding to the plurality of first-level first alignment welding portions are formed on the carrier board.

It should be understood that in order to connect at least a portion of the plurality of first-level interconnect bumps of the at least one first-level device to the plurality of first-level interconnect bumps of the at least one second-level device without fan-out, interconnections between second-level interconnection bumps, at least a portion of the plurality of first-level interconnection bumps need to be consistent with the said plurality of first-level interconnection bumps in terms of volume, size, geometry, composition, distribution, location, number, etc. The plurality of second-level interconnection bumps correspond to each other such that the plurality of second-level interconnection bumps can be aligned when the at least one second-level device is subsequently accurately aligned to the corresponding target position on the first-level component including the first-level device. At least a portion of the first level interconnect bumps are accurately centered with the plurality of second level interconnect bumps to facilitate stacked interconnection between the at least one second level device and the first level component. Even.

In some embodiments, the plurality of second-level interconnection bumps respectively correspond to the plurality of first-level interconnection bumps. In an alternative embodiment, the plurality of second level interconnect bumps and the plurality of second level first alignment pads together serve as the second level first of the at least one second level device. A plurality of second-level interconnection terminals on the surface respectively correspond to the plurality of first-level interconnection bumps.

As an exemplary embodiment, as shown in FIG. 6A, two first-level semiconductor devices 510, 510', a second-level semiconductor device 550, and a carrier board 520 are provided. The two first level semiconductor devices 510, 510' are not identical, for example in size and/or functionality. It can be understood that although only the reference numerals of relevant parts of the first-level semiconductor device 510 are shown in FIG. 6A for the purpose of convenience of explanation and are described in conjunction with them below, the description is also applicable to the first-level semiconductor device 510 ' corresponding similar parts. Each first-level semiconductor device 510, 510' has a plurality of first-level interconnect bumps 512 distributed on the active surface 511, and a plurality of first-level alignment solder bumps 514 formed on the passive surface 513. . The second-level semiconductor device 550 is formed with a plurality of second-level interconnection bumps 552 and a plurality of second-level first alignment soldering bumps 554 distributed on the active surface 551 , as the first-level interconnection bumps 512 Corresponding second-level interconnection terminals respectively, and the second-level semiconductor device 550 is also provided with TSVs 555 that are electrically connected to the second-level first alignment soldering bumps 554 and part of the second-level interconnection bumps 552 respectively. A plurality of corresponding first-level ones are formed on one surface of the carrier board 520 in the same arrangement (or relative positional relationship) as the first-level alignment soldering bumps 514 on each of the first-level semiconductor devices 510 and 510'. Align pad 524.

S420 to S440: basically the same as the aforementioned S320 to S340 respectively.

S450: Expose the plurality of first-level interconnection bumps from the plastic package to form a first-level component.

As an exemplary embodiment, as shown in FIG. 6B , the side of the plastic package 530 where the first-level interconnection bumps 512 (or the active surface 511 ) are located is thinned until the first-level interconnection bumps 512 are exposed. This forms first level semiconductor element 540.

S460: Place the at least one second-level device on the first-level component such that the plurality of second-level first alignment welding portions are aligned with the plurality of second-level first components on the first-level component. Two alignment soldering portions are substantially aligned, wherein the plurality of second-level second alignment soldering portions are preformed on a side of the first-level component that exposes the plurality of first-level interconnection bumps and Corresponding to the plurality of second-level first alignment welding portions respectively.

In some embodiments, when the plurality of second-level interconnection bumps correspond to the plurality of first-level interconnection bumps respectively, between S450 and S460, the method further includes: The plurality of second-level second alignment soldering portions are formed on the side where the first-level interconnection bumps are exposed. As an alternative embodiment, when the second-level first aligned soldering portion has the form of an aligned soldering bump, in S410 the first-level device is further disposed on the first-level first surface. The plurality of second-level second alignment welding portions in the form of alignment welding bumps are formed.

In some embodiments, when the plurality of second-level interconnect bumps and the plurality of second-level first alignment pads together serve as the second-level first of the at least one second-level device, When there are a plurality of second-level interconnection terminals on the surface respectively corresponding to the plurality of first-level interconnection bumps and the plurality of second-level first alignment soldering portions have the form of aligned soldering bumps , in S460, a portion of the plurality of first-level interconnection bumps respectively corresponding to the plurality of second-level first alignment welding portions is used as the plurality of second-level second alignment welding portions. As an alternative embodiment, when the plurality of second-level interconnect bumps and the plurality of second-level first alignment pads together serve as the second-level first of the at least one second-level device, When there are a plurality of second-level interconnection terminals on the surface respectively corresponding to the plurality of first-level interconnection bumps, between S450 and S460, it also includes: on the plurality of first-level interconnection bumps The plurality of second-level second alignment welding portions having the form of alignment welding bumps are respectively formed on a portion corresponding to the plurality of second-level first alignment welding portions.

It should be understood that in a direction perpendicular to the second-level first surface of the at least one second-level device (or the side surface of the first-level component that exposes the first-level interconnect bump), the The height of the second level interconnection bumps is sufficiently less than the sum of the heights of the second level first alignment soldering portion and the second level second alignment soldering portion such that the first level interconnection bumps and The second level interconnect bumps are also spaced apart from each other after the second level first alignment welds and the second level second alignment welds subsequently form second level alignment welds.

As an exemplary embodiment, as shown in FIG. 6C , second-level semiconductor device 550 is placed on first-level semiconductor element 540 such that second-level alignment solder bumps 554 are with corresponding first-level interconnect bumps 512 (as the second level second alignment weld) are in contact. At this time, the second-level alignment solder bumps 554 are misaligned with the corresponding first-level interconnection bumps 512 .

S470: Form a plurality of second-level alignment welding spots by welding the plurality of second-level first alignment welding parts and the plurality of second-level second alignment welding parts, so that the at least one The second-level device is accurately aligned to the first-level component, and the at least one second-level device and the first-level component are connected to each other in an at least partially molten state of the plurality of second-level alignment solder joints. The plurality of second-level interconnection bumps are respectively engaged with corresponding first-level interconnection bumps while the level elements are pressed toward each other to form a plurality of interconnection joints.

In some embodiments, in S470, when the at least one second-level device is accurately aligned with the first-level component and the plurality of second-level alignment solder joints are still in an at least partially molten state , respectively engaging the plurality of second-level interconnection bumps and the corresponding first-level interconnection bumps while pressing the at least one second-level device and the first-level component toward each other. In other embodiments, in S470, after the at least one second-level device is accurately aligned and fixed to the first-level component, the second-level alignment solder joint is at least partially melted again, and The plurality of second-level interconnect bumps and corresponding first-level interconnect bumps are respectively engaged while pressing the at least one second-level device and the first-level component toward each other.

In some embodiments, the second-level interconnection bumps and/or the first-level interconnection bumps contain solder, and in S470, the plurality of second-level interconnection bumps and the corresponding first-level interconnection bumps are The first-level interconnection bumps are soldered separately to form interconnection solder joints. In some embodiments, the second-level interconnect bumps and/or the first-level interconnect bumps do not include solder, and in S470, the plurality of second-level interconnect bumps and corresponding The first level interconnect bumps are thermally bonded.

As an exemplary embodiment, as shown in FIG. 6D , second-level alignment solder bumps 554 and corresponding first-level interconnect bumps 512 are soldered to form second-level alignment solder bumps 556 . During the soldering process, the second-level alignment soldering bumps 554 in the molten state will wet the corresponding first-level interconnection bumps 512 and interact with the corresponding first-level interconnection bumps based on their own minimum surface energy principle. 512 performs self-alignment to drive the second-level semiconductor device 550 to achieve precise alignment on the first-level semiconductor element 540 . After the soldering is completed, the active surface 551 of the second-level semiconductor device 550 is spaced apart from the first-level semiconductor element 540 to form a space. Then, as shown in FIG. 6E , the second-level semiconductor device 550 and the first-level semiconductor element 540 are pressed toward each other while being heated. At this time, the second-level alignment solder joints 556 are again at least partially melted and further flattened, and the second-level interconnection bumps 552 (also in an at least partially molten state) are subsequently connected to the first-level interconnection bumps 512 Contact is made and a second level interconnect pad 558 is formed.

S480: Basically the same as the aforementioned S390.

Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the concept and scope of the present application. In this way, if these changes and modifications of this application fall within the scope of the claims of this application and their equivalent technical solutions, the description of this application is also intended to include these changes and modifications.

S310: Provide at least one first-level device, at least one second-level device and a carrier board, wherein the first-level device has a plurality of first-level interconnection terminals formed on the first-level first surface and is connected to the first-level first surface. A plurality of first-level first alignment welding portions are formed on an opposite first-level second surface, and at least one second-level device is formed with a plurality of second-level interconnection terminals and a plurality of second-level interconnection terminals on the second-level first surface. a second-level first alignment welding portion, and a plurality of first-level second alignment welding portions respectively corresponding to the plurality of first-level first alignment welding portions are formed on the carrier board S320: Place at least one first-level device on the carrier board so that the plurality of first-level first alignment welding portions and the plurality of first-level second alignment welding portions are substantially aligned S330: Form a plurality of first-level alignment solder joints by welding a plurality of first-level first alignment welding portions and a plurality of first-level second alignment welding portions, so that at least one first-level device is accurately aligned. Align and secure to carrier plate S340: Plastic sealing is performed on the side of the carrier board where at least one first-level device is located to form a plastic package covering at least one first-level device. S350: Exposing multiple first-level interconnect terminals from the plastic package S360: Sequentially forming an interconnection layer and a plurality of transfer terminals respectively corresponding to the plurality of second-level interconnection terminals on the side of the plastic package where the first-level interconnection terminals are exposed, so that the plurality of first-level interconnection terminals are At least part of them are electrically connected to the plurality of transfer terminals through the interconnection layer, and a plurality of second-level second-level second-level second-level second-level second-level second-level second-level second-level second-level second-level second-level second-level second-level alignment welding pads are also formed on the interconnection layer. Align the solder joints to form the first level components S370: Place at least one second-level device on the first-level component so that the plurality of second-level first alignment welding parts are substantially aligned with the plurality of second-level second alignment welding parts. S380: Form a plurality of second-level alignment solder joints by soldering a plurality of second-level first alignment solder parts and a plurality of second-level second alignment solder joints, so that at least one second-level device is accurately aligned. to the first-level component, and in a state where the plurality of second-level alignment solder joints are at least partially molten, pressing the at least one second-level component and the first-level component toward each other while simultaneously pressing the plurality of second-level alignment solder joints toward each other. Connecting terminals and multiple transfer terminals are individually joined to form multiple interconnection joints S390: Release pressing S410: Provide at least one first-level device, at least one second-level device and a carrier board, wherein the first-level device has a plurality of first-level interconnection bumps formed on the first level first surface and is in contact with the first-level device. A plurality of first-level first alignment soldering portions are formed on the first-level second surface opposite the first surface, and at least one second-level device is formed with a plurality of second-level interconnections on the second-level first surface. bumps and a plurality of second-level first alignment welding portions, wherein the plurality of second-level interconnection bumps respectively correspond to at least a portion of the plurality of first-level interconnection bumps; and a plurality of second-level interconnection bumps are formed on the carrier board. A plurality of first-level second alignment welding parts respectively corresponding to the first-level first alignment welding parts S420: Place at least one first-level device on the carrier board so that the plurality of first-level first alignment welding portions and the plurality of first-level second alignment welding portions are substantially aligned S430: Form a plurality of first-level alignment solder joints by welding a plurality of first-level first alignment welding parts and a plurality of first-level second alignment welding parts, so that at least one first-level device is accurately aligned. Align and secure to carrier plate S440: Plastic sealing is performed on the side of the carrier board where at least one first-level device is located to form a plastic package covering at least one first-level device. S450: Exposing multiple first-level interconnection bumps from the plastic package to form first-level components S460: Place at least one second-level device on the first-level component, so that the plurality of second-level first alignment welding portions are substantially the same as the plurality of second-level second alignment welding portions on the first-level component. Alignment, wherein a plurality of second-level second alignment soldering portions are preformed on a side of the first-level component that exposes the plurality of first-level interconnect bumps and is aligned with the plurality of second-level first aligning soldering portions Don't correspond S470: Form a plurality of second-level alignment solder joints by soldering a plurality of second-level first alignment solder parts and a plurality of second-level second alignment solder joints, so that at least one second-level device is accurately aligned. to the first-level component, and with the plurality of second-level alignment solder joints in an at least partially molten state, pressing the at least one second-level component and the first-level component toward each other while simultaneously pressing the plurality of second-level alignment solder joints toward each other. The connecting bumps are respectively joined to the corresponding first-level interconnection bumps to form multiple interconnection joints. S480: Release pressing 400:Semiconductor components 410, 410’: first-level semiconductor device 411:Active surface 412: First level interconnect bumps 413: Invalid surface 414: First level alignment soldering bumps 416: First level alignment solder joint 420: Carrier board 424: Align pad 430:Plastic sealing body 440: First level semiconductor components 442: transfer pad 444: Second level alignment pad 445:Dielectric layer 448: Trace 450: Second level semiconductor devices 451:Active surface 452: Second level interconnect bumps 454: Second level alignment soldering bumps 456: Second level alignment solder joint 458: Second level interconnection solder joints 510, 510’: first-level semiconductor device 511:Active surface 512: First level interconnect bumps 513: Passive surface 514: First level alignment soldering bumps 520: Carrier board 524: First level alignment pad 530:Plastic sealing body 540: First level semiconductor components 550: Second level semiconductor devices 551:Active surface 552: Second level interconnect bumps 554: Second level first aligned soldering bumps 555:TSV 556: Second level alignment solder joint 558: Second level interconnection solder joints L1, L2: vertical center line P:Plate

[Fig. 1] Schematic diagram illustrating wafer drift and wafer rotation phenomena caused by misplacement positioning or mold flow pushing during a chip-first fan-out packaging process according to the prior art. . [Figure 2] A schematic diagram showing a state of mismatch (or misalignment) of under-bump metal (UBM) and redistribution layer (RDL) trace positions formed after wafer drift and rotation as shown in Figure 1 occurs. [Fig. 3] A flowchart showing a packaging method according to an embodiment of the present application. [ FIGS. 4A to 4K ] show cross-sectional views for schematically explaining the packaging method according to the exemplary embodiment of the present application. [Fig. 5] A flowchart showing a packaging method according to another embodiment of the present application. [ FIGS. 6A to 6E ] illustrate cross-sectional views for schematically explaining a packaging method according to an exemplary embodiment of the present application.

S310: Provide at least one first-level device, at least one second-level device and a carrier board, wherein the first-level device has a plurality of first-level interconnection terminals formed on the first-level first surface and is connected to the first-level first surface. A plurality of first-level first alignment welding portions are formed on an opposite first-level second surface, and at least one second-level device is formed with a plurality of second-level interconnection terminals and a plurality of second-level interconnection terminals on the second-level first surface. a second-level first alignment welding portion, and a plurality of first-level second alignment welding portions respectively corresponding to the plurality of first-level first alignment welding portions are formed on the carrier board

S320: Place at least one first-level device on the carrier board so that the plurality of first-level first alignment welding portions and the plurality of first-level second alignment welding portions are substantially aligned

S330: Form a plurality of first-level alignment solder joints by welding a plurality of first-level first alignment welding portions and a plurality of first-level second alignment welding portions, so that at least one first-level device is accurately aligned. Align and secure to carrier plate

S340: Plastic sealing is performed on the side of the carrier board where at least one first-level device is located to form a plastic package covering at least one first-level device.

S350: Exposing multiple first-level interconnect terminals from the plastic package

S360: Sequentially forming an interconnection layer and a plurality of transfer terminals respectively corresponding to the plurality of second-level interconnection terminals on the side of the plastic package where the first-level interconnection terminals are exposed, so that the plurality of first-level interconnection terminals are At least part of them are electrically connected to the plurality of transfer terminals through the interconnection layer, and a plurality of second-level second-level second-level second-level second-level second-level second-level second-level second-level second-level second-level second-level second-level second-level alignment welding pads are also formed on the interconnection layer. Align the solder joints to form the first level components

S370: Place at least one second-level device on the first-level component so that the plurality of second-level first alignment welding parts are substantially aligned with the plurality of second-level second alignment welding parts.

S380: Form a plurality of second-level alignment solder joints by soldering a plurality of second-level first alignment solder parts and a plurality of second-level second alignment solder joints, so that at least one second-level device is accurately aligned. to the first-level component, and in a state where the plurality of second-level alignment solder joints are at least partially molten, pressing the at least one second-level component and the first-level component toward each other while simultaneously pressing the plurality of second-level alignment solder joints toward each other. Connecting terminals and multiple transfer terminals are individually joined to form multiple interconnection joints

S390: Release pressing

Claims (18)

A semiconductor packaging method, including: S410: providing at least one first-level device, at least one second-level device and a carrier board, wherein the first-level device has a plurality of first-level interconnects formed on the first-level first surface. The bumps are connected and a plurality of first-level first alignment welding portions are formed on the first-level second surface opposite to the first-level first surface, and the at least one second-level device is on the second-level A plurality of second-level interconnection bumps and a plurality of second-level first alignment soldering portions are formed on the first surface, wherein the plurality of second-level interconnection bumps are connected to the plurality of first-level interconnections. At least part of the bumps respectively correspond to each other; a plurality of first-level second alignment welding portions respectively corresponding to the plurality of first-level first alignment welding portions are formed on the carrier board; S420: Convert the first-level first alignment welding portions to At least one first-level device is placed on the carrier board, so that the plurality of first-level first alignment welding parts are substantially aligned with the plurality of first-level second alignment welding parts; S430: By aligning The plurality of first-level first alignment welding parts and the plurality of first-level second alignment welding parts are welded to form a plurality of first-level alignment welding spots, so that the at least one first-level device Precisely align and fix it to the carrier board; S440: Perform plastic sealing on the side of the carrier board where the at least one first-level device is located to form a plastic package covering the at least one first-level device; S450: Apply The plurality of first-level interconnection bumps are exposed from the plastic package, thereby forming a first-level component; S460: Place the at least one second-level device on the first-level component, so that the plurality of first-level interconnection bumps are A second-level first alignment welding portion is substantially aligned with a plurality of second-level second alignment welding portions on the first-level component, wherein the plurality of second-level second alignment welding portions are preformed On a side of the first-level component that exposes the plurality of first-level interconnection bumps and respectively corresponds to the plurality of second-level first alignment soldering portions; S470: Form a plurality of second-level alignment welding spots by welding the plurality of second-level first alignment welding parts and the plurality of second-level second alignment welding parts, so that the at least one The second-level device is accurately aligned to the first-level component, and the at least one second-level device and the first-level component are connected to each other in an at least partially molten state of the plurality of second-level alignment solder joints. While pressing the level components toward each other, the plurality of second-level interconnection bumps are respectively joined to the corresponding first-level interconnection bumps to form a plurality of interconnection joints; and S480: release the pressing. The semiconductor packaging method of claim 1, wherein any one of the plurality of first-level first alignment soldering portions and the plurality of first-level second aligning soldering portions has an alignment soldering bump. and the other has the form of an alignment pad corresponding to the alignment solder bump, or the plurality of first-level first alignment soldering portions and the plurality of first-level second alignment The welding parts all have the form of aligned welding bumps; and at least one of the plurality of second-level first alignment welding parts and the plurality of second-level second alignment welding parts has an alignment welding bump. Point shape. The semiconductor packaging method according to claim 1, wherein the plurality of second-level interconnection bumps correspond to the plurality of first-level interconnection bumps respectively. The semiconductor packaging method of claim 1, wherein the plurality of second-level interconnection bumps and the plurality of second-level first alignment soldering portions together serve as the at least one second-level device. A plurality of second-level interconnection terminals on the first surface of the second level respectively correspond to the plurality of first-level interconnection bumps. The semiconductor packaging method according to claim 3, wherein between the S450 and the S460, it further includes: forming a The plurality of second level second alignment welds. The semiconductor packaging method according to claim 3, wherein the second-level first alignment welding The first-level device has the form of aligned solder bumps, and in S410, the first-level device also forms the plurality of second devices in the form of aligned solder bumps on the first-level first surface. The second level is aligned with the welded part. The semiconductor packaging method of claim 4, wherein the second-level first alignment soldering portion has the form of an aligned soldering bump, and in the S460, the plurality of first-level interconnection bumps are A portion corresponding to each of the plurality of second-level first alignment welding portions serves as the plurality of second-level second alignment welding portions. The semiconductor packaging method according to claim 4, wherein between the S450 and the S460, it further includes: aligning the plurality of second-level first-level interconnect bumps with the plurality of first-level interconnection bumps. The plurality of second-level second alignment welding portions in the form of aligned welding bumps are respectively formed on corresponding portions of the welding portions. The semiconductor packaging method of claim 1, wherein at least one of the at least one first-level device and the at least one second-level device includes at least one of a semiconductor device and an interconnection board, the interconnection The board is an adapter board or base board. The semiconductor packaging method according to claim 1, wherein at least one of the at least one first-level device and the at least one second-level device is further provided with at least one through electrode. The semiconductor packaging method of claim 1, wherein in a direction perpendicular to the second-level first surface of the at least one second-level device, the height of the second-level interconnect bump is less than the The sum of the heights of the second-level first alignment welding portion and the second-level second alignment welding portion is such that the first-level interconnection bumps and the second-level interconnection bumps are in the S470 spaced apart from each other before performing the pressing. The semiconductor packaging method of claim 1, wherein in the S470, the at least one second-level device and the first-level component are accurately aligned and the plurality of second-level alignment solder joints are While still in an at least partially molten state, the at least one second stage device and the first stage The plurality of second-level interconnection bumps and corresponding first-level interconnection bumps are respectively engaged while the components are pressed toward each other. The semiconductor packaging method of claim 1, wherein in S470, after the at least one second-level device is accurately aligned and fixed to the first-level component, the second-level alignment welding The points are again at least partially melted, and the plurality of second-level interconnect bumps and corresponding first-level interconnect bumps are pressed while pressing the at least one second-level device and the first-level element toward each other. points are joined separately. The semiconductor packaging method of claim 1, wherein at least one of the first-level interconnection bumps and the second-level interconnection bumps contains solder and the plurality of first-level interconnection bumps in S470 are The second-level interconnection bumps and the corresponding first-level interconnection bumps are respectively joined to form a plurality of interconnection joints including: connecting the plurality of second-level interconnection bumps and the corresponding first-level interconnection bumps. Solder separately to form interconnecting solder joints. The semiconductor packaging method according to claim 1, wherein neither the first-level interconnection bumps nor the second-level interconnection bumps include solder, and the plurality of second-level interconnections in S470 are The connecting bumps and the corresponding first-level interconnection bumps are respectively joined to form a plurality of interconnection joints including: heat pressing the plurality of second-level interconnection bumps and the corresponding first-level interconnection bumps. Binding. The semiconductor packaging method of claim 1, wherein the plurality of second-level alignment solder joints and/or the plurality of interconnection joints are at least partially solidified to secure the at least one second-level device to After the first level component is removed, the pressing is released. A semiconductor element packaged by the semiconductor packaging method according to any one of claims 1 to 16, the semiconductor element including at least one first-level device and at least one second-level device Device, wherein the at least one second level device is disposed above a first level element formed from the at least one first level device. An electronic device including the semiconductor element according to claim 17.