TWI828013B - Semiconductor packaging method, semiconductor assembly, and electronic device including the same - Google Patents

Abstract

The invention discloses a semiconductor packaging method, a semiconductor assembly and an electronic device including the semiconductor assembly. The semiconductor packaging method comprises the steps: providing at least one semiconductor device and a carrier plate, wherein a plurality of first alignment welding parts are formed on the active surface of the semiconductor device besides connecting terminals, and a plurality of corresponding second alignment welding parts are formed on the carrier plate; placing the semiconductor device on the carrier plate so that the first alignment welding parts are substantially aligned with the second alignment welding parts; forming an alignment welding spot by welding the first alignment welding parts and the second alignment welding parts so that these miconductor device is accurately aligned and fixed to the carrier plate; forming a plastic package body by performing plastic package on the side where the semiconductor device of the carrier plate is located; exposing the connecting terminals from the plastic package body after the carrier plate is removed; and sequentially forming an interconnection layer and an external terminal on the surface of the plastic package body so that the connecting terminals are connected to the external terminal through the interconnection layer, wherein the surface exposes the connecting terminals.

Description

Semiconductor packaging method, semiconductor component and electronic device including same

Embodiments of the present application relate to the field of semiconductor manufacturing technology, and in particular to semiconductor packaging methods, semiconductor components, and electronic equipment including the semiconductor components.

Semiconductor packages and systems have always pursued density, smallness, lightness and thinness in design, while striving to achieve high integration and multi-functionality in terms of functionality. Currently, a variety of packaging technologies are proposed to meet the above technical requirements, such as fan-out wafer-level packaging, chiplet, heterogeneous integration, 2.5D/3D 3D) packaging. These packaging technologies have different advantages and characteristics, but there are also some technical challenges. Taking the existing fan-out package as an example, it faces many technical problems, such as warpage, die shift, surface flatness (toporgraphy), and non-coplanarity between the chip and the plastic package (chip). -to-mold non-planarity), packaging reliability (Reliability), etc. Although the industry continues to work hard to improve these technical problems by improving equipment, materials, and processes. But there are still no economical and effective solutions to some technical problems, especially warpage, wafer drift and surface coplanarity between different wafers.

In addition, there are some common technologies in the manufacturing process of various high-end semiconductor packaging and systems, which often involve high-precision placement and fixation of semiconductor devices. This process step is usually performed by high-precision pick and place or die bonder equipment, but its placement speed is limited, making the production speed very slow, and the equipment cost is expensive, which has become a major bottleneck in the development and popularization of technology.

Semiconductor components (also called semiconductor packages) are the core components of modern electronic equipment or products. Semiconductor components can be roughly divided in terms of device quantity and density: discrete semiconductor components, that is, single-chip components, such as a single digital logic processor, diode, transistor; multi-chip components, such as image sensors (CIS) and image processor (ASIC) modules, central processing unit (CPU) and dynamic memory device (DRAM) stack; and system-level components, such as RF front-end modules (FEM) in mobile phones, mobile phones and Display module in smart watch. Usually, system-in-package contains a wider range of devices. In addition to semiconductor devices, there are also passive components (resistors, capacitors, inductors) and other devices and even components.

Semiconductor components in this article may include active and passive components, including but not limited to bipolar transistors, field effect transistors, integrated circuits and other active components and chip resistors, capacitors, inductors, integrated passive components ( IPD), microelectromechanical systems (MEMS) and other passive devices. Various electrical connections are established between various active and passive devices to form circuits that enable semiconductor components to perform high-speed calculations and other useful functions.

Currently, semiconductor manufacturing typically involves two complex manufacturing processes, front-end wafer manufacturing and back-end packaging manufacturing, each of which may involve hundreds of steps. Front-end wafer manufacturing involves forming multiple dies on the surface of a wafer. Each wafer is typically identical and contains circuitry formed by electrically connecting active and/or passive elements. Back-end packaging manufacturing involves separating individual wafers from completed wafers and packaging them into semiconductor components to provide electrical connections, structural support, heat dissipation and environmental isolation, while facilitating subsequent assembly of electronic products.

An important goal of semiconductor manufacturing is to produce smaller semiconductor devices, packages, and components. Smaller products usually have higher integration, consume less power, have higher performance, and have smaller area/volume, which is very important for the market performance of the final product. On the one hand, smaller integrated circuits can be made by improving the front-end wafer process, thereby shrinking the wafer, increasing density and improving performance. On the other hand, backdoor Packaging processes can further reduce the size, increase density and improve performance of semiconductor components by improving packaging design, processes and packaging materials.

Currently, in the back-end packaging process, a relatively novel and efficient packaging method is fan-out packaging. Fan-out packaging involves coating single or multiple qualified dies (dies) from diced wafers with molding compound and routing interconnect traces from the die's interconnect pads to the outside via a redistribution layer (RDL). solder balls to achieve higher I/O density and flexible integration packaging technology. Fan-out packaging can be mainly divided into chip-first packaging and chip-last packaging. Chip-first packages can be divided into active surface-down (face-down) and active surface-up (face-up) types.

The mainstream process of chip-first/face-down packaging may include the following main steps: picking up the wafer from the diced wafer and placing it on a carrier plate with an adhesive film so that its active surface faces the adhesive film; applying molding compound Molding the side on which the chip is mounted; removing the carrier (together with the adhesive film) to expose the active surface of the chip; forming interconnect layers (including RDL layers and under-bump metallization (UBM) on the active surface of the chip )); forming solder balls on the interconnect layer, wherein the interconnect pads or interconnect bumps of the wafer are electrically connected to the solder balls through the interconnect layer; and cutting to form independent semiconductor components.

The chip-first/face-up packaging process can be roughly the same as the chip-first/face-down packaging process. The main difference is that when the chip is picked up and placed on the carrier plate with adhesive film, its active surface backing to the adhesive film; thinning the molding compound on the active surface side of the wafer after molding to expose the interconnect bumps on the active surface of the wafer; and the carrier board can be removed after the interconnect layers and solder balls are formed.

Among the technical problems currently faced by fan-out packaging, there is still a lack of efficient and economical methods for high-precision placement and position fixation of chips. Often, the higher the wafer placement accuracy, the higher the equipment cost and the lower the production efficiency. Moreover, it is difficult for the accuracy of wafer loading equipment to exceed the 0.5 micron limit. In addition, after the wafer is placed on the adhesive film, the position is fixed by the adhesive film, but the adhesive film is deformable, and the plastic sealing material is The flow will push the wafer, causing the wafer to shift and rotate on the adhesive film. The higher temperatures used in the encapsulation process exacerbate this problem. Another source of wafer displacement and rotation is the internal stress within the plastic package (a form in which the wafer and carrier are overmolded with plastic material). Specifically, in the existing chip-first/face-down packaging process, the plastic sealing process includes three stages: heating injection molding, partial solidification of the plastic sealant while maintaining high temperature, and cooling. This is usually followed by a constant-temperature heating step to completely cure the molding compound. There are differences in the thermal expansion coefficients of wafers, plastic packaging materials, plastic films, carrier boards, etc. Therefore, the mismatch of thermal expansion coefficients of various materials during the plastic packaging process and the curing shrinkage of the plastic packaging materials lead to uneven internal stress in the plastic packaging body, further causing chip drift and / Or rotation (as shown in the chip arrangement in the lower right of Figure 1) and warping of the plastic package. Wafer drift and/or rotation will cause mismatch or misalignment between the subsequently formed RDL traces and UBM (as shown in the upper right of Figure 2 after wafer drift and rotation), which may result in a significant decrease in yield. . The warpage of the plastic package will cause difficulties in subsequent packaging processes including under-bump metallization (UBM) and redistribution (RDL). In severe cases, the process may even be impossible to continue.

The present invention aims to solve several core technical problems mentioned above.

The purpose of this application is to propose a new breakthrough semiconductor packaging method, a semiconductor component, and an electronic device containing the semiconductor component, so as to at least solve the above and other technical problems existing in the prior art.

One aspect of the present application provides a semiconductor packaging method, including: providing a semiconductor device and a carrier board, wherein in addition to connection terminals, a plurality of first alignment soldering portions are formed on an active surface of the semiconductor device, and the carrier board A plurality of second alignment welding parts respectively corresponding to the plurality of first alignment welding parts are formed on the board; The semiconductor device is placed on the carrier such that the plurality of first alignment soldering portions are substantially aligned with the plurality of second aligning soldering portions; by performing the plurality of first alignment soldering portions and the plurality of second alignment welding parts to form a plurality of alignment welding spots, so that the semiconductor device is accurately aligned and fixed to the carrier board; by the semiconductor device on the carrier board Molding is performed on the side to form a plastic encapsulation body covering the semiconductor device; after the carrier board is removed, the connection terminals are exposed from the plastic encapsulation body; and the surface of the plastic encapsulation body exposing the connection terminals An interconnection layer and external terminals are sequentially formed on the substrate, so that the connection terminals are connected to the external terminals through the interconnection layer.

Another aspect of the present application provides a semiconductor element packaged by the above semiconductor packaging method.

Another aspect of the present application provides an electronic device including the above-mentioned semiconductor element.

It should be understood that the above description is only an overview of the present application, so that the technical solution of the present application can be understood more clearly, so that it can be implemented according to the content of the description. In order to make the above and other objects, features and advantages of the present application more apparent and understandable, specific embodiments of the present application are described in detail below.

S310: Provide at least one semiconductor device and a carrier board, wherein in addition to the connection terminals, a plurality of first alignment welding portions are formed on the active surface of the semiconductor device, and the carrier board is formed with a plurality of first alignment welding portions. A plurality of second alignment welding parts respectively corresponding to the first alignment welding parts

S320: Place the at least one semiconductor device on the carrier such that the plurality of first alignment welding portions and the plurality of second alignment welding portions are substantially aligned

S330: Form a plurality of alignment welding spots by welding the plurality of first alignment welding parts and the plurality of second alignment welding parts, so that the at least one semiconductor device is accurately aligned and fixed to the carrier board

S331: Turn over the semiconductor device and the carrier board as a whole, so that the carrier board is above the at least one semiconductor device, and melt or partially melt the alignment solder joints again and then cool them down. The alignment solder joint solidifies

S332: After the alignment solder joints are melted or partially melted again, use a pressing plate to flatten the passive surfaces of the multiple semiconductor devices, so that the passive surfaces of the multiple semiconductor devices are basically located at In the same plane parallel to the carrier plate

S340: Form a plastic package covering the semiconductor device by performing plastic sealing on the side of the carrier board where the semiconductor device is located.

S350: After removing the carrier board, expose the connection terminals from the plastic package

S360: Sequentially form an interconnection layer and an external terminal on the surface of the plastic package where the connection terminal is exposed, so that the connection terminal is connected to the external terminal through the interconnection layer.

410:Semiconductor devices

411: Source surface

412:Align soldering bumps

413:Align solder joints

414:Interconnect bumps

420: Carrier board

422: Align pad

430:Plastic sealing body

442: Trace

444:UBM

446:Dielectric layer

450: Solder ball

520: Carrier board

510:Semiconductor devices

511: Source surface

512: Soldering bumps

513:Align solder joints

514:Interconnect pad

522: Align pad

530:Plastic sealing body

542: trace

544:UBM

546:Dielectric layer

550: Solder ball

準或塑封模流(mold flow)推擠造成的晶片漂移和晶片旋轉現象的示意圖。 [Fig. 1] shows an illustration of inaccuracies in placement and positioning during a chip-first fan-out type packaging process according to the prior art.

Schematic diagram of wafer drift and wafer rotation caused by quasi or mold flow pushing.

[Fig. 2] Schematic diagram showing a state of mismatch (or misalignment) of under-bump metal (UBM) and redistribution layer (RDL) trace positions formed after wafer drift and rotation as shown in Fig. 1 in the prior art. .

[Fig. 3] A flowchart showing a packaging method according to an embodiment of the present application.

[Figs. 4A to 4G] show cross-sectional views for schematically explaining a packaging method according to an exemplary embodiment of the present application.

[Figs. 5A to 5G] Show cross-sectional views for schematically explaining a packaging method according to another exemplary embodiment of the present application.

This application includes the following description of at least one embodiment with reference to the accompanying drawings, in which like numerals refer to the same or similar components. Although the following description is primarily based on specific embodiments, it will be understood by those of ordinary skill in the art that the following description is intended to cover all aspects of the application that may be included in the application as defined by the appended claims and their equivalents and as supported by the following description and drawings. Substitutions, modifications, and equivalent technical means or solutions within the concept and scope of the invention. In the following description, some specific details, such as specific configurations, compositions, processes, etc., are given in order to provide a full understanding of the present application. In other instances, specific details of well-known processes and manufacturing techniques have not been described in order to avoid unnecessarily obscuring the present application. Furthermore, the various embodiments shown in the drawings are schematic illustrations and not necessarily to scale.

This application aims to propose a new and breakthrough packaging method that can at least solve the above technical problems.

The packaging method according to the embodiment of the present application utilizes the self-alignment ability of the alignment solder joint (joint) between the semiconductor device and the carrier board when the solder is in a molten or partially molten state to automatically and accurately align the semiconductor device to the carrier board. target position and achieve positional fixation of the semiconductor device after solidification of the solder, where the active surface of the semiconductor device (i.e. the front side having connection terminals, where the connection terminals may be interconnection pads or interconnections formed thereon A first alignment welding portion and a corresponding second alignment welding portion (for example, one of them is an alignment welding bump and the other is an alignment welding bump) are respectively preformed on one side of the carrier board and the alignment pad; or both alignment solder bumps). The packaging method causes the first and second alignment soldering parts to contact each other after placing the semiconductor device at a target position on the carrier board. One (or both) is melted to form an alignment solder joint. At this time, if the semiconductor device is not accurately aligned to the target position on the carrier (i.e., the first alignment solder portion and the second alignment solder portion are not aligned) , then the aligned solder joints in the molten or partially molten state (liquid or partially liquid state) will automatically and accurately introduce the semiconductor device to the target position based on the principle of minimum surface energy to minimize the surface energy, and the aligned solder joints will Keep the semiconductor device firmly in place at the target location. The first alignment welding part and the second alignment welding part (in aspects including but not limited to volume, geometry, composition, location, distribution, quantity, etc.) are optimally designed to achieve the most accurate, effective, efficient and reliable automatic welding. Alignment capabilities. Since the welding method is used instead of the film adhesion method to fix the semiconductor device on the carrier board, it not only improves the warpage problem but also prevents the possible drift and rotation problems of the semiconductor device during the plastic packaging process through the strong welding method. It can also take into account the alignment welding. The self-alignment ability of the points allows a certain degree of placement deviation when picking and placing semiconductor devices, thereby significantly reducing the requirements for semiconductor device placement accuracy (especially the pick and place or die bonder), and It can significantly increase the speed of semiconductor device pick-up and placement operations, thereby improving process efficiency and reducing process costs.

As used herein, the term "semiconductor device" may refer to a wafer (also interchangeably referred to as a die, die, die, integrated circuit) produced in a fab (fab), that is, after wafer dicing and Chips that have not been packaged after testing can usually only have interconnect pads for external connections. If desired, the semiconductor device may also be a pre-processed (at least partially packaged) wafer, such as having interconnect bumps formed on the interconnect pads, or the semiconductor device may have additional structures, such as stacked wafers. and packaged wafers.

The term "active surface" as used herein generally refers to the circuit-functional side surface of a semiconductor device having interconnect pads thereon (or interconnect bumps formed on interconnect pads), and may be used interchangeably. The ground is called the front or functional surface. The active surface of the semiconductor device and the other side surface that does not have a circuit function (interchangeably referred to as the passive surface or back surface) face each other.

The term "connection terminal" as used herein generally refers to an interconnect pad or interconnect bump on an active surface of a semiconductor device.

The term "alignment weld" as used herein generally refers to a structure that can be welded to a corresponding another alignment weld for alignment by welding methods known in the art.

Figure 3 shows a schematic flowchart of a packaging method according to an embodiment of the present application. As shown in Figure 3, the packaging method includes the following steps:

S310: Provide at least one semiconductor device and a carrier board, wherein in addition to the connection terminals, a plurality of first alignment soldering portions are formed on the active surface of the semiconductor device, and the carrier board is formed with a plurality of first alignment welding portions. The first alignment welding parts correspond to a plurality of second alignment welding parts respectively.

In some embodiments, there are multiple semiconductor devices. As an example, the plurality of semiconductor devices may be at least partially different from each other in function, size or shape, or may be identical to each other. It should be understood that the method can be determined according to specific process conditions or actual needs (for example, the size and shape of the carrier board and the semiconductor device, the placement spacing or packaging size and shape of the semiconductor device, manufacturing process specifications, functional design of the semiconductor element, etc.) The type and specific number of the semiconductor devices are appropriately selected and are not specifically limited in this application.

In some embodiments, the carrier is a glass carrier, a ceramic carrier, a metal carrier, an organic polymer material carrier, a silicon wafer, or a combination of two or even more of the above carriers.

In some embodiments, any one of the first alignment welding portion and the second alignment welding portion is an alignment welding bump, and the other is an alignment welding bump corresponding to the alignment welding bump. Align pads. In other embodiments, the first alignment welding part and the second alignment welding part are both alignment welding bumps, and their melting points may be the same or different. As an example, the alignment soldering bumps can be pre-fabricated on the semiconductor device (e.g., wafer) or carrier board. As an example, the alignment pads may be pre-fabricated on the semiconductor device or carrier using a deposition (eg, metal layer)-photolithography-etching process. It should be understood that the first alignment welding part and the second alignment welding part may also adopt any other welding structure or form as long as they can be welded to each other for alignment purposes.

In some embodiments, the first alignment welding portions correspond to the second alignment welding portions in terms of volume, size, geometry, composition, distribution, location, number, etc., so that they can be made by welding to each other. The semiconductor devices are accurately aligned to corresponding target positions on the carrier board.

It should be understood that the first alignment welding can be appropriately selected according to specific process conditions or actual needs (for example, the size and shape of the carrier and the semiconductor device, the placement pitch of the semiconductor device, or the package size and shape, etc.) The specific volume, size, geometry, composition, distribution, location and quantity of the second alignment welding portion and/or the second alignment welding portion are not specifically limited in this application. For example, the first alignment bonding portions may be formed to have substantially the same volume, size, geometry, or composition for all semiconductor devices, regardless of whether the function, size, or shape is the same as each other, and the second alignment bonding portion on the carrier may be The aligned welding portions can all be formed with substantially the same volume, size, geometry or composition to reduce subsequent process complexity and improve packaging efficiency. For another example, for semiconductor devices with different functions, sizes or shapes, the first alignment welding part and the second alignment welding part may be formed into different volumes, sizes, geometries or compositions so that they can be welded later. Different solder joint heights are then formed to achieve specific functions or meet specific requirements. in some In an embodiment, for a plurality of semiconductor devices, the first alignment welding portion and/or the second alignment welding portion are configured such that the active surfaces of the plurality of semiconductor devices after subsequent formation of alignment welding points can lie in the same plane parallel to the carrier plate. In some embodiments, for a plurality of semiconductor devices, the first alignment bonding portion and/or the second alignment bonding portion are configured such that after subsequent formation of alignment bonding points, the plurality of semiconductor devices have no The source surface can lie in the same plane parallel to the carrier plate. For another example, at least three substantially regularly distributed first alignment welding portions may be formed on each of the semiconductor devices, so that the active surface of the semiconductor device can pass through the first alignment welding portions and all the first alignment welding portions. The welding of the second aligned welding portion is firmly and stably maintained in a plane substantially parallel to the carrier board. For another example, on each of the semiconductor devices, the first alignment welding portions may be distributed and formed on edges sufficiently far away from the connection terminals so as not to affect subsequent processes and product applications.

In some embodiments, the connection terminals are interconnect bumps, as shown in Figure 4A. As an example, the interconnection bumps may be pre-fabricated on the semiconductor device using bump production processes known in the art (for example, electroplating, ball placement, template printing, evaporation/sputtering, etc.) on the pad. For example, the interconnection bumps may be in the form of conductive pillars. As a specific embodiment, in a direction perpendicular to the active surface (or carrier) of the semiconductor device, the height of the interconnection bump is sufficiently smaller than the first alignment soldering portion and the second alignment The sum of the heights of the welding portions is such that the height of the alignment welding points formed after subsequent welding of the first alignment welding portion and the second alignment welding portion is greater than the height of the interconnection bumps, so as not to affect The subsequent welding of the first alignment welding portion and the second alignment welding portion, or the subsequent welding of the interconnection bumps on the first alignment welding portion and the second alignment welding portion It was damaged when pressed against the carrier plate.

In an alternative embodiment, the connection terminals are the interconnect pads themselves, as shown in Figure 5A.

S320: Place the at least one semiconductor device on the carrier board so that the plurality of first alignment welding portions and the plurality of second alignment welding portions are substantially aligned.

In some embodiments, the "substantially aligned" includes that the first alignment weld and the second alignment weld are respectively in contact with each other but are not precisely aligned in a direction perpendicular to the passive surface. middle. "Centered" herein generally means that the centers of the first alignment weld and the second alignment weld are aligned in a direction perpendicular to the passive surface. It should be noted that the “basic alignment” of the first alignment welding part and the second alignment welding part means that there is at least a gap between the first alignment welding part and the second alignment welding part. contact to such an extent that self-alignment is possible as described below by means of the minimum surface energy principle of the aligned solder joints in the molten or partially molten state during the welding process, so "substantially aligned" includes not exactly aligned but at least There is a state of physical contact, but the state of precise alignment is not excluded.

It should be understood that when the semiconductor device is placed on the carrier in step S320, the active surface of the semiconductor device faces the carrier (ie, the surface on which the first alignment soldering portion is formed), and the passive surface of the semiconductor device faces away from the carrier. plate.

S330: Form a plurality of alignment welding spots by welding the plurality of first alignment welding parts and the plurality of second alignment welding parts, so that the at least one semiconductor device is accurately aligned and fixed to the Describe the carrier board.

It should be noted that "precise alignment" means a state in which the deviation between the actual position and the target position of the semiconductor device on the carrier board is within the tolerance range of this field. It should be understood that the precise alignment is achieved by utilizing the principle of minimum surface energy that the solder joint formed by welding the first alignment welding part and the second alignment welding part exhibits in a molten or partially molten state during the welding process. Specifically, when the first alignment bonding portion and the second alignment bonding portion contact each other but are not precisely aligned in a direction perpendicular to the active surface of the semiconductor device or the carrier board, during the bonding process, the first alignment bonding portion the alignment weld portion and the second alignment weld portion One of the alignment solder bumps melts or partially melts and wets the other of the alignment pad or another alignment solder bump, or both the first alignment solder portion and the second alignment solder portion As the alignment welding bump melts or partially melts, thereby forming an alignment solder joint in a molten or partially molten state, at this time, based on the principle of minimum surface energy, the alignment solder joint in a molten or partially molten state will tend to deform and move. In order to bring the first alignment welding part and the second alignment welding part close to a centered state, thereby driving the semiconductor device that is lighter relative to the carrier board to be accurately aligned to the target position on the carrier board.

It should be understood that after welding the first alignment bonding portion and the second alignment bonding portion, due to the height of the alignment bonding point itself formed thereby (perpendicular to the active surface of the semiconductor device or the direction of the carrier), the active surface of the semiconductor device and the carrier are spaced apart to form a certain space therebetween.

In some embodiments, the alignment soldering bumps are made of solder, and the soldering can use various molten solder soldering methods known in the art, including but not limited to reflow soldering, laser soldering, high-frequency soldering, Infrared welding, etc.

In some embodiments, after S330, S331 is also included: flipping the semiconductor device and the carrier board as a whole, so that the carrier board is above the at least one semiconductor device, and again making the pair After the quasi-solder joints are melted or partially melted, the temperature is lowered to solidify the quasi-solder joints. It should be understood that at this time, the re-melted or partially melted alignment solder joints are moderately elongated due to the weight of the semiconductor device, thereby further improving the self-alignment accuracy. It should be noted that due to the surface energy of the alignment solder joints in the molten or partially molten state, the semiconductor device will not fall off the carrier due to its own weight. As an alternative embodiment, in S310, a viscous flux is pre-coated on the plurality of first alignment welding parts and/or the second alignment welding parts, and S330 includes S330': before performing the welding , flipping the semiconductor device and the carrier board as a whole, so that the carrier board is in the at least one semiconductor above the device. It should be understood that after flipping over at this time, the alignment solder joints that were melted or partially melted during the welding process are moderately elongated due to the weight of the semiconductor device, thereby further improving the self-alignment accuracy. It should be noted that since the sticky flux adheres the semiconductor device to the carrier board, the semiconductor device will not fall off from the carrier board due to its own weight after being turned over. It should be understood that before S340 described below, the semiconductor device and the carrier board need to be turned over again as a whole.

In some embodiments, when there are multiple semiconductor devices, S330 includes S330": when the semiconductor device and the carrier are accurately aligned and the alignment solder joints are still in a molten or partially molten state. , use a pressing plate to flatten the passive surfaces of the plurality of semiconductor devices, so that the passive surfaces of the plurality of semiconductor devices are substantially located in the same plane parallel to the carrier board. As an example, S330 ” includes: placing the platen over the passive surfaces of the plurality of semiconductor devices; pressing the platen toward the carrier such that the passive surfaces of the plurality of semiconductor devices are substantially positioned with the The carrier plate is parallel to the same plane; while maintaining the pressing, the temperature is lowered so that the alignment solder joints are basically solidified; and the pressing plate is removed. As an alternative embodiment, when there are multiple semiconductor devices, S332 is also included after S330: after melting or partially melting the alignment solder joints again, using a pressing plate to passively The surface is flattened so that the passive surfaces of the plurality of semiconductor devices are substantially located in the same plane parallel to the carrier board. As an example, the S332 includes: melting or partially melting the alignment solder joints again; placing the platen above the passive surfaces of the plurality of semiconductor devices; pressing the platen toward the carrier board, so that the passive surfaces of the plurality of semiconductor devices are substantially located in the same plane parallel to the carrier; while maintaining pressing, cooling is performed to allow the alignment solder joints to substantially solidify; and removing the Press the plate. It can be understood that since the pressing plate is kept pressed until the alignment solder joint is substantially solidified and then the pressing plate is removed, the surface energy of the molten solder joint can be prevented from returning the semiconductor device to its original height before flattening.

This ensures that the passive surfaces of all semiconductor devices are precisely flush and at the same height. It will be appreciated that appropriate pressure needs to be exerted on the platen so that the alignment pads in a molten or partially molten state are properly deformed and the resulting vertical (relative to the active surface of the semiconductor device or carrier) displacement of the platen is appropriate. , to prevent damage to semiconductor devices. As an example, a solder trap is preformed around the second alignment welding portion of the carrier board, thereby preventing excess molten solder from flowing uncontrollably during the pressing process.

In some embodiments, the above-mentioned flattening process using a pressing plate is combined with the above-mentioned welding process or re-melting process after flipping. As an example, S330" is executed after S330' is executed in S330, or S332 is executed after S330 including S330' is executed, or S331 is executed after S330 including S330" is executed, or S332 is executed while S331 is executed.

S340: Form a plastic encapsulation body covering the semiconductor device by performing plastic encapsulation on the side of the carrier board where the semiconductor device is located.

It should be understood that through the molding, not only the passive surface (ie, the opposite surface of the active surface) and side surfaces of the semiconductor device are covered, but also the space between the active surface of the semiconductor device and the carrier board is also covered. Filled to cover.

In some embodiments, a molding compound of a resinous material (eg, epoxy resin) is used for molding.

In some embodiments, molding processes such as injection molding, pressure injection, and printing are used for plastic sealing, and optionally combined with an underfill process.

S350: After removing the carrier board, expose the connection terminals from the plastic package.

In some embodiments, the carrier is removed by processes known in the art such as stripping, etching, ablation, and grinding. As an example, when using a peeling process, the soldering between the carrier board and the semiconductor device (ie, the alignment solder joints) can be desoldered to facilitate peeling off the carrier board from the plastic package. .

In some embodiments, some or all of the alignment solder joints are also removed when or after the carrier board is removed. As an example, some or all of the alignment solder joints may be removed by processes known in the art such as desoldering, etching, ablation, or grinding. In some embodiments, some or all of the alignment pads are retained as part of the final semiconductor component (i.e., the finished package) for electrical connections (eg, power and ground), heat dissipation, mechanical structure, etc.

In some embodiments, when the connection terminals are interconnection bumps, the interconnection bumps are made by thinning (such as grinding, etching or ablation, etc.) the plastic package after removing the carrier board. point exposed.

In some embodiments, when the connection terminal is an interconnection pad, the interconnection pad is exposed by forming an opening on the plastic package after removing the carrier board. As an example, laser ablation (eg, laser drilling) may be used to form the opening. As an example, the opening may be formed by mechanical drilling. As an example, before forming the opening, the plastic package may be thinned to meet product design requirements and/or to facilitate the opening.

S360: Sequentially form an interconnection layer and an external terminal on the surface of the plastic package where the connection terminal is exposed, so that the connection terminal is connected to the external terminal through the interconnection layer.

In some embodiments, the interconnection layer includes a redistribution layer (RDL) and an under-bump metal (UBM) in a direction away from the connection terminal, thereby achieving conductive connection between the connection terminal and the external terminal. . It should be understood that the interconnection layer also includes an insulating layer for achieving electrical insulation between conductive paths, and the specific number and material of the insulating layer can be appropriately selected according to specific process conditions or needs, and this application is not particularly limited. .

In some embodiments, the external terminals are solder balls.

In some embodiments, the external terminals are solder pads.

In some embodiments, the packaging method further includes: thinning (for example, grinding, etching or ablation, etc.) the side of the plastic package where the passive surface of the semiconductor device is located. As an example, the thickness may be thinned to the passive surface of the semiconductor device, or the thinned portion may include a portion of the passive surface side of the semiconductor device. As a result, the thickness of the final semiconductor element can be further reduced.

In some embodiments, passive devices are also packaged with the semiconductor device in substantially the same manner as in the embodiments described above.

In some embodiments, after S360, the packaging method further includes: cutting.

It should be understood that the dicing process may be performed to produce independent semiconductor components according to the packaging specifications of the semiconductor components (including but not limited to wafer level packaging, wafer level packaging, system level packaging), or the dicing process may not be performed.

Below, the packaging method according to the present application will be described in more detail with reference to exemplary embodiments.

4A to 4G show cross-sectional views for schematically illustrating a packaging method according to an exemplary embodiment of the present application.

As shown in Figure 4A, a plurality of semiconductor devices and a carrier board 420 are provided. Among the plurality of semiconductor devices, at least two semiconductor devices 410, 410' are different, such as different sizes and/or functions. On the active surface 411 of each semiconductor device 410, 410', a plurality of interconnection bumps 414 respectively conductively connected to the interconnection pads (not shown) are distributed in the area except the edges, and are formed on the edges. A plurality of alignment solder bumps 412 are formed spaced apart from the interconnect bumps 414 . For example, the active surfaces 411 of the semiconductor devices 410, 410' are generally rectangular, and substantially identical alignment solder bumps 412 may be formed near four corners of the rectangle. The height of the alignment solder bumps 412 in the direction perpendicular to the active surface 411 is greater than that of the interconnect bumps. 414. A plurality of corresponding alignment pads 422 are formed on one surface of the carrier board 420 in the same arrangement (or relative positional relationship) as the alignment soldering bumps 412 on each semiconductor device 410, 410'. Alternatively, in addition to the semiconductor devices, passive devices may be provided in a similar structure. For example, reference numeral 410' shown in Figure 4 may be replaced with a passive component.

As shown in FIG. 4B, the semiconductor devices 410, 410' are placed on the carrier 420 so that the alignment solder bumps 412 are in contact with the corresponding alignment pads 422. At this time, the alignment solder bump 412 and the alignment pad 422 are not aligned (ie, the vertical centerline L1 of the alignment solder bump 412 and the vertical centerline L2 of the alignment pad 422 do not coincide).

As shown in FIG. 4C , the alignment solder bumps 412 and the alignment pads 422 are soldered (eg, by reflow soldering) to form the alignment solder joints 413 . During the soldering process, the alignment solder bumps 412 in the molten state will wet the alignment pads and self-align with the alignment pads 422 based on their own minimum surface energy principle (i.e., the alignment solder bumps 412 The vertical center line L1 of the alignment pad 422 coincides with the vertical center line L2 of the alignment pad 422 ), so that the semiconductor devices 410 and 410 ′ are driven to achieve precise alignment on the carrier board 420 . After the soldering is completed, the active surfaces 411 of the semiconductor devices 410, 410' (and the interconnect bumps 414) are spaced apart from the carrier 420 to form a space.

As shown in FIG. 4D , plastic sealing is performed on the side of the carrier board 420 on which the semiconductor devices 410 and 410' are soldered. The plastic encapsulation 430 covers all surfaces of the semiconductor devices 410, 410', including the active surface 411 (and interconnection bumps 414), passive surfaces, and side surfaces. The space below the active surface 411 may be filled using an underfill process.

As shown in FIG. 4E , the carrier plate 420 is removed from the plastic package 430 and turned over as a whole. When the carrier board 420 is removed, at least a portion of the alignment pads 413 (including the alignment pads 422) may also be removed at the same time. After the whole body is turned over, the side of the plastic package 430 where the active surface 411 (or the interconnection bump 414) is located is reduced. Thin until interconnect bumps 414 are exposed. It will be appreciated that at least a portion of the remaining alignment pads 413 may be further removed by thinning.

As shown in FIG. 4F , redistribution layer (RDL) traces 442 , UBM 444 , and solder balls 450 are sequentially formed on the surface of the plastic package 430 with the interconnection bumps 414 exposed, so as to form the interconnection bumps 414 to the corresponding solder balls. 450 conductive path. During this process, particularly when forming RDL traces 442 and/or UBM 444, a dielectric layer 446 is also formed to achieve electrical isolation between conductive paths.

As shown in FIG. 4G, the other surface of the plastic package 430 (that is, the side where the passive surfaces of the semiconductor devices 410 and 410' are located) is thinned to remove part of the passive surfaces of the semiconductor devices 410 and 410'.

It should be understood that before, during or after each step of the above packaging method, other processing (for example, additional processing required for heterogeneous integrated packaging) may be further performed according to actual packaging needs.

Finally, although not shown in the figure, singulation can be performed according to the packaging specifications of the semiconductor device to complete the production of independent semiconductor devices.

5A to 5G show cross-sectional views for schematically illustrating a packaging method according to another exemplary embodiment of the present application. It should be noted that the parts that are the same or similar to the previous exemplary embodiment according to FIGS. 4A to 4G will not be described again.

As shown in Figure 5A, a plurality of semiconductor devices and a carrier board 520 are provided. On the active surface 511 of each semiconductor device 510, 510', a plurality of interconnection pads 514 are distributed in the area except the edge, and a plurality of alignment pads are formed spaced apart from the interconnection pad 514 at the edge. Solder bump 512. A plurality of corresponding alignment pads 522 are formed on a surface of the carrier board 520 .

As shown in FIG. 5B , the semiconductor devices 510, 510' are placed on the carrier 520 so that the alignment solder bumps 512 are in contact with the corresponding alignment pads 522. At this time, the alignment solder bumps 512 and the alignment pads 522 are misaligned.

As shown in Figure 5C, the alignment solder bumps 512 and the pads 520 are soldered to form the alignment solder joints 513, thereby achieving precise alignment of the semiconductor devices 510, 510' on the carrier board 520 based on the principle of minimum surface energy.

As shown in FIG. 5D , when the alignment solder joints 513 are still in a molten state, after placing the platen P on the passive surfaces of the semiconductor devices 510 and 510 ′ (ie, the opposite surface of the active surface 511 ), press (i.e. The plate P is pressed toward the carrier board 520 to perform a flattening process, so that the passive surfaces of the plurality of semiconductor devices 510, 510' are in the same plane parallel to the carrier board 520. Subsequently, the temperature is lowered while maintaining pressing to solidify the alignment solder joints 513, and then the pressing plate P is removed.

As shown in FIG. 5E, plastic packaging is performed on the side of the carrier board 520 on which the semiconductor devices 510 and 510' are placed. The plastic package 530 covers all surfaces of the semiconductor devices 510 and 510'.

As shown in FIG. 5F , the carrier plate 520 is removed from the plastic package 530 and turned over as a whole. Subsequently, drilling (eg, laser drilling) is performed on the side of the plastic package 530 where the active surface 511 (or the interconnection pad 514 ) is located, to expose the interconnection pad 514 . Thinning can be done if necessary before drilling.

As shown in FIG. 5G, redistribution layer (RDL) traces 542, UBM 544, and solder balls 550 are sequentially formed on the surface of the plastic package 530 with the interconnection pads 514 exposed, to form the interconnection pads 514 to the corresponding solder balls. 550 conductive path. During this process, particularly when forming RDL traces 542 and/or UBM 544, a dielectric layer 546 is also formed to achieve electrical isolation between conductive paths.

Finally, although not shown, cutting can be performed according to the functional design specifications of the semiconductor device to complete the production of independent semiconductor devices.

Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the concept and scope of the present application. In this way, if these changes and modifications of this application fall within the scope of the claims of this application and their equivalent technical solutions, the description of this application is also intended to include these changes and modifications.

S310: Provide at least one semiconductor device and a carrier board, wherein in addition to the connection terminals, a plurality of first alignment welding portions are formed on the active surface of the semiconductor device, and the carrier board is formed with a plurality of first alignment welding portions. A plurality of second alignment welding parts respectively corresponding to the first alignment welding parts

S320: Place the at least one semiconductor device on the carrier such that the plurality of first alignment welding portions and the plurality of second alignment welding portions are substantially aligned

S330: Form a plurality of alignment welding spots by welding the plurality of first alignment welding parts and the plurality of second alignment welding parts, so that the at least one semiconductor device is accurately aligned and fixed to the carrier board

S340: Form a plastic package covering the semiconductor device by performing plastic sealing on the side of the carrier board where the semiconductor device is located.

S350: After removing the carrier board, expose the connection terminals from the plastic package

S360: Sequentially form an interconnection layer and an external terminal on the surface of the plastic package where the connection terminal is exposed, so that the connection terminal is connected to the external terminal through the interconnection layer.

Claims (20)

A semiconductor packaging method, including: S310: providing at least one semiconductor device and a carrier board, wherein in addition to connection terminals, a plurality of first alignment welding portions are formed on the active surface of the at least one semiconductor device, and the carrier board A plurality of second alignment welding portions respectively corresponding to the plurality of first alignment welding portions are formed on the board; S320: Place the at least one semiconductor device on the carrier board so that the plurality of first alignment welding portions are An alignment welding portion is substantially aligned with the plurality of second alignment welding portions; S330: Form a plurality of alignment welding portions by welding the plurality of first alignment welding portions and the plurality of second alignment welding portions. Alignment solder joints so that the at least one semiconductor device is accurately aligned and fixed to the carrier board; S340: Form a mold covering the at least one semiconductor device by performing plastic packaging on the side of the carrier board where the at least one semiconductor device is located. A plastic package of a semiconductor device; S350: after removing the carrier board, exposing the connection terminals from the plastic package; and S360: sequentially forming interconnections on the surface of the plastic package exposing the connection terminals layer and external terminals, such that the connection terminals are connected to the external terminals through the interconnection layer. The semiconductor packaging method according to claim 1, wherein any one of the first alignment welding part and the second alignment welding part has a form of an alignment welding bump, and the other one has a shape similar to that of the first alignment welding part and the second alignment welding part. The alignment soldering bumps correspond to the form of the alignment pads; or the plurality of first alignment welding parts and the plurality of second alignment welding parts all have the form of aligned soldering bumps. The semiconductor packaging method of claim 2, wherein the alignment soldering bumps are made of solder, and the soldering is performed by molten solder. The semiconductor packaging method according to claim 1, wherein the plurality of first alignment soldering portions are located on the active surface in an area without the connection terminals. The semiconductor packaging method of claim 1, wherein substantially aligning the plurality of first alignment welding portions with the plurality of second alignment welding portions includes: causing the plurality of first alignment welding portions The plurality of second alignment bonding portions are respectively in contact with each other but are not precisely aligned in a direction perpendicular to the active surface. The semiconductor packaging method according to claim 3, wherein in the S310, viscous flux is pre-coated on the plurality of first alignment welding parts and/or the second alignment welding parts, and the S330 Includes S330': before performing the welding, flipping the at least one semiconductor device and the carrier board as a whole so that the carrier board is above the at least one semiconductor device. The semiconductor packaging method according to claim 3, wherein after the S330, the semiconductor packaging method further includes S331: flipping the at least one semiconductor device and the carrier board as a whole, so that the carrier board is Above the at least one semiconductor device, the plurality of alignment solder joints are melted or partially melted again and then cooled and solidified. The semiconductor packaging method according to claim 3, wherein when the at least one semiconductor device is multiple, the S330 includes S330″: forming precise alignment between the multiple semiconductor devices and the carrier board but the When the plurality of alignment solder joints are still in a molten or partially molten state, a pressing plate is used to flatten the passive surfaces of the plurality of semiconductor devices, so that the passive surfaces of the plurality of semiconductor devices are substantially located between The carrier plate is parallel to the same plane until the alignment solder joints are substantially solidified, and then the pressing plate is removed. The semiconductor packaging method according to claim 3, wherein when the at least one semiconductor device is multiple, the semiconductor packaging method further includes S332 after the S330: melting or partially melting the alignment solder joints again Finally, a pressing plate is used to flatten the passive surfaces of the plurality of semiconductor devices, so that the passive surfaces of the plurality of semiconductor devices are substantially located in the same plane parallel to the carrier board until the The alignment solder joints are substantially solidified, and then the platen is removed. The semiconductor packaging method according to claim 3, wherein solder wells are respectively pre-formed around the plurality of second alignment welding portions of the carrier board. The semiconductor packaging method according to claim 1, wherein the connection terminals are interconnection bumps formed on interconnection pads, and in a direction perpendicular to the active surface, the first alignment bonding The sum of the heights of the joint and the second alignment solder portion is large enough such that the height of the alignment solder joint is greater than the height of the interconnection bump. The semiconductor packaging method of claim 11, wherein exposing the connection terminals from the plastic package includes: exposing the interconnection bumps by thinning the plastic package. The semiconductor packaging method of claim 1, wherein the connection terminal is an interconnection pad, and exposing the connection terminal from the plastic package includes: forming an opening on the plastic package to expose the interconnection pad. Even the pads are exposed. The semiconductor packaging method according to claim 1, further comprising: thinning the side of the plastic package where the passive surface is located. The semiconductor packaging method according to claim 1, further comprising: performing cutting after forming the interconnection layer and the external terminal. The semiconductor packaging method of claim 1, when the carrier board is removed or after the carrier board is removed, the alignment solder joints are at least partially retained for manufacturing by the semiconductor packaging method. At least one of the electrical connection, heat dissipation and mechanical structure of the semiconductor component. The semiconductor packaging method according to claim 1, further comprising: when removing the carrier board or after removing the carrier board, also removing at least part of the alignment solder joints. The semiconductor packaging method according to claim 1, wherein the interconnection layer includes a redistribution layer and an under-bump metal layer in order away from the connection terminals. A semiconductor element packaged by the semiconductor packaging method according to any one of claims 1 to 18. An electronic device including the semiconductor element according to claim 19.