KR20220074762A - A method of packaging semiconductor, semiconductor assembly and electronic device comprising the same - Google Patents

Abstract

The present application discloses a semiconductor packaging method, a semiconductor assembly, and an electronic device including the same. A semiconductor packaging method includes providing at least one semiconductor device and a carrier substrate, further forming a plurality of first alignment soldering portions in addition to a connection terminal on an active surface of the semiconductor device, and forming a plurality of second alignment soldering portions corresponding to the carrier substrate step; disposing the semiconductor device on a carrier substrate to generally align the first alignment soldering portion with the second alignment soldering portion; forming an alignment solder joint by soldering the first alignment soldering unit and the second alignment soldering unit, thereby accurately aligning and fixing the semiconductor device to the carrier substrate; forming a molded body by performing molding on a side of the carrier substrate on which the semiconductor device is located; after removing the carrier substrate, exposing the connection terminal from the molding body; and sequentially forming an interconnection layer and an external terminal on a surface where the connection terminals of the molding body are exposed, and connecting the connection terminals to the external terminals through the interconnection layer.

Description

A method of packaging semiconductor, semiconductor assembly and electronic device comprising the same

Embodiments of the present application relate to the field of semiconductor manufacturing technology, and more particularly, to a semiconductor packaging method, a semiconductor assembly, and an electronic device including the same.

Semiconductor packages and systems have been pursuing compactness, miniaturization, weight reduction, and thinness in terms of design, and high integration and versatility in terms of functionality. At present, in order to meet the above technical needs, various packaging technologies, for example, fan-out type wafer-level packaging, chiplet packaging, heterogeneous integration, 2.5-dimensional (2.5d)/3-dimensional ( 3D) packaging has been proposed. Each of these packaging technologies has different advantages and characteristics, but all of them have some technical problems. Taking conventional fan-out packaging as an example, warpage, die shift, surface toporgraphy, chip-to-mold non-planarity, reliability of packaging ( Reliability), etc., are faced with various technical problems. Within the industry, there are continuous efforts to improve these technical problems through the improvement of equipment, materials, process details, etc., but in some technical problems, in particular, the problems of torsion, die shift, and surface planarity between different chips can be solved economically and effectively. no solution yet

In addition, some common technologies exist in the manufacturing process of various high-end semiconductor packages and systems, and are often related to high-precision placement and fixing of semiconductor devices. These process steps are generally performed by high-precision chip mounting (pick and place or die bonder) equipment, but the pick-and-place speed is limited, so the production speed is very slow, and the cost of the equipment is high, which is a big obstacle to technology development and dissemination. becomes this

An object of the present invention is to solve some of the key technical problems.

The present application aims to provide a novel and innovative semiconductor packaging method, a semiconductor assembly, and an electronic device including the semiconductor assembly, which can solve at least the above and other technical problems existing in the prior art.

The present application provides a semiconductor packaging method in one aspect, which

A semiconductor device and a carrier substrate are provided to further form a plurality of first alignment soldering portions in addition to the connection terminals on the active surface of the semiconductor device, and a plurality of second alignment soldering portions respectively corresponding to the plurality of first alignment soldering portions are formed on the carrier substrate. forming an alignment soldering part;

disposing the semiconductor device on the carrier substrate to generally align the plurality of first alignment soldering portions with the plurality of second alignment soldering portions;

forming a plurality of alignment solder joints by soldering the plurality of first alignment soldering units and the plurality of second alignment soldering units, thereby accurately aligning and fixing the semiconductor device to a carrier substrate;

forming a molding body surrounding the semiconductor device by performing molding on a side of the carrier substrate on which the semiconductor device is located;

after removing the carrier substrate, exposing the connection terminal from the molding body; and

and sequentially forming an interconnection layer and an external terminal on a surface on which the connection terminal of the molding body is exposed, and connecting the connection terminal to the external terminal through the interconnection layer.

In another aspect, the present application provides a semiconductor assembly, wherein the semiconductor assembly is packaged through the semiconductor packaging method.

In another aspect, the present application provides an electronic device including the semiconductor assembly.

The above description is merely a schematic description of the present application so that the technical solution of the present application can be clearly understood and implemented according to the contents of the specification. In order that the above and other objects, features, and advantages of the present application may be more clearly and easily understood, a specific implementation method of the present application will be described in detail below.

Since the semiconductor device is fixed to the carrier substrate by replacing the bonding method of the adhesive film using the soldering method, not only the torsion problem is improved, but also the die shift and rotation problems that may occur in the semiconductor device during the molding process through the solid soldering method In addition, in consideration of the self-aligning ability of the alignment solder joint, a predetermined placement deviation can be tolerated when picking up and placing the semiconductor element, so that the placement accuracy of the semiconductor element (especially the pick and place or die bonder))), and the pick-up and placement operation speed of semiconductor devices is significantly improved, thereby increasing process efficiency and reducing process costs.

FIG. 1 is an explanatory diagram illustrating die shift and chip rotation caused by misalignment or mold flow pushing during a chip-first fan-out packaging process according to the related art.
FIG. 2 is an explanatory diagram of a mismatch (or misalignment) state of under bump metal layer (UBM) and redistribution layer (RDL) traces formed after the die shift and rotation shown in FIG. 1 .
3 is a flowchart of a packaging method according to an embodiment of the present application.
4A to 4G are cross-sectional views schematically illustrating a packaging method according to an exemplary embodiment of the present application.
5A to 5G are cross-sectional views schematically illustrating a packaging method according to another exemplary embodiment of the present application.

This application includes at least one embodiment of the reference drawings in the description that follows, wherein like numbers indicate like or similar elements. Although the following description is mainly based on specific embodiments, for those of ordinary skill in the art, the following description is defined by the appended claims and equivalents, and the invention of the present application supported by the following description and accompanying drawings It should be understood that the purpose is to cover alternatives, modifications, and equivalent technical means or measures included within the concept and scope. In the following description, some specific details, such as specific arrangements, compositions, and processes, are provided in order to provide a sufficient understanding of the present application. In other circumstances, specific details of well-known processes and manufacturing techniques are not described in order to avoid unnecessary confusion with respect to the present application. In addition, various embodiments shown in the accompanying drawings are schematically illustrated and are not necessarily drawn to scale.

BACKGROUND Semiconductor assemblies (also called semiconductor packages) are a key component of modern electronic devices or products. A semiconductor assembly is generally a discrete semiconductor assembly in terms of the quantity and density of devices, that is, a single-chip assembly such as a single digital logic processor, a diode, and a triode; multi-chip assemblies such as modules of image sensors (CIS) and image processors (ASICs), central processing units (CPUs) and dynamic memory (DRAM) stacks; and system-level assemblies, such as RF front-end modules (FEM) in mobile phones, and display screen modules in mobile phones and smart watches. Typically, a system level package includes a relatively wide range of components, and in addition to semiconductor components, it further includes passive components (resistors, capacitors, inductors) and other components, even assemblies.

Semiconductor assemblies in this text may include active and passive components, and active components such as bipolar transistors, field effect transistors, integrated circuits, and chip resistors, capacitors, inductors, integrated passive devices (IPD), microelectromechanical systems (MEMS) passive elements such as, but not limited to. By establishing various electrical connections between various active and passive components, semiconductor assemblies form circuits capable of performing high-speed calculations and other useful functions.

Currently, semiconductor manufacturing typically includes two complex manufacturing processes, a front process for manufacturing a wafer and a post process for manufacturing a package, each process involving hundreds of steps. A whole process of manufacturing a wafer involves forming a plurality of chips (die) on the surface of the wafer, each chip is usually the same, and a circuit formed by electrically connecting active and/or passive units therein includes The post-process of manufacturing the package is related to separating individual chips from the finished wafer and packaging them into semiconductor assemblies to provide electrical connection, structural support, heat dissipation and environmental isolation, and at the same time provide convenience for the subsequent assembly of electronic products. do.

An important goal in semiconductor manufacturing is to produce smaller semiconductor devices, packages and assemblies. Smaller products typically have higher levels of integration, consume less power, have higher performance, and have a smaller area/volume, which is critical to the market performance of the final product. On the other hand, by improving the wafer process, which is the previous process, a smaller integrated circuit can be manufactured, thereby reducing the chip size, increasing the density, and improving performance. On the other hand, in the packaging process, which is a post-process, the size of the semiconductor assembly may be further reduced, the density may be increased, and performance may be improved by improving the package design, process, and package material.

In the current post-processing packaging process, a relatively novel and effective packaging method is fan-out packaging. Fanout packaging encapsulates one or more acceptance chips (die) from a cut wafer with a molding compound and draws interconnected traces via a redistribution layer (RDL) from the chip's interconnected pads to external solder balls, resulting in higher I/L. It is a packaging technology that realizes O density and flexible integration. Fan-out packaging can be mainly divided into chip-first packaging and chip-last packaging. Chip-first packaging can also be divided into active face-down and active face-up types.

The main stream process of chip-first/face-down packaging can include the following major steps: Picking up the chip from the cut wafer and placing it on a carrier substrate with an adhesive film attached thereto so that the active surface is an adhesive film to face; molding the side on which the chip is mounted using a molding compound; removing the carrier substrate (along with the adhesive film) to expose the active surface of the chip; forming an interconnect layer (including an RDL layer and an under bump metal layer (UBM)) on the active surface of the chip; forming solder balls in the interconnect layer, wherein the interconnect pads or interconnect bumps of the chip implement electrical connection with the solder balls through the interconnect layer; and cutting to form an independent semiconductor assembly.

The chip-first/face-up type packaging process can be largely the same as the chip-first/face-down type packaging process, with the main difference being that when the chip is picked up and placed on a carrier substrate to which an adhesive film is attached, the active surface The step of making the adhesive film and the back; thinning a molding compound on the active surface side of the chip after molding to expose interconnect bumps on the active surface of the chip; and removing the carrier substrate after the interconnect layer and the solder ball are formed.

The technical problem facing fan-out packaging today is that it still lacks an efficient and economical method for high-precision placement and positioning of chips. Often, the higher the placement precision of the chip, the higher the cost of the equipment, the lower the production efficiency, and the precision of the chip pick and place equipment is difficult to break through the 0.5 micron limit. In addition, after placing the chip on the adhesive film, the position is fixed with the adhesive film, but the viscous adhesive film has the potential to be deformed. causes The relatively high temperatures used in the molding process exacerbate this problem. Another cause of the movement and rotation of the chip is the internal stress in the molded body (the form in which the chip and the carrier substrate are molded by being wrapped in a molding material). When embodied in the conventional chip-first/face-down packaging process, the molding process includes three steps: heating and injection, maintaining the molding material at a high temperature for partial curing, and cooling. In general, there may be further a step of completely curing the molding material by heating it to a constant temperature thereafter. Since chips, molding materials, adhesive films, carrier substrates, etc. have different coefficients of thermal expansion, non-uniform internal stress of the molded body is caused due to mismatch of thermal expansion coefficients of various materials and curing shrinkage of molding materials during the molding process. Further, it results in die shift and/or rotation (chip arrangement in the lower right of Fig. 1) and distortion of the molded body. Die shift and/or rotation may further result in mismatch or misalignment of the subsequently formed RDL trace and UBM position (the state after the die shift and rotation in the upper right of FIG. . The torsion of the molded body can lead to difficulties in subsequent packaging processes, including under-bump metallization (UBM) and redistribution (RDL), in severe cases, even making it impossible to continue manufacturing.

It is an object of the present application to provide a new and innovative packaging method capable of solving at least the above technical problem.

The packaging method according to the embodiment of the present application uses the self-aligning ability of an alignment solder joint between a semiconductor device and a carrier substrate when solder is in a molten or partially molten state to automatically and accurately position a semiconductor device to a target position on a carrier substrate. Alignment and positioning to the semiconductor device can be achieved after the solder has solidified, wherein the active surface of the semiconductor device (i.e., the front surface with the connection terminals, the connection terminals may be interconnection pads, formed thereon) may be interconnect bumps) and second alignment soldering portions corresponding to the first alignment soldering portions, respectively, on one side of the carrier substrate (eg, one of which is an alignment solder bump and the other is an alignment pad; or two All are aligned solder bumps) are preformed. In the packaging method, one (or two) of the first alignment soldering unit and the second alignment soldering unit is melted after the semiconductor device is placed at a target position on the carrier substrate, the first alignment soldering unit and the second alignment soldering unit are brought into contact with each other. to form an alignment solder joint, and at this time, if the semiconductor device is not accurately aligned to the target position on the carrier substrate (that is, if the first alignment soldering part and the second alignment soldering part are not aligned), a molten or partially molten state (liquid state or Partial liquid state), the alignment solder joint automatically guides the semiconductor device to the target position precisely according to the principle of minimum surface energy to minimize the surface energy. keep the state The first alignment soldering part and the second alignment soldering part (including but not limited to aspects such as volume, geometry, composition, location, distribution and quantity) are the most accurate, effective, highly efficient and reliable self-alignment capability. It is desirable to design it to implement Since the semiconductor element is fixed to the carrier substrate by replacing the adhesion method of the adhesive film using the soldering method, not only the torsion problem is improved, but also the die shift and rotation problems that may occur in the semiconductor element during the molding process through the solid soldering method In addition, in consideration of the self-aligning ability of the alignment solder joint, a predetermined placement deviation can be tolerated when picking up and placing the semiconductor element, so that the placement accuracy of the semiconductor element (especially the pick and place or die bonder))), and the pick-up and placement operation speed of semiconductor devices is significantly improved, thereby increasing process efficiency and reducing process costs.

The term "semiconductor device" used in this text refers to a chip produced in a chip manufacturing plant (fab) (can be interchangeably referred to as a bare chip, die, wafer chip, and integrated circuit), that is, a wafer that is still packaged after being cut and tested. It means a chip that has not been used, and such a chip may typically have only interconnection pads for connecting to the outside. If necessary, the semiconductor device may be a chip that has undergone pretreatment (minimum partial packaging), such as forming interconnect bumps on interconnect pads, and the semiconductor device includes additional structures such as stacked chips and packaged chips. may be provided.

As used herein, the term “active surface” generally refers to the surface of the side having a circuit function of a semiconductor device, on which an interconnection pad (or interconnection bump formed on the interconnection pad) is provided, the front or They may be called interchangeably in terms of function. The active surface of the semiconductor element is opposed to the other surface (which may be referred to as a passive surface or a back surface interchangeably) which does not have a circuit function.

As used herein, the term “connection terminal” generally refers to an interconnection pad or interconnection bump on an active surface of a semiconductor device.

As used herein, the term “aligned soldering unit” refers to a structure for alignment that is soldered to a corresponding other alignment soldering unit through a soldering method known in the art.

3 is a flow explanatory diagram of a packaging method according to an embodiment of the present application. 3 , the packaging method includes the following steps:

S310: providing at least one semiconductor device and a carrier substrate, further forming a plurality of first alignment soldering portions in addition to the connection terminals on the active surface of the semiconductor device, and the plurality of first alignment soldering portions and each of the plurality of first alignment soldering portions on the carrier substrate A plurality of corresponding second alignment soldering portions are formed.

In some embodiments, the semiconductor device is plural. By way of example, the plurality of semiconductor devices may be at least partially different from each other in function, dimension, or shape, or may be the same as each other. According to specific process conditions or actual needs (for example, the dimensional shape of the carrier substrate and the semiconductor device, the arrangement interval or packaging dimensional shape of the semiconductor device, the manufacturing process norm, the functional design of the semiconductor assembly, etc.) of the semiconductor device It should be understood that the type and specific quantity may be appropriately selected, and the present application is not particularly limited thereto.

In some embodiments, the carrier substrate is a glass carrier substrate, a ceramic carrier substrate, a metal carrier substrate, an organic polymer material carrier substrate or a silicon wafer, or a combination of the two, or even two or more types of carrier substrates.

In some embodiments, one of the first alignment soldering unit and the second alignment soldering unit is an alignment solder bump, and the other is an alignment pad corresponding to the alignment solder bump. In some other embodiments, both the first alignment soldering part and the second soldering part are aligned solder bumps, and the melting points of the two soldering parts may be the same or different. As an example, the alignment solder bump is a semiconductor device (eg, a wafer) using a bump manufacturing process known in the art (eg, electroplating method, ball attach method, stencil printing method, evaporation / sputtering method, etc.) Alternatively, it may be fabricated in advance on a carrier substrate. For example, the alignment pad may be prepared in advance on a semiconductor device or a carrier substrate using a deposition (eg, metal layer)-photoetching-etching process. It should be understood that the first alignment soldering portion and the second alignment soldering portion may adopt any other soldering structure or configuration, as long as they can be soldered to each other for alignment purposes.

In some embodiments, the first alignment soldering part corresponds to the second alignment soldering part in volume, size, geometric shape, component, distribution, position, quantity, etc., so that the semiconductor device is connected to the carrier substrate through soldering to each other. can be precisely aligned to the corresponding target position in

The first alignment soldering unit and/or the second alignment soldering unit are performed according to specific process conditions or actual demands (eg, the size shape of the carrier substrate and the semiconductor device, the arrangement interval of the semiconductor device, the package size shape, etc.) It should be understood that the specific volume, size, geometric shape, component, distribution, position and quantity of the part may be appropriately selected, and the present application is not particularly limited thereto. For example, for all semiconductor devices, irrespective of whether the function, size, or shape are identical to each other, the first alignment soldering portions may all be formed of substantially the same volume, size, geometry, or component, and may be formed on a carrier substrate. All of the second alignment soldering units are also formed to have substantially the same volume, size, geometric shape or components, thereby reducing the complexity of a subsequent process and increasing packaging efficiency. Also, for example, for semiconductor devices having different functions, sizes or shapes, the first alignment soldering portion and the second alignment soldering portion may be formed in different volumes, sizes, geometries or components, so that different solders after a subsequent soldering process By forming the joint height, a specific function can be implemented or a specific need can be met. In some embodiments, for a plurality of semiconductor devices, after the first alignment soldering portion and/or the second alignment soldering portion subsequently forms an alignment solder joint, the active surfaces of the plurality of semiconductor devices are connected to the carrier substrate and It is installed so that it can be located in the same parallel plane. In some embodiments, for the plurality of semiconductor devices, the passive surfaces of the plurality of semiconductor devices are parallel to the carrier substrate after the first alignment soldering portion and/or the second alignment soldering portion subsequently forming an alignment solder joint. It is installed so that it can be located in the same plane. Also, for example, forming at least three generally regularly distributed first alignment soldering portions for each of the semiconductor elements, such that the active surface of the semiconductor element is a carrier through soldering of the first alignment soldering portions and the second soldering portions. It can be made to remain rigid and stable in a plane generally parallel to the substrate. Also, for example, in each of the semiconductor devices, the first alignment soldering portion may be distributed and formed at an edge sufficiently far from the connection terminal so as not to affect subsequent processes and product applications.

In some embodiments, the connector is an interconnect bump as shown in FIG. 4A . As an example, the interconnect bump may be prefabricated on an interconnect pad on a semiconductor device using a bump fabrication process known in the art (eg, electroplating, ball attach, stencil printing, evaporation/sputtering, etc.). can For example, the interconnect bumps may be in the form of conductive pillars. As a specific embodiment, in a direction perpendicular to the active surface (or carrier substrate) of the semiconductor device, the height of the interconnection bump is sufficiently smaller than the sum of the heights of the first alignment soldering portion and the second alignment soldering portion, and The height of the alignment solder joint formed after the subsequent soldering of the first alignment soldering part and the second alignment soldering part is higher than the height of the interconnection bump, so that the subsequent soldering of the first alignment soldering part and the second alignment soldering part is not affected or , or during subsequent soldering of the first alignment soldering unit and the second alignment soldering unit, the interconnection bump is prevented from being damaged by being pressed against the carrier substrate.

In an alternative embodiment, as shown in Fig. 5a, the connecting terminal is an interconnection pad.

S320: disposing the at least one semiconductor device on the carrier substrate such that the plurality of first alignment soldering portions are generally aligned with the plurality of second alignment soldering portions.

In some embodiments, the "generally aligned" includes a state in which the first alignment soldering portion and the second alignment soldering portion respectively contact each other, provided that they are not precisely aligned in a direction perpendicular to the passive surface. "Alignment" in the text generally means that the centers of the first alignment soldering portion and the second alignment soldering portion are aligned in a direction perpendicular to the passive surface. It should be explained, that the first alignment soldering part and the second alignment soldering part are "generally aligned" according to the minimum surface energy principle of the alignment solder joint in a molten or partially molten state during the soldering process as shown in the text below. It indicates the presence of contact between at least the first alignment soldering portion and the second alignment soldering portion to the extent of self-aligning. Accordingly, "generally aligned" includes states that are not precisely aligned, but at least in physical contact, but does not exclude precisely aligned states as well.

It should be understood that when the semiconductor device is placed on the carrier substrate in step S320, the active surface of the semiconductor device faces the carrier substrate (ie, the surface on which the first alignment soldering portion is formed), and the passive surface of the semiconductor device faces the carrier substrate away from the carrier substrate. All.

S330: Soldering the plurality of first alignment soldering parts and the plurality of second alignment soldering parts to form a plurality of alignment solder joints, thereby accurately aligning the at least one semiconductor device and fixing it to the carrier substrate.

It should be noted that "correctly align" refers to a state in which a deviation between an actual position and a target position of the semiconductor device on the carrier substrate is within an acceptable range in the art. It should be understood that the precise alignment is implemented using the principle of minimum surface energy that appears in a molten or partially molten state during a soldering process of a solder joint formed by soldering the first alignment soldering part and the second alignment soldering part. Specifically, when the first alignment soldering unit and the second alignment soldering unit contact each other but are not accurately aligned in a direction perpendicular to the active surface of the semiconductor device or the carrier substrate, in the soldering process, the first alignment soldering unit and the first alignment soldering unit Among the two alignment soldering parts, one side as the alignment solder bump is melted or partially melted to infiltrate the other side as the alignment pad or other alignment solder bump, or both the first alignment soldering unit and the second alignment soldering unit are melted as alignment solder bumps or partially molten to form an alignment solder joint in a molten or partially molten state, wherein, according to the minimum surface energy principle, the alignment solder joint in a molten or partially molten state is aligned with the first alignment soldering portion and the second alignment soldering portion By deforming and moving to approach the state, it is possible to precisely align a semiconductor device, which is lighter than the carrier substrate, at a target position on the carrier substrate.

After soldering the first alignment soldering part and the second alignment soldering part, due to the height of the alignment solder joint itself formed thereby (in the direction perpendicular to the active surface of the semiconductor device or the carrier substrate), the It should be understood that the active surface and the carrier substrate are spaced apart from each other to form a space therebetween.

In some embodiments, the alignment solder bump is made of solder, and the soldering may adopt a soldering method that melts various solders known in the art, such as reflow soldering, laser soldering, high-frequency soldering, infrared soldering, etc. including, but not limited to.

In some embodiments, after step S330, the semiconductor device and the carrier substrate are entirely turned over so that the carrier substrate is on top of the at least one semiconductor device, and then the alignment solder joint is melted or partially melted and then the alignment The method further includes step S331 of lowering the temperature so that the solder joint is solidified. At this time, it should be understood that the molten or partially melted alignment solder joint is appropriately stretched due to the weight of the semiconductor device, and thus the self-alignment precision may be further improved. It should be noted that, due to the surface energy of the alignment solder joint in a molten state or a partially molten state, the semiconductor device does not come off from the carrier substrate due to its own weight. As an alternative embodiment, in step S310, the plurality of first alignment soldering portions and/or second alignment soldering portions are coated with a viscous flux in advance, and in step S330, before performing the soldering, the semiconductor device and the carrier and a step S330' of turning over the substrate as a whole so that the carrier substrate is positioned on top of the at least one semiconductor device. At this time, it should be understood that the alignment solder joint, which is molten or partially melted during the soldering process after being turned over, is appropriately stretched due to the weight of the semiconductor device, and thus self-alignment precision may be further improved. It should be noted that since the viscous flux adhesively connects the semiconductor device to the carrier substrate, there is no risk of the semiconductor device being detached from the carrier substrate due to its own weight after being turned over. It should be understood that, before step S340 below, a step of turning over the semiconductor device and the carrier substrate as a whole is further required.

In some embodiments, when there are a plurality of semiconductor devices, step S330 is performed when the semiconductor device and the carrier substrate are accurately aligned and the alignment solder joint is still in a molten or partially molten state, using a pressing plate to use the plurality of semiconductor devices. and planarizing the passive surfaces of the plurality of semiconductor devices, thereby positioning the passive surfaces of the plurality of semiconductor devices generally in the same plane parallel to the carrier substrate. placing the platen over a surface; pressing the platen against the carrier substrate to position the passive surfaces of the plurality of semiconductor devices in a generally coplanar plane parallel to the carrier substrate; while maintaining the pressurized state, lowering the temperature to substantially solidify the alignment solder joint; and removing the pressure plate. As an alternative embodiment, when there are a plurality of the semiconductor devices, after step S330, the alignment solder joint is melted or partially melted again, and then the passive surfaces of the plurality of semiconductor devices are planarized using a pressure plate, whereby the plurality of semiconductors The method further comprises a step S332 of positioning the passive surface of the device generally in the same plane parallel to the carrier substrate. As an example, S332 may further include: melting or partially melting the alignment solder joint; placing the platen over the passive surfaces of the plurality of semiconductor devices; pressing the platen against the carrier substrate to position the passive surfaces of the plurality of semiconductor devices in a generally coplanar plane parallel to the carrier substrate; while maintaining the pressure, lowering the temperature to substantially solidify the alignment solder joint; and removing the pressure plate. It can be understood that since the alignment solder joint is usually pressed until solidified and then the platen is removed, the surface energy of the molten solder joint can prevent the semiconductor device from returning to its original height before pressing. There will be.

Accordingly, it is possible to accurately align all the passive surfaces of the semiconductor device to come to the same height. Appropriate pressure is applied to the platen to appropriately deform the alignment solder joints in the molten or partially molten state, thereby moving the platen vertically (relative to the active surface of the semiconductor device or the carrier substrate) appropriately to prevent damage to the semiconductor device. There is a need. For example, by forming a solder trap in advance around the second alignment soldering portion of the carrier substrate, it is possible to prevent the excess molten solder from flowing uncontrollably during the pressing process.

In some embodiments, the planarization treatment with the platen is combined with the soldering treatment or remelting treatment after the inversion. For example, in S330, after executing S330' and then executing S330", or after executing S330 including S330', then executing S332, or after executing S330 including S330", then executing S331, or When S331 is executed, S332 is executed.

S340: Forming a molding body surrounding the semiconductor device by molding a side of the carrier substrate on which the semiconductor device is located.

It should be understood that through the molding, not only the passive surface (ie the opposite side of the active surface) and the side surface of the semiconductor device are wrapped, but also the space between the active surface of the semiconductor device and the carrier substrate is filled and wrapped. do.

In some embodiments, molding is performed using a molding compound of a resin material (eg, an epoxy resin).

In some embodiments, molding may be performed using a molding process such as injection, extrusion, or printing, and an underfill process may be optionally combined.

S350: After removing the carrier substrate, exposing the connection terminal from the molding body.

In some embodiments, the carrier substrate may be removed through processes known in the art, such as exfoliation, etching, ablation, or polishing. For example, when the peeling process is adopted, the solder (ie, to the alignment solder joint) between the carrier substrate and the semiconductor device may be removed to facilitate peeling the carrier substrate from the molding body.

In some embodiments, some or all of the alignment solder joint is further removed when removing the carrier substrate or after removing the carrier substrate. For example, some or all of the alignment solder joint may be removed through a process known in the art, such as desoldering, etching, ablation, or polishing. In some embodiments, some or all of the alignment solder joints are left as part of the final semiconductor assembly (ie, finished packaging) for electrical connections (eg, power and ground), heat dissipation, mechanical structures, and the like.

In some embodiments, when the connection terminal is an interconnect bump, after the carrier substrate is removed, the molding body is thinned (eg, polished, etched or ablated, etc.) to expose the interconnect bump.

In some embodiments, when the connection terminal is an interconnection pad, an opening is formed in the molding body after removing the carrier substrate to expose the interconnection pad. As an example, laser ablation (eg, laser drilling) may be used to form the opening. By way of example, the opening may be formed through machine drilling. As an example, prior to forming the opening, thinning may be performed on the molded body to facilitate opening and/or to meet product design requirements.

S360: A step of sequentially forming an interconnection layer and an external terminal on a surface of the molding body exposed to the connection terminal, and connecting the connection terminal to the external terminal through the interconnection layer.

In some embodiments, the interconnection layer may include a redistribution layer (RDL) and an under bump metal (UBM) sequentially in a direction away from the connection terminal, thereby implementing a conductive connection between the connection terminal and the external terminal. . It should be understood that the interconnection layer further includes an insulating layer for realizing electrical insulation between various conductive paths, and the specific quantity and material of the insulating layer can be appropriately selected according to specific process conditions or needs, so this The application does not specifically limit this.

In some embodiments, the external terminal is a solder ball.

In some embodiments, the external terminal is a pad.

In some embodiments, the packaging method further includes thinning (eg, polishing, etching, ablation, etc.) a side where the molded body and the passive surface of the semiconductor device are located. For example, thinning to the passive surface of the semiconductor device may be performed, or a portion of the passive surface side of the semiconductor device may be included in the thinned portion, thereby further reducing the thickness of the final semiconductor assembly.

In some embodiments, the passive device is further packaged along with the semiconductor device in substantially the same manner as in the above embodiments.

In some embodiments, the packaging method further includes performing cutting after step S360.

It is understood that individual semiconductor assemblies may or may not be cut by performing the cutting process in accordance with the packaging specifications of the semiconductor assembly (including, but not limited to, wafer level packaging, chip level packaging, and system level packaging). shall.

Hereinafter, the packaging method of the present application will be described in more detail by combining exemplary embodiments.

4A to 4G are cross-sectional views schematically illustrating a packaging method according to an exemplary embodiment of the present application.

As shown in FIG. 4A , a plurality of semiconductor devices and a carrier substrate 420 are provided. Among the plurality of semiconductor devices, at least two semiconductor devices 410 and 410 ′ are different from each other, for example, have different sizes and/or functions. In the active surface 411 on each semiconductor element 410, 410', a plurality of interconnection bumps 414 each conductively connected to an interconnection pad (not shown) are distributed and formed in the region except for the edge, A plurality of alignment solder bumps 412 are formed at the edge portions to be spaced apart from the interconnect bumps 414 . For example, the active surfaces 411 of the semiconductor devices 410 and 410' are generally rectangular, and may each form approximately equal alignment solder bumps 412 to each other near the four corners of the rectangle. Alignment solder bumps 412 are greater than interconnect bumps 414 in height along a direction perpendicular to active surface 411 . A plurality of alignment pads 422 corresponding to the alignment solder bumps 412 on each of the semiconductor devices 410 and 410' are formed on one surface of the carrier substrate 420 in the same arrangement (or relative positional relationship). Optionally, in addition to the semiconductor device, it is also possible to provide a passive device with a similar structure. For example, reference numeral 410' shown in FIG. 4 may be replaced with a passive element.

As shown in FIG. 4B , the semiconductor devices 410 and 410 ′ are disposed on the carrier substrate 420 , and the alignment solder bumps 412 are brought into contact with the corresponding alignment pads 422 . At this time, the alignment solder bump 412 is not aligned with the alignment pad 422 (that is, the vertical center line L1 of the alignment solder bump 412 and the vertical center line L2 of the alignment pad 422 do not overlap) .

As shown in FIG. 4C , the alignment solder bumps 412 and the alignment pads 422 are soldered (eg, through reflow soldering) to form an alignment solder joint 413 . During the soldering process, the alignment solder bumps 412 in a molten state may infiltrate the alignment pads, and by performing self-alignment with the alignment pads 422 based on its minimum surface energy principle (ie, alignment solder bumps 412 ). ) overlapping the vertical center line L1 of the alignment pad 422 and the semiconductor devices 410 and 410 ′ may be precisely aligned with the carrier substrate 420 . After soldering is complete, the active surfaces 411 (and interconnect bumps 414) of the semiconductor elements 410 and 410' are spaced apart from the carrier substrate 420 to form a space.

As shown in FIG. 4D , molding is performed on the side to which the semiconductor devices 410 and 410 ′ of the carrier substrate 420 are soldered. Molding body 430 covers all surfaces of semiconductor device 410 , 410 ′, including active surface 411 (and interconnect bump 414 ), passive surfaces and sides. The space below the active surface 411 may employ an underfill process.

As shown in FIG. 4E , the carrier substrate 420 is removed from the molded body 430 and turned over entirely. When the carrier substrate 420 is removed, at least a portion of the alignment solder joint 413 (including the alignment pad 422 ) may be simultaneously removed. After turning over entirely, the side on which the active surface 411 (or interconnecting bumps 414 ) of the molding body 430 reside is thinned until the interconnecting bumps 414 are exposed. It will be appreciated that at least a portion of the remaining alignment solder joint 413 may be further removed through the thinning.

As shown in FIG. 4F , redistribution layer (RDL) traces 442 , UBM 444 , and solder balls 450 are sequentially formed on the surface on which the interconnection bumps 414 of the molding body 430 are exposed. It forms a conductive path from the connecting bump 414 to the corresponding solder ball 450 . In this process, in particular when forming the RDL traces 442 and/or the UBM 444 , a dielectric layer 446 is further formed to implement electrical isolation between the conductive paths.

As shown in FIG. 4G , the other surface of the molding body 430 (ie, the side where the passive surfaces of the semiconductor elements 410 and 410' are located) is thinned, and the semiconductor elements 410 and 410' are thinned. ) remove the part of the passive surface side.

Before, during, or after each step of the packaging method, other processing (eg, additional processing required for heterogeneous integration packaging) may be additionally performed according to actual packaging demand.

Finally, although not shown, the individual semiconductor assembly may be manufactured by performing singulation according to the package standard of the semiconductor assembly.

5A to 5G are cross-sectional views schematically illustrating a packaging method according to another exemplary embodiment of the present application. It should be noted that, in the text below, the same or similar parts to the above-described exemplary embodiment according to FIGS. 4A to 4G have been omitted.

As shown in FIG. 5A , a plurality of semiconductor devices and a carrier substrate 520 are provided. On the active surface 511 on each of the semiconductor devices 510 and 510', a plurality of interconnection pads 514 are distributed in an area excluding an edge, and a plurality of interconnection pads 514 and a plurality of spaced apart from each other at the edge portion of alignment solder bumps 512 are formed. A plurality of alignment pads 522 corresponding to one surface of the carrier substrate 520 are formed.

As shown in FIG. 5B , semiconductor devices 510 and 510 ′ are disposed on a carrier substrate 520 to bring the alignment solder bumps 512 into contact with the corresponding alignment pads 522 . In this case, the alignment solder bumps 512 are not aligned with the alignment pads 522 .

As shown in FIG. 5C, an alignment solder joint 513 is formed by soldering the alignment solder bump 512 and the pad 520, and accordingly, the semiconductor devices 510 and 510' based on the minimum surface energy principle. ) can be precisely aligned with the carrier substrate 520 .

As shown in FIG. 5D, when the solder joint 513 is still in a molten state, the platen P on the passive surface (ie, the opposite side of the active surface 511) of the semiconductor elements 510 and 510'. After arranging, by pressing the pressure plate P (that is, toward the carrier substrate 520) to perform a planarization process, the passive surfaces of the plurality of semiconductor devices 510 and 510 ′ are combined with the carrier substrate 520 . placed in the same parallel plane. Thereafter, while maintaining the pressure, the temperature is lowered to solidify the alignment solder joint 513 and then the pressure plate P is removed.

As shown in FIG. 5E , molding is performed on the side on which the semiconductor elements 510 and 510 ′ of the carrier substrate 520 are disposed, and the semiconductor elements 510 and 510 ′ are formed as a molding body 530 . covers all surfaces of

As shown in FIG. 5F , the carrier substrate 520 is removed from the molded body 530 and turned over entirely. Thereafter, a perforation (eg, laser perforation) is performed on the side where the active surface 511 (or interconnect pad 514 ) of the molding body 530 is located, exposing the interconnect pad 514 . Before perforation, if necessary, thinning may be performed.

5G, by sequentially forming a redistribution layer (RDL) trace 542, UBM 544, and solder ball 550 on the surface where the interconnection pad 514 of the molding body 530 is exposed, It forms a conductive path from the interconnect pad 514 to the corresponding solder ball 550 . In this process, in particular, when forming the RDL traces 542 and/or the UBM 544 , a dielectric layer 546 is further formed to implement electrical isolation between conductive paths.

Finally, although not shown, the individual semiconductor assembly may be manufactured by cutting according to the functional design standard of the semiconductor assembly.

It is apparent that those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the present application. As such, if such changes and modifications of the present application fall within the scope of the claims and equivalent technical solutions of the present application, the description of the present application includes such changes and modifications.

Claims (20)

In the semiconductor packaging method,
S310: Provide at least one semiconductor device and a carrier substrate to further form a plurality of first alignment soldering portions other than a connection terminal on an active surface of the at least one semiconductor device, and the plurality of first alignment soldering portions on the carrier substrate Forming a plurality of second alignment soldering portions respectively corresponding to;
S320: disposing the at least one semiconductor device on the carrier substrate to generally align the plurality of first alignment soldering portions with the plurality of second alignment soldering portions;
S330: forming a plurality of alignment solder joints by soldering the plurality of first alignment soldering portions and the plurality of second alignment soldering portions, thereby accurately aligning and fixing the at least one semiconductor device to the carrier substrate;
S340: forming a molding body surrounding the at least one semiconductor device by performing molding on a side of the carrier substrate on which the at least one semiconductor device is located;
S350: after removing the carrier substrate, exposing the connection terminal from the molding body; and
S360: A semiconductor packaging method comprising the step of sequentially forming an interconnection layer and an external terminal on a surface of the molding body on which the connection terminal is exposed, and connecting the connection terminal to the external terminal through the interconnection layer . According to claim 1,
one of the first alignment soldering part and the second alignment soldering part has a shape of an alignment solder bump, and the other has a shape of an alignment pad corresponding to the alignment solder bump; or both of the plurality of first alignment soldering units and the second alignment soldering units have the form of alignment solder bumps. 3. The method of claim 2,
The alignment solder bump is made of solder, and the soldering is performed through a method of melting the solder. According to claim 1,
and the plurality of first alignment soldering portions are located in a region without the connection terminal on the active surface. According to claim 1,
The step of generally aligning the plurality of first alignment soldering portions and the plurality of second alignment soldering portions may include contacting the plurality of first alignment soldering portions and the plurality of second alignment soldering portions, respectively, with each other, and perpendicular to the active surface. and not correctly aligning in the phosphor direction. 4. The method of claim 3,
In step S310, the plurality of first alignment soldering portions and/or second alignment soldering portions are coated with a viscous flux in advance, and in step S330, before performing the soldering, the at least one semiconductor device and the carrier substrate Including a step S330' of turning over the whole so that the carrier substrate is positioned on the at least one semiconductor device. 4. The method of claim 3,
After step S330, the at least one semiconductor device and the carrier substrate are turned over so that the carrier substrate is on top of the at least one semiconductor device, and then the plurality of alignment solder joints are melted or partially melted. Further comprising the step S331 of lowering and solidifying, the semiconductor packaging method. 4. The method of claim 3,
When there are a plurality of the at least one semiconductor device, in step S330, when the plurality of semiconductor devices and the carrier substrate are accurately aligned and the plurality of alignment solder joints are still in a molten or partially molten state, the planarizing the passive surfaces of the plurality of semiconductor devices, thereby placing the passive surfaces of the plurality of semiconductor devices in a generally coplanar plane parallel to the carrier substrate, and removing the platen after the alignment solder joint is generally solidified; S330", the semiconductor packaging method. 4. The method of claim 3,
When there are a plurality of the at least one semiconductor device, the semiconductor packaging method is performed after step S330 by melting or partially melting the alignment solder joint again, and then using a platen to planarize the passive surfaces of the plurality of semiconductor devices. , positioning the passive surfaces of the plurality of semiconductor devices generally in the same plane parallel to the carrier substrate, and removing the platen after the alignment solder joint is generally solidified (S332). 4. The method of claim 3,
A semiconductor packaging method of forming solder traps in advance, respectively, around the plurality of second alignment soldering portions of the carrier substrate. According to claim 1,
The connection terminal is an interconnection bump formed on an interconnection pad, and in a direction perpendicular to the active surface, the sum of the heights of the first alignment soldering portion and the second alignment soldering portion is equal to the height of the alignment soldering joint. A method of packaging semiconductors, large enough to be greater than the height of the interconnect bumps. 12. The method of claim 11,
and exposing the connection terminals from the molding body includes exposing the interconnect bumps by thinning the molding body. According to claim 1,
wherein the connection terminal is an interconnect pad, and exposing the connection terminal from the molding includes exposing the interconnect pad by forming an opening in the molding body. The method of claim 1,
The method of claim 1, further comprising the step of performing thinning on the side of the molded body on which the passive surface is located. According to claim 1,
After forming the interconnection layer and the external terminal, the method further comprising the step of performing cutting. According to claim 1,
When removing the carrier substrate or after removing the carrier substrate, the alignment solder joint is left as a minimal part to be used for at least one of electrical connection, heat dissipation, and mechanical structure of a semiconductor assembly manufactured through the semiconductor packaging method. , semiconductor packaging methods. According to claim 1,
and also removing at least some of the alignment solder joints when removing the carrier substrate or after removing the carrier substrate. According to claim 1,
The interconnection layer includes a redistribution layer and an under-bump metal layer sequentially in a direction away from the connection terminal. A semiconductor assembly comprising:
A semiconductor assembly packaged via the semiconductor packaging method according to claim 1 . In an electronic device,
An electronic device comprising the semiconductor assembly according to claim 19 .

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