TWM507066U - Chip package structure - Google Patents

Description

Chip package structure

The present invention relates to a semiconductor package structure, and more particularly to a chip package structure for reducing the use of packaged plastics.

With the development of portable and wearable electronic products, it has become a trend to develop products with high efficiency, small size, high speed, high quality and versatility. In order to make the size of consumer electronic products toward miniaturization, the Wafer Level Chip Scale Package (WLCSP) process is a technical method often used in chip packaging. The chip size (CSP) package uses the Solder Bump to directly pull out the circuit without using conventional wire bonding. In addition to reducing the line resistance, it can effectively reduce parasitic inductance and increase the operating frequency of the product. In addition, the wafer area is close to the package size, and the power density can be optimized.

In addition, in a conventional packaging process, a molding compound is usually used to encapsulate the wafer to form a plastic-clad layer covering the wafer. In addition to providing wafer support strength, the plastic seal layer prevents the wafer from being damaged during transportation or during the preparation process, and also protects the wafer from moisture intrusion. However, while the plastic seal protects the wafer, it can pollute the environment.

The present embodiment is to provide a chip package structure in which a wafer is packaged by a conductive frame. The conductive frame still provides support strength and protection to the wafer, thus reducing the use of the molding compound. In addition, by changing the cutting position, a chip package structure that can be applied in different circuits can be formed according to different circuits.

One embodiment of the present invention provides a chip package structure for mounting on a circuit board. The chip package structure includes a conductive frame, an insulating paste, a first wafer, and a first Two wafers. The conductive frame has a bottom portion and a first partition plate, and the bottom portion includes a first conductive portion and a second conductive portion. And the first partition plate protrudes from the second conductive portion. The insulating colloid is disposed between the first conductive portion and the second conductive portion. The first wafer is disposed on the first conductive portion, wherein the drain of the first wafer is electrically connected to the first conductive portion. The second wafer is disposed on the second conductive portion, wherein the drain of the second wafer is electrically connected to the second conductive portion. When the chip package structure is disposed on the circuit board, the source of the first wafer is electrically connected to the drain of the second wafer via the circuit board, the first spacer and the second conductive portion.

Another embodiment of the present invention provides a chip package structure including a control wafer in addition to the above-described conductive frame, insulating paste, first wafer and second wafer. The control wafer is disposed on the first conductive portion, and the control wafer is electrically insulated from the first conductive portion. When the chip package structure is disposed on the circuit board, the source of the first wafer is electrically connected to the drain of the second wafer via the circuit board, the first spacer and the second conductive portion.

In the manufacturing method of the chip package structure provided by the present embodiment, the use of the conductive frame instead of the molding compound to package the wafer can reduce the use of the molding compound while avoiding environmental pollution as much as possible. In addition, when the conductive frame is cut to form a plurality of wafer package structures, different package structures can be formed by changing the position of the cut.

In order to further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings are only for reference and description, and are not intended to limit the creation.

S1‧‧‧Semiconductor components

10, 10a, 10b‧‧‧ active surface

101‧‧‧ gate

102‧‧‧ source

11, 11a, 11b‧‧‧ back

110, 110a, 110b‧‧‧ bungee

103,104‧‧‧Bottom bump metal pad

105, 105a, 105b, 105c, 105d‧‧‧ gate pads

106, 106a, 106b, 106c, 106d‧‧‧ source pad

30‧‧‧ solder pads

F1, F2, F3, F4‧‧‧ conductive frame

20‧‧‧floor

201‧‧‧ bearing surface

202‧‧‧ bottom

200‧‧‧Receiving area

21‧‧‧ partition board

210, 210a, 210b‧‧‧ end faces

22, 22a, 22b, 23, 32a~32d‧‧‧ conductive layer

3‧‧‧Joint adhesive

203, 203b, 303b, 403b‧‧‧ first cutting slot

204, 304b, 404‧‧‧second cutting groove

C1, C1’‧‧‧ first wafer

C2, C2'‧‧‧ second chip

C3, C3’‧‧‧ third chip

C4‧‧‧fourth wafer

P1, P2, P3, P4, P5, P6‧‧‧ chip package structure

F1’‧‧‧ Conductor

20’‧‧‧ bottom

4‧‧‧Insulating adhesive

5, 5'‧‧‧ boards

203a, 303a, 304a, 403a‧‧‧ cutting marks

6‧‧‧Insulation pattern

6'‧‧‧Insulating colloid

L, L’‧‧‧ cutting line

L1‧‧‧ first cutting line

L2‧‧‧second cutting line

F2’‧‧‧First Conductor

21a‧‧‧First partition

21b‧‧‧Second divider

20a, 40a‧‧‧ first conductive part

20b, 40b‧‧‧Second Conductive Section

51‧‧‧Voltage input pad

52‧‧‧High side gate pads

53‧‧‧Switch pads

54‧‧‧Low side gate pads

55‧‧‧Grounding pads

30a~30d‧‧‧Electrical Department

R0‧‧‧ control element

R1‧‧‧ control chip

S10~S12, S20~S22, S22', S220~S222‧‧‧ process steps

1 is a flow chart of a method of fabricating a chip package structure of an embodiment of the present invention.

2 is a partial cross-sectional view showing the wafer package structure of the present embodiment in the step of FIG. 1.

3 is a partial cross-sectional view showing the wafer package structure of the present embodiment in the step of FIG. 1.

4A is a partial top plan view showing the conductive frame of the present embodiment.

Fig. 4B is a schematic cross-sectional view taken along line H-H of Fig. 4A.

4C is a partial cross-sectional view showing a conductive frame of another embodiment of the present invention.

FIG. 5A is a partial top plan view showing the wafer package structure of the present embodiment in the step of FIG. 1. FIG.

Fig. 5B is a schematic cross-sectional view taken along line I-I of Fig. 5A.

5C is a partial cross-sectional view showing the wafer package structure of another embodiment of the present invention in the step of FIG. 1.

FIG. 6A is a partial bottom view showing the chip package structure of the present embodiment in a step.

Fig. 6B is a schematic cross-sectional view taken along line J-J of Fig. 6A.

FIG. 7 is a partial cross-sectional view showing the wafer package structure of the present embodiment assembled on a circuit board.

FIG. 8 is a flow chart showing a method of fabricating a chip package structure of another embodiment of the present invention.

FIG. 9A is a partial bottom view showing the wafer package structure of another embodiment of the present invention in the step of FIG.

Fig. 9B is a schematic cross-sectional view taken along line I'-I' of Fig. 9A.

FIG. 10A is a partial bottom view showing the wafer package structure of another embodiment of the present invention in performing the steps of FIG. 8. FIG.

Fig. 10B is a schematic cross-sectional view taken along line J'-J' of Fig. 10A.

FIG. 11 is a partial cross-sectional view showing the wafer package structure of another embodiment of the present invention assembled on a circuit board.

Fig. 12A is a view showing the application of the wafer package structure of another embodiment of the present invention to an electric circuit.

Figure 12B shows a top plan view of a package structure of another embodiment of the present invention.

Figure 13A shows a schematic diagram of a wafer package structure of another embodiment of the present invention applied to an electrical circuit.

Figure 13B is a top plan view showing a wafer package structure of another embodiment of the present invention.

Fig. 14A is a view showing the application of the wafer package structure of another embodiment of the present invention to an electric circuit.

14B is a top plan view showing a wafer package structure of another embodiment of the present invention.

Figure 15A shows a partial bottom view of the wafer package structure of another embodiment of the present invention in the steps of Figure 8.

Figure 15B is a partial bottom plan view showing the wafer package structure of another embodiment of the present invention in the step of Figure 8.

Figure 16A shows a bottom view of another wafer package structure of the present creative embodiment.

Figure 16B is a diagram showing the application of the wafer package structure of another embodiment of the present invention to an electric circuit.

FIG. 17A is a partial bottom view showing the wafer package structure of still another embodiment of the present invention at step S220 of FIG. 8.

FIG. 17B is a partial bottom view showing the wafer package structure of still another embodiment of the present invention at step S222 of FIG. 8.

Figure 18 is a bottom plan view showing a wafer package structure of still another embodiment of the present invention.

Please refer to FIG. 1, which shows a flow chart of a method of fabricating a chip package structure according to an embodiment of the present invention. The method of fabricating the chip package structure provided by the present embodiment can be applied to packaging the same or different kinds of wafers. The aforementioned wafer is, for example, a power transistor, an integrated circuit element or a diode or the like. The power transistor is, for example, a vertical power transistor, an insulated gate bipolar transistor (IGBT), or a bottom-source lateral diffusion MOSFET.

In step S10, a wafer is provided in which the wafer has a plurality of semiconductor elements. The material constituting the wafer is usually germanium, but may be other semiconductor materials such as gallium arsenide, gallium nitride (GaN) or tantalum carbide (SiC). In the present creative embodiment, the original thickness of the wafer is approximately 350 to 680 μm. In the present creative embodiment, the wafer has completed the fabrication of the component and includes a plurality of semiconductor components.

In step S11, a wiring layer is formed on each of the semiconductor elements. The aforementioned circuit layer may include an under bump metallization (UBM) to And a plurality of pads respectively formed on the bottom bump metal pads. In another embodiment, the circuit layer may also be a line redistribution layer (RDL). In step S12, a cutting step is performed on the wafer to form a plurality of wafers separated from each other.

In step S20, a conductive frame is provided, and the conductive frame includes a bottom plate and a plurality of partition plates, wherein the bottom plate has a bearing surface and a bottom surface opposite to the bearing surface, and the plurality of partition plates are disposed on the bearing Face and define multiple accommodating areas. The detailed structure of the conductive frame will be described in detail later.

In step S21, a plurality of wafers are respectively fixed in a plurality of accommodating regions, and a back surface of each of the wafers is connected to the bearing surface. Finally, in step S22, the conductive frame is cut to form a plurality of wafer package structures separated from each other. The chip package structure formed by the above process has a conductive frame formed by cutting a conductive frame.

Details of the various steps in Figure 1 will be further illustrated by way of example below. Referring to FIG. 2 and FIG. 3, a cross-sectional view of the chip package structure of the present embodiment is shown in the step of FIG. In the present embodiment, only a schematic cross-sectional view of two of the semiconductor elements S1 of the wafer is shown. The semiconductor component S1 may be a vertical MOS field effect transistor, a control wafer or a diode. In this embodiment, the semiconductor component is a vertical MOS field effect transistor.

Since the wafer has been previously ground and completed, the active surface 10 of each semiconductor element S1 has a patterned protective layer (not shown), a gate 101 and a source 102, and the back surface 11 of the semiconductor element S1. A back electrode layer has been formed for use as the drain 110.

Referring to FIG. 2, in the embodiment, the step of forming a wiring layer on each of the semiconductor elements S1 includes forming a plurality of bottom bump metal pads 103 and 104 on the gate 101 and the source 102, respectively. A plurality of pads are formed on the bottom bump metal pads 103, 104.

The manner of forming the bottom bump metal pads 103, 104 can be utilized, such as electroless plating, sputtering or vapor deposition. In an embodiment, the material constituting the bottom bump metal pads 103, 104 may be selected from one of nickel gold (NiAu) or titanium copper (TiCu). and Moreover, the bottom bump metal pads 103, 104 may be alloyed or have a laminated structure.

Next, a plurality of pads are formed on the plurality of bottom bump metal pads 103, 104, respectively, as contacts for connecting external lines. In this embodiment, one of the pads is a gate pad 105 and the other pad is a source pad 106. The technical means for forming the pad are, for example, forming solder bumps or performing a ball placement process. Alternatively, the aforementioned pad may be formed by a copper bump method, a gold bump method, or an electroplating method.

In other embodiments, if the semiconductor device S1 is subsequently soldered to the circuit board, and the corresponding electrical contacts on the circuit board are pre-formed with sufficient solder and appropriate flux, and the pads and the electrical contacts The step of forming the plurality of pads 105, 106 on the bottom bump metal pads 103, 104 may be omitted if the alignment is not too precise. Next, as described in step S12, a cutting step is performed on the wafer to form a plurality of wafers C1 separated from each other, as shown in FIG.

Referring to FIG. 1, next, in step S20, a conductive frame is provided. Please refer to FIG. 4A and FIG. 4B , wherein FIG. 4A is a partial top view of the conductive frame of the present embodiment, and FIG. 4B is a cross-sectional view taken along line H-H of FIG. 4A .

The material constituting the conductive frame F1 may be copper, iron, nickel or an alloy thereof. In the present embodiment, the material constituting the conductive frame F1 is a copper alloy, and the thickness of the conductive frame F1 is 25 to 500 μm. In addition, the conductive frame F1 can be fabricated by techniques such as etching, stamping, or stamping. In one embodiment, when the material of the conductive frame F1 is copper or an alloy thereof, the outer surface of the conductive frame F1 may be plated with nickel or other metal materials or plated with a non-metal material to avoid oxidation of the copper and affect the appearance.

Referring to FIG. 4A and FIG. 4B together, the conductive frame F1 of the embodiment includes a bottom plate 20 and a plurality of partition plates 21 . As shown in FIG. 4B, the bottom plate 20 has a bearing surface 201 and a bottom surface 202 opposite to the bearing surface 201. In addition, a plurality of partition plates 21 are protruded from the bearing surface 201 of the bottom plate 20, and a plurality of accommodating regions 200 are defined.

In detail, the conductive frame F1 has a frame (not shown), and an accommodating space is defined between the frame and the bottom plate 20, and the plurality of partitioning plates 21 are used to divide the accommodating space into a plurality of interconnectable spaces. The accommodation area 200. In this embodiment, the plurality of partition plates 21 are Arranged in an array on the bottom plate 20, and the longitudinal direction of each of the columns of the partition plates 21 extends along the first direction D1, and the spacing between any two adjacent partition plates 21 arranged along the second direction D2 may be Slightly larger than the width of the wafer.

In addition, a conductive layer 22 may be selectively plated on the end surface 210 of each of the partition plates 21. The material of the conductive layer 22 may be a metal such as nickel, tin, silver or an alloy thereof that is relatively easy to bond with electrical contacts on the circuit board. In addition, referring to FIG. 4C, a partial cross-sectional view of the conductive frame of another embodiment of the present invention is shown. In this embodiment, another layer of conductive layer 23 may also be selectively plated on the wafer carrier surface 201 to match the properties of the wafer bonding material used.

Next, the conductive frame shown in FIGS. 4A and 4B will be taken as an example for description. Referring to FIG. 4B, the bottom surface 202 of the bottom plate 20 may be formed with a plurality of first cutting grooves 203 and a plurality of second cutting grooves 204 corresponding to the accommodating area 200, wherein the plurality of first cutting grooves 203 and the plurality of second cutting grooves The 204 are interleaved with each other to form a boundary of a plurality of wafer package structures. The positions of the plurality of first cutting grooves 203 and the plurality of second cutting grooves 204 and the position of the partition plate 21 are shifted.

In an embodiment, the plurality of first cutting grooves 203 are juxtaposed to each other and extend along the first direction D1. In addition, the plurality of second cutting grooves 204 are juxtaposed to each other and extend along the second direction D2. In one embodiment, each of the first cutting grooves 203 and each of the second cutting grooves 204 has a width of about 50 μm. In other embodiments, the aforementioned first cutting groove 203 and second cutting groove 204 may also be omitted.

In another embodiment, the bottom surface 202 of the bottom plate 20 may further include a plurality of cutting marks formed in advance. In one embodiment, the cutting mark is a notch to define the position of the opening pattern in a subsequent cutting step.

Next, please continue to refer to FIGS. 5A to 5B. FIG. 5A is a partial top plan view showing the wafer package structure of the present embodiment in step S21 of FIG. 1. Fig. 5B is a schematic cross-sectional view taken along line I-I of Fig. 5A.

5A shows that a plurality of wafers C1 are respectively fixed in a plurality of accommodating regions 200, wherein the back surface 11 of each of the wafers C1 faces the bearing surface 201. In this embodiment The wafer C1 shown in FIG. 3 will be described as an example.

After the wafer is diced, a plurality of wafers C1 are formed. These wafers C1 are placed in the accommodating area 200 of the conductive frame F1, respectively. In other embodiments, after the plurality of the same or different wafers are cut in advance, the wafers are re-arranged in the accommodating area 200 of the conductive frame F1. These wafers may be the same or different semiconductor components, such as power transistors, integrated circuit components or diodes, and the like. The power transistor is, for example, a vertical power transistor, an insulated gate bipolar transistor (IGBT), or a bottom-source lateral diffusion MOSFET.

That is to say, the wafers are respectively fixed in a plurality of predetermined accommodating regions 200 on the conductive frame F1 according to the needs of the actual application, and will be described in detail later by way of examples.

In this embodiment, each of the wafers C1 is fixed in the corresponding accommodating area 200 by a bonding glue 3, wherein the bonding glue 3 may be a conductive adhesive or an insulating glue, depending on the type of the wafer C1. In this embodiment, the wafer C1 is a vertical MOS field effect transistor, and the bonding glue 3 is a conductive paste, such as a silver paste, a silver paste, a sintered silver, a solder paste, a solder or a copper paste. However, in other embodiments, when the wafer is a control wafer, the bonding glue is an insulating paste. After the bonding paste 3 is formed between the wafer C1 and the carrying surface 201, the bonding paste 3 is cured by a baking or reflow process to fix the wafer C1 to the conductive frame F1. The technical means for forming the bonding glue 3 between the wafer C1 and the carrying surface 201 may be a known technical means such as dispensing or screen coating.

It is to be noted that, after the wafer C1 is fixed on the carrying surface 201 by the bonding adhesive 3, the drain 110 of the wafer C1 can be electrically connected through the bonding adhesive 3 and the bottom plate 20 of the conductive frame F1, thereby being electrically connected to the separation. Board 21. Moreover, when the wafer C1 is assembled on the circuit board, the conductive layer 22 on the end surface 210 of the partitioning plate 21 can serve as the drain pad of the wafer C1. In other embodiments, when the wafer is a control wafer, the bonding glue 3 is an insulating glue, electrically electrically isolating the wafer from the conductive frame F1, wherein the insulating glue may be an insulating high heat-dissipating glue.

Next, referring to FIG. 5C, a partial cross-sectional view of the chip package structure of another embodiment of the present invention is shown in step S21. When the wafer C1 is to be used in a high-voltage operation or a severe environment, the dispenser can be further formed on the periphery of the wafer C1 by using a dispenser. The insulating glue is used to coat the wafer C1 to provide protection to the wafer C1.

Referring to FIG. 6A and FIG. 6B, FIG. 6A is a partial top plan view showing the chip package structure of the present embodiment in step S22, and FIG. 6B is a cross-sectional view taken along line J-J of FIG. 6A.

As shown in FIGS. 6A and 6B, the conductive frame F1 is cut to form a plurality of mutually separated wafer package structures P1. When the cutting step is performed, it is cut by the bottom surface 202 of the conductive frame F1, and can be completed by a mechanical cutter (such as a diamond knife), laser cutting, or by wet etching. In addition, in the cutting step, further comprising, according to the positions of the plurality of first cutting grooves 203 and the plurality of second cutting grooves 204, along the plurality of first cutting lines L1 in the first direction D1 (two in FIG. 6A) And cutting is performed along the plurality of second cutting lines L2 (two shown in FIG. 6A) in the second direction D2.

The chip package structure P1 completed by the above process can reduce the circuit resistance and the parasitic inductance, and the cut conductive frame itself can also provide support and heat dissipation capability to the wafer C1, so that the chip package structure P1 still has a certain mechanical strength.

In addition, referring to FIG. 7, a partial cross-sectional view showing the wafer package structure of the present embodiment assembled on a circuit board is shown.

After the above-described dicing step, the chip package structure P1 includes a conductive frame F1' and a wafer C1 fixed to the conductive frame F1'. In other words, the conductive frame F1 forms the conductive frame F1' of the wafer package structure P1 after the above-described cutting step, and the conductive frame F1' includes the bottom portion 20' (the cut bottom plate 20) and the partitioning plate 21.

The drain 110 of the wafer C1 can be electrically connected to the bottom portion 20' and the partitioning plate 21 by the bonding glue 3. Moreover, since the drain 110 is electrically connected to the drain of the wafer C1, when the wafer C1 is assembled on the circuit board, the conductive layer 22 located at the end surface 210 of the partition 21 can serve as the drain pad of the wafer C1.

That is, by bonding the glue 3 and the partitioning plate 21 of the conductive frame F1, The gate pad 105, the source pad 106 and the drain pad (the conductive layer 22) of the chip package structure P1 are all located on the same side of the chip package structure P1, and are easily assembled on the circuit board 5. Accordingly, when the chip package structure P1 is assembled on the circuit board 5, the active surface 10 of the wafer C1 is disposed toward the circuit board 5, thereby making the gate pad, the source pad and the drain pad of the chip package structure P1. The pads can be soldered to corresponding electrical contacts on the circuit board 5.

In another embodiment of the present invention, different wafer combinations can be utilized with different cutting methods and locations to form different wafer package structures.

Referring to FIG. 8, a flow chart of a method of fabricating a chip package structure according to another embodiment of the present invention is shown. In this embodiment, the steps S10, S11, S12, S20, and S21 are similar to the embodiment of FIG. 1, and are not described in this embodiment.

In this embodiment, the step S22 of cutting the conductive frame further includes: cutting the conductive frame according to the position of the cutting mark to form an opening pattern on the bottom surface of the conductive frame in step S220; Injecting an insulating glue into the opening pattern to bond the conductive frame; and in step S222, cutting the conductive frame according to the positions of the plurality of first cutting grooves and the plurality of second cutting grooves to form mutually separated Multiple chip package structures.

Please refer to FIG. 9A and FIG. 9B. Fig. 9A is a partial bottom plan view showing the wafer package structure of another embodiment of the present invention in step S220, and Fig. 9B is a cross-sectional view taken along line I'-I' of Fig. 9A.

It should be noted that the conductive frame F2 of the embodiment has a plurality of cutting marks 203a, a plurality of first cutting grooves 203b and a plurality of second cutting grooves 204 on the bottom surface 202 of the bottom plate 20. In the present embodiment, the cutting mark 203a is a strip-shaped notch and is juxtaposed with the first cutting groove 203b. Further, the plurality of cutting marks 203a and the plurality of first cutting grooves 203b are alternately arranged. In other embodiments, the cutting mark 203a may also be a letter, a pattern or a number printed on the bottom surface of the conductive frame F1.

Further, in the present embodiment, a first wafer C1' and a second wafer C2 adjacent to each other among a plurality of wafers will be described as an example. In an example, the first wafer C1' and The second wafer C2 is a high side transistor and a low side transistor, respectively, and a gate (not labeled) and a source (not labeled) of the first wafer C1' are formed on the active surface 10a. And the drain (not labeled) is the back surface 11a forming the first wafer C1'. Similarly, the gate (not labeled) and the source (not labeled) of the second wafer C2 are formed on the active surface 10b, and the drain (not labeled) is the back surface 11b forming the second wafer C2.

In addition, a plurality of pads have been formed on the active surface 10a of the first wafer C1', and at least two of the pads are used as the gate pads 105a and the source pads 106a, respectively. Similarly, a plurality of pads have been formed on the active surface 10b of the second wafer C2, wherein at least two of the pads are used as the gate pads 105b and the source pads 106b, respectively.

Similar to the embodiment of FIG. 5B, before the step of cutting the conductive frame F2, the first wafer C1' and the second wafer C2 have been respectively adhered to the two adjacent in the second direction D2 by the bonding glue 3. Within the accommodating area 200, wherein the bonding glue 3 is a conductive paste. At this time, the drain 110a of the first wafer C1' and the drain 110b of the second wafer C2 are electrically connected to each other through the conductive frame F2.

Referring to FIGS. 9A and 9B, when the cutting step is performed, the conductive frame F2 can be cut along the plurality of cutting lines L (one of which is shown in FIG. 9A) in the first direction D1 according to the position of the cutting mark 203a. The opening pattern is formed on the bottom surface 202 of the conductive frame F2. Since the conductive frame F2 is cut, the drain 110a of the first wafer C1' is electrically insulated from the drain 110b of the second wafer C2. In the embodiment, the opening pattern includes a plurality of first slots juxtaposed with the first cutting grooves 203b, and the plurality of first slots are alternately arranged with the plurality of first cutting grooves 203b.

Next, please refer to FIG. 10A and FIG. 10B. FIG. 10A is a partial bottom view showing the wafer package structure of another embodiment of the present invention after performing step S221. Fig. 10B is a schematic cross-sectional view taken along line J'-J' of Fig. 10A.

As shown in FIGS. 10A and 10B, an insulating paste is injected into the opening pattern to form an insulating pattern 6. In detail, the sealing machine may be used to inject the glue in the opening pattern, or the cut-out conductive frame F2 may be partially immersed in the insulating glue to fill the opening pattern with the insulating glue. After injecting the insulating glue, the insulating glue is cured to make the original cut The conductive frame F2 that is worn and separated is again bonded. At this time, the drain of the first wafer C1' and the drain of the second wafer C2 are no longer electrically connected through the conductive frame F2, but are electrically insulated from each other.

Then, according to the positions of the first cutting groove 203b and the second cutting groove 204, the conductive frame F2 is cut along the first cutting line L1 in the first direction D1 and along the second cutting line L2 in the second direction D2. A plurality of wafer package structures P2 separated from each other are formed.

Please refer to Figure 11. FIG. 11 is a partial cross-sectional view showing the wafer package structure of another embodiment of the present invention assembled on a circuit board. The chip package structure P2 of this embodiment can be used for assembly on a circuit board 5' and is suitable for a voltage conversion circuit. The chip package structure P2 includes a first conductive frame F2', an insulating paste 6', a first wafer C1', and a second wafer C2.

In detail, the first conductive frame F2' is formed by the conductive frame F2 through the cutting step, and has a bottom portion and a first partitioning plate 21a, wherein the bottom portion includes a first conductive portion 20a and a second conductive portion 20b, And the first partitioning plate 21a is protruded from the second conductive portion 20b.

The insulating colloid 6' is disposed between the first conductive portion 20a and the second conductive portion 20b to be connected to the first conductive portion 20a and the second conductive portion 20b, and to electrically connect the first conductive portion 20a and the second conductive portion 20b. insulation.

It is to be noted that, after the above-described cutting step and the gelatinization curing step, the bottom plate 20 of the conductive frame F2 is cut to form a bottom portion, and the bottom portion has the first conductive portion 20a and the second conductive portion 20b which are spaced apart from each other. The insulating paste 6' is disposed between the first conductive portion 20a and the second conductive portion 20b, and insulates the first conductive portion 20a from the second conductive portion 20b. In addition, the first partitioning plate 21a is still electrically connected to the second conductive portion 20b.

The first wafer C1' is disposed on the first conductive portion 20a, and the drain 110a of the first wafer C1' is electrically connected to the first conductive portion 20a through the conductive bonding paste 3. Similarly, the second wafer C2 is disposed on the second conductive portion 20b, and the drain 110b of the second wafer C2 is electrically connected to the second conductive portion 20b through the conductive bonding paste 3.

Since the first partitioning plate 21a is electrically connected to the second conductive portion 20b, the first partitioning plate 21a is electrically connected to the drain 110b of the second wafer C2. In addition, the chip package structure P2 of the embodiment further includes a second partition plate 21b. The second partitioning plate 21b is formed on one side of the first conductive frame F2' and electrically connected to the first conductive portion 20a. That is, the first wafer C1' is located in the accommodating area 200 defined by the first partitioning plate 21a and the second partitioning plate 21b.

When the chip package structure P2 is disposed on the circuit board 5' and applied to the voltage conversion circuit, the source pad 106a of the first wafer C1' passes through the circuit board 5', the first partitioning plate 21a and the second conductive portion 20b. Electrically connected to the drain 110b of the second wafer C2.

Referring to FIG. 11 , in detail, the circuit board 5 ′ is provided with a plurality of pads, and at least the voltage input pads 51 , the high side gate pads 52 , the switching pads 53 , and the low side gates are included in the pads 5′. Pad 54 and ground pad 55. When the front surface of the chip package structure P2 (the side opposite to the bottom of the first conductive frame F2') is disposed facing the circuit board 5', the second partition plate 21b is bonded to the voltage input pad 51 through the conductive layer 22b, and The gate pad 105a of a wafer C1' is bonded to the high side gate pad 52. In addition, the source pad 106a of the first wafer C1' and the conductive layer 22a on the first spacer 21a are bonded to the switching pad 53, and the gate pad 105b and the source pad 106b of the second wafer C2 are bonded. It is bonded to the low side gate pad 54 and the ground pad 55, respectively. Accordingly, the chip package structure P2 of the present embodiment can be directly applied to a voltage conversion circuit.

Please refer to FIG. 12A and FIG. 12B. Fig. 12A is a view showing the application of the wafer package structure of another embodiment of the present invention to an electric circuit. Figure 12B is a top plan view showing a wafer package structure of another embodiment of the present invention.

As can be seen from FIGS. 12A and 12B, the respective pads of the chip package structure P2 of FIG. 12B can serve as contacts for external circuits. For example, the VIN pin of the control element R0 is electrically connected to the conductive layer 22b of the second partition plate 21b through a line configuration on the circuit board 5', and the GH pin is electrically connected to the first wafer C1'. The gate pads 105a and the SW pins are electrically connected to the source pads 106a of the first wafer C1' and the conductive layer 22a of the first spacer 21a. The GL pins are electrically connected to the second wafer C2. The gate pad 105b and the GND pin are electrically connected to the source pad 106b of the second wafer C2.

That is to say, the chip package structure fabricated by the method of manufacturing the chip package structure of the present embodiment has established an electrical connection between the wafers by the conductive frame. Therefore, the chip package structure of the present embodiment is actually a semi-finished product of a circuit component, and can be directly applied to a circuit.

Please refer to FIG. 13A and FIG. 13B. Figure 13A shows a schematic diagram of a wafer package structure of another embodiment of the present invention applied to an electrical circuit. Figure 13B is a top plan view showing a wafer package structure of another embodiment of the present invention.

Fig. 13A shows another voltage conversion circuit. Compared to the voltage conversion circuit of FIG. 12A, in the circuit diagram of FIG. 13A, three power transistors are used, one of which is a high-side power transistor (high-side MOSFET) and the other two are low-side power. Low-side MOSFET.

In the present embodiment, the wafer package structure P3 applied to FIG. 13A can be formed by appropriately designing the cutting position. The chip package structure P3 has a first wafer C1' and two second wafers C2', wherein the drains of the two second wafers C2' are electrically connected to the second conductive portion 20b. In the present embodiment, the cutting step of performing the cutting step to form the wafer package structure P3 is the same as that of the previous embodiment.

In addition, the chip package structure may further include a third wafer in addition to the first wafer and the second wafer. In detail, please refer to FIG. 14A and FIG. 14B. Fig. 14A is a view showing the application of the wafer package structure of another embodiment of the present invention to an electric circuit. 14B is a top plan view showing a wafer package structure of another embodiment of the present invention. In the voltage conversion circuit shown in FIG. 14A, in addition to the application of the high side power transistor and the low side power transistor, the low side power transistors are connected in parallel with a diode.

The chip package structure P4 shown in FIG. 14B further includes a third wafer C3 in addition to the first wafer C1' and the second wafer C2', wherein the first wafer C1' is disposed on the first conductive portion 20a, and the second The wafer C2' and the third wafer C3 are disposed on the second conductive portion 20b, wherein the second wafer C2' and the third wafer C3 pass through the second conductive portion 20b. Inter-connected. In this embodiment, the first wafer C1' and the second wafer C2' are both power transistors, and the third wafer C3 is a diode. In addition, the first wafer C1', the second wafer C2' and the third wafer C3 are permeable to the conductive frame and the circuit layer disposed on the circuit board, and are electrically connected according to the circuit diagram shown in FIG. 14A.

As shown in Figs. 14A and 14B, the third wafer C3 has a pad 30, and the source pads 106b of the second wafer C2' are electrically connected to the GND pin of the control element R0. In the present embodiment, the cutting method of performing the cutting step to form the package structure P4 is the same as that of the previous embodiment.

In other embodiments, another wafer package structure can be formed by changing the shape and position of the opening pattern and the position of the cut. Referring to FIG. 15A, a partial bottom view of the chip package structure of another embodiment of the present invention is shown in step S220 of FIG.

Compared with the conductive frame F2 of FIG. 9A, the bottom surface of the conductive frame F3 of FIG. 15A includes a plurality of cuts extending along the second direction D2 in addition to a plurality of cut marks 303a extending along the first direction D1. The symbol 304a is provided, and the plurality of cutting marks 304a are juxtaposed with the plurality of second cutting grooves 304b. That is, the cutting marks 303a and 304a extend along the first direction D1 and the second direction D2, respectively. Further, the cutting mark 304a and the second cutting groove 304b are alternately arranged.

In the present embodiment, the first wafer C1', the second wafer C2, the third wafer C3', and the fourth wafer C4 are collectively packaged for application in another voltage conversion circuit. In the present embodiment, the first wafer C1', the second wafer C2, the third wafer C3', and the fourth wafer C4 are all vertical power transistors.

In the embodiment of FIG. 15A, when the cutting step is performed, the position along the cutting mark 303a in the first direction D1 is along the cutting line L, and in the second direction D2 is performed along the cutting line L' according to the position of the cutting mark 304a. A cutting step to form an opening pattern. The opening pattern formed in this embodiment includes a first slit (not shown) extending in the first direction D1 and a second slit (not shown) extending in the second direction D2.

Referring to FIG. 15A, the first slot and the second slot are staggered with each other, so that the first wafer C1', the second wafer C2, the third wafer C3', and the fourth wafer C4 are electrically connected to each other. edge. Next, as described in step S221 of FIG. 8, an insulating paste is injected into the opening pattern. After the insulating paste is injected, the insulating paste is cured to form the insulating pattern 6, so that the conductive frame F3 which was originally separated by the cut-through is again bonded.

Next, referring to FIG. 15B, a partial bottom view of the wafer package structure of another embodiment of the present invention in step S222 of FIG. 8 is shown. As shown in FIG. 15B, according to the positions of the first cutting groove 303b and the second cutting groove 304b, the conductive frame is cut along the first cutting line L1 in the first direction D1 and along the second cutting line L2 in the second direction D2. The body F3 is formed to form a plurality of wafer package structures P5 separated from each other.

Please refer to FIG. 16A and FIG. 16B. Figure 16A shows a bottom view of another wafer package structure of the presently-created embodiment applied to multi-phase control or full-bridge rectification. Figure 16B is a diagram showing the application of the wafer package structure of another embodiment of the present invention to an electric circuit. After the above-described dicing step and the sizing step, the wafer package structure P5 includes an insulating colloid 6' which is formed by cutting the insulating pattern 6 described above. In the present embodiment, the insulating colloid 6' has a cross shape, thereby dividing the bottom of the conductive frame into a plurality of conductive portions 30a to 30d. The first wafer C1', the second wafer C2, the third wafer C3', and the fourth wafer C4 are respectively disposed on the plurality of conductive portions 30a to 30d.

In addition, the conductive frame has a plurality of partition plates respectively disposed on the conductive portions 30a-30d and electrically connected to the first wafer C1', the second wafer C2, the third wafer C3' and the fourth wafer C4, respectively. pole. The tops of the plurality of partition plates respectively have conductive layers 32a 32d to be electrically connected to the pads on the circuit board.

Referring to FIG. 16B, the chip package structure P5 of the present embodiment can be applied to a full bridge phase shift conversion circuit, wherein the first wafer C1', the second wafer C2, the third wafer C3', and the fourth wafer C4 are permeable to the conductive frame. And the circuit layer that has been configured on the circuit board is electrically connected according to the circuit diagram shown in FIG. 16B. Each of the pads of the chip package structure P5 in Fig. 16A can be used as a contact of an external circuit. In this embodiment, the first wafer C1' and the third wafer C3' are both high-side MOSFETs, and the second wafer C2 and the fourth wafer are both low-side power transistors ( Low-side MOSFET).

Accordingly, the VIN1 pin of the control element R0 can be electrically connected to the conductive layer 32a, and the GH1 pin can be electrically connected to the gate pad 105a of the first wafer C1', and the SW1 pin can be electrically connected to the first chip. The source pad 106a of C1' and the conductive layer 32b, wherein the conductive layer 32b is electrically connected to the drain of the second wafer C2. In addition, the GL1 pin can be electrically connected to the gate pad 105b of the second wafer C2, and the GND pin can be electrically connected to the source pad 106b of the second wafer C2.

Similarly, the gate pads 105c and SW2 of the GH2 pin electrically connected to the third wafer C3' can be electrically connected to the source pad 106c of the third wafer C3' and the conductive layer 32c, wherein the conductive layer 32c is a drain electrically connected to the third wafer C3. In addition, the GL2 pin can be electrically connected to the gate pad 105d of the fourth wafer C4, and the GND pin can be electrically connected to the source pad 106d of the fourth wafer C4.

In another embodiment of the present invention, the control wafer, the high side power transistor, and the low side power transistor in the voltage conversion circuit can be packaged together in a single chip package structure. Please refer to FIG. 17A, FIG. 17B and FIG. FIG. 17A is a partial bottom view of the wafer package structure of the embodiment of the present invention in step S220 of FIG. 8. FIG. 17B is a partial bottom view of the chip package structure of the embodiment of the present invention at step S222 of FIG. Figure 18 is a bottom plan view showing a wafer package structure of still another embodiment of the present invention.

Referring to FIG. 17A, the control wafer R1 and the first wafer C1' are respectively disposed in two accommodating regions adjacent to each other in the first direction D1, and the second wafer C2 is placed on the side of the control wafer R1 and the first wafer C1'. In the two housing areas. Further, it is to be noted that the control wafer R1 is fixed to the conductive frame F4 by an insulating bonding glue to be electrically insulated from the drain of the first wafer C1'.

As shown in FIG. 17A, when step S220 is performed, a cutting step is performed along the dicing line L according to the dicing mark 403a in the first direction D1 to electrically isolate the drains of the first wafer C1' and the second wafer C2, and form Opening pattern. Subsequently, in step S221, an insulating paste is injected into the opening pattern to bond the conductive frame, wherein the insulating paste is cured to form the insulating pattern 6.

Thereafter, referring to FIG. 17B, when step S222 is performed, the conductive frame F4 is cut along the first cutting line L1 according to the position of the first cutting groove 403b in the first direction D1, and according to the second cutting groove 404 in the second direction D2. The position cuts the conductive frame F4 along the second cutting line L2 to form a plurality of mutually separated wafer package structures P6.

Referring to Fig. 18, the chip package structure P6 includes a conductive frame, a control wafer R1, a first wafer C1' and a second wafer C2.

The conductive frame includes a bottom portion and at least one partition plate (four shown in FIG. 18), wherein the bottom portion has a first conductive portion 40a and a second conductive portion 40b which are disposed apart from each other. The control wafer R1 and the first wafer C1' are disposed on the first conductive portion 40a, and the control wafer R1 is electrically insulated from the first conductive portion 40a. The second wafer C2 is disposed on the second conductive portion 40b.

The control chip R1 can be electrically connected to the control ends of the first wafer C1' and the second wafer C2 by a conductive frame and a wiring layer disposed on the circuit board. In this embodiment, the control wafer R1 is vertically adjacent to the first wafer C1' but placed in a different accommodating area, and the second wafer C2' is correspondingly placed in the two accommodating areas.

In addition, an insulating colloid 6' is further disposed between the first conductive portion 40a and the second conductive portion 40b to electrically insulate the first conductive portion 40a from the second conductive portion 40b. When the chip package structure P6 is disposed on the circuit board, the source of the first wafer C1' can be electrically connected to the drain of the second wafer C2 via the circuit board, the partition plate, and the second conductive portion 40b.

[Possible effects of the examples]

In summary, the beneficial effects of the present invention may be that, in the manufacturing method of the chip package structure provided by the present embodiment, the plurality of wafers after cutting are placed on the conductive frame, which can reduce the use of the plastic sealant. In this case, the wafer is provided with supporting force and mechanical strength. In addition, in the chip package structure of the present embodiment, the drain of the wafer is electrically connected to the conductive frame, and the source and the gate of the active surface of the wafer are electrically connected to the circuit board. Accordingly, when the wafer is in operation, the heat dissipation of the wafer can be simultaneously performed by the conductive frame and the circuit board, thereby providing a two-way heat dissipation effect.

In addition, when the conductive frame is cut to form a wafer package structure, the position at which the insulating pattern is formed and the position of the dicing can be changed to form different chip package structures to be applied to different circuits. In addition, the chip package structure provided by the present embodiment directly forms a pad directly connected to the circuit board on the electrode, which can reduce parasitic resistance and parasitic inductance. When the chip package structure of the present embodiment is applied to a circuit component, the efficiency of operation of the component can be improved.

The above description is only a preferred and feasible embodiment of the present invention, and thus does not limit the scope of the patent of the present invention. Therefore, any equivalent technical changes made by using the present specification and the contents of the schema are included in the scope of protection of the present creation. .

P1‧‧‧ chip package structure

C1‧‧‧ first chip

10‧‧‧Active face

F1’‧‧‧ Conductor

21‧‧‧ partition board

22‧‧‧ Conductive layer

105‧‧‧Gate pad

106‧‧‧Source pad

110‧‧‧汲polar

3‧‧‧Joint adhesive

20’‧‧‧ bottom

201‧‧‧ bearing surface

202‧‧‧ bottom

5‧‧‧Circuit board

Claims (6)

A chip package structure for mounting on a circuit board, the chip package structure comprising: a conductive frame having a bottom portion and a first partition plate, wherein the bottom portion includes a first conductive portion and a second portion a conductive portion, and the first partitioning plate protrudes from the second conductive portion; an insulating colloid disposed between the first conductive portion and the second conductive portion; a first wafer disposed on The first conductive portion, wherein a drain of the first wafer is electrically connected to the first conductive portion; and a second wafer is disposed on the second conductive portion, and a drain of the second wafer Electrically connecting to the second conductive portion; wherein, when the chip package structure is disposed on the circuit board, a source of the first wafer is via the circuit board, the first partition plate, and The second conductive portion is electrically connected to the drain of the second wafer. The chip package structure of claim 1, further comprising a second spacer on one side of the conductive frame, wherein the second spacer is electrically connected to the first conductive portion, and The first partitioning plate forms a first accommodating area, wherein the insulating colloid is located in the first accommodating area. The chip package structure of claim 1, wherein the first chip package structure further comprises a third wafer, the second wafer and the third wafer are disposed on the second conductive portion, and The second conductive portions are electrically connected to each other. The chip package structure of claim 1, wherein the first wafer and the second wafer are power transistors, and the third wafer is a diode. A chip package structure for mounting on a circuit board, the chip package structure comprising: a conductive frame having a bottom portion and a first partitioning plate, the bottom portion includes a first conductive portion and a second conductive portion, and the first partitioning plate is electrically connected to the second conductive portion; An insulating layer disposed between the first conductive portion and the second conductive portion; a first wafer disposed on the first conductive portion, wherein a drain of the first wafer is electrically connected to the a first conductive portion; a control wafer disposed on the first conductive portion, the control wafer is electrically insulated from the first conductive portion; and a second wafer disposed on the second conductive portion The drain of the second wafer is electrically connected to the second conductive portion; wherein, when the chip package structure is disposed on the circuit board, the source of the first wafer is via the circuit board, The first partitioning plate and the second conductive portion are electrically connected to the drain of the second wafer. The chip package structure of claim 5, wherein the control wafer is fixed to the first conductive portion by an insulating paste and electrically insulated from the first conductive portion.