TWI614843B - Chip package structure - Google Patents

Abstract

The invention discloses a chip packaging structure, which can be arranged on a circuit board. The chip package structure includes a conductive frame and a chip. The conductive frame has a bottom and a partition plate protruding from the bottom, and the partition plate is electrically connected to the bottom. The wafer is disposed on the bottom, and the wafer and the partition plate are on the same side of the bottom. The back of the chip has an electrode disposed toward the bottom, and the electrode is electrically connected to the bottom. The chip package structure has a gap between the partition plate and the chip.

Description

Chip package structure [Related applications]

The present invention is a division of Taiwan Patent Application No. 104131105 (application date: September 21, 2015), the entire content of which is incorporated as a part of the patent specification of this invention for reference.

The present invention relates to a semiconductor packaging structure, and more particularly to a chip packaging structure that reduces the use of packaging plastic.

With the development of portable and wearable electronic products, it has become a trend to develop products with high efficiency, small size, high speed, high quality and versatility. In order to miniaturize the external dimensions of consumer electronic products, the wafer level chip scale package (WLCSP) process has become a common technical method used in chip packaging. In the chip size (CSP) package, Solder Bump is used to directly lead out the circuit without using traditional wiring. In addition to reducing line resistance, it can effectively reduce parasitic inductance and increase product operating frequency. In addition, the chip area is close to the package size, and the power density can be optimized.

In addition, in a traditional packaging process, a plastic packaging material is usually used to package the wafer to form a plastic encapsulation layer covering the wafer. In addition to providing the wafer support strength, the plastic encapsulation layer prevents the wafer from being damaged during transportation or during the manufacturing process, and also protects the wafer from moisture intrusion. However, although the plastic sealing layer can protect the wafer, it will pollute the environment.

Embodiments of the present invention provide a chip packaging structure and a manufacturing method thereof, which package a chip by a conductive frame. The conductive frame still provides support strength to the wafer and Protection, thus reducing the use of encapsulants. In addition, in the manufacturing method of the chip packaging structure provided by the embodiment of the present invention, by changing the cutting position, a chip packaging structure applicable to different circuits can be formed according to different circuits.

One embodiment of the present invention provides a chip packaging structure that can be disposed on a circuit board. The chip package structure includes a conductive frame and a chip. The conductive frame has a bottom and a partition plate protruding from the bottom, and the partition plate is electrically connected to the bottom. The wafer is disposed on the bottom, and the wafer and the partition plate are on the same side of the bottom. The back of the chip has an electrode disposed toward the bottom, and the electrode is electrically connected to the bottom. The chip package structure has a gap between the partition plate and the chip.

One embodiment of the present invention provides a chip packaging structure including a conductive frame and a plurality of chips disposed on the conductive frame. The conductive frame has a bottom and a plurality of partition plates. The bottom includes a plurality of conductive portions insulated from each other, and the plurality of partition plates are electrically connected to the plurality of conductive portions, respectively. Each wafer is disposed on a corresponding conductive portion, and a back surface of each wafer has an electrode electrically connected to the corresponding conductive portion, and a back surface of each wafer is disposed toward the corresponding conductive portion. The chip package structure has a plurality of gaps respectively located between the partition plate and the wafer.

One embodiment of the present invention provides a method for manufacturing a chip package structure, including the following steps. A conductive frame is provided. The conductive frame includes a bottom plate and a plurality of partition plates. The bottom plate has a bearing surface and a bottom surface opposite to the bearing surface. A plurality of partition plates are disposed on the bearing surface and define a plurality of plates. Accommodation area. Then, a plurality of wafers are respectively fixed in a plurality of accommodating areas, and a back surface of each wafer is connected to a bearing surface. Subsequently, the conductive frame is cut to form a plurality of chip packaging structures separated from each other.

One embodiment of the present invention provides another chip packaging structure for mounting on a circuit board. The chip package structure includes a conductive frame, an insulating gel, a first chip, and a second chip. The conductive frame has a bottom and a first partition plate, and the bottom includes a first conductive portion and a second conductive portion. And the first partition plate protrudes from the second conductive portion. The insulating gel is disposed between the first conductive portion and the second conductive portion. The first chip is disposed on the first conductive portion, and the drain of the first chip is electrically connected to the first conductive portion. The second chip is set at the Two conductive parts, wherein the drain of the second chip is electrically connected to the second conductive part. When the chip package structure is disposed on a circuit board, the source of the first chip is electrically connected to the drain of the second chip via the circuit board, the first separator, and the second conductive portion.

Another embodiment of the present invention provides another chip packaging structure, which includes a control chip in addition to the conductive frame, the insulating gel, the first chip, and the second chip described above. The control chip is disposed on the first conductive portion, and the control chip is electrically insulated from the first conductive portion. When the chip package structure is disposed on a circuit board, the source of the first chip is electrically connected to the drain of the second chip via the circuit board, the first separator, and the second conductive portion.

In the manufacturing method of the chip packaging structure provided by the embodiment of the present invention, the conductive frame is used instead of the plastic sealing material to encapsulate the chip, which can reduce the use of the plastic sealing material and avoid environmental pollution as much as possible. In addition, when the conductive frame is cut to form a plurality of chip packaging structures, different packaging structures can be formed by changing the positions of the cuts.

In order to further understand the features and technical contents of the present invention, please refer to the following detailed description of the present invention and the accompanying drawings, but the drawings are provided for reference and explanation only, and are not intended to limit the present invention.

S1‧‧‧Semiconductor

10, 10a, 10b‧‧‧ Active face

101‧‧‧Gate

102‧‧‧Source

11, 11a, 11b ‧‧‧ back

110, 110a, 110b‧‧‧ Drain

103, 104‧‧‧ bottom bump metal pad

105, 105a, 105b, 105c, 105d‧‧‧Gate pads

106, 106a, 106b, 106c, 106d‧‧‧ source pads

30‧‧‧pad

F1, F2, F3, F4‧‧‧ conductive frame

20‧‧‧ floor

201‧‧‧ bearing surface

202‧‧‧ underside

200‧‧‧accommodation area

21‧‧‧ divider

210, 210a, 210b

22, 22a, 22b, 23, 32a ~ 32d‧‧‧ conductive layer

3‧‧‧Adhesive

203, 203b, 303b, 403b ‧‧‧ the first cutting groove

204, 304b, 404‧‧‧Second cutting groove

C1, C1’‧‧‧ first chip

C2, C2’‧‧‧ second chip

C3, C3 ’‧‧‧ third chip

C4‧‧‧ fourth chip

P1, P2, P3, P4, P5, P6‧‧‧ chip package structure

F1’‧‧‧ conductive frame

20’‧‧‧ bottom

4‧‧‧ insulating glue

5,5’‧‧‧Circuit board

203a, 303a, 304a, 403a‧‧‧cut marks

6‧‧‧ insulation pattern

6’‧‧‧ insulating gel

L, L’ ‧‧‧ cutting line

L1‧‧‧The first cutting line

L2‧‧‧Second cutting line

F2’‧‧‧First conductive frame

21a‧‧‧First divider

21b‧‧‧Second divider

20a, 40a‧‧‧The first conductive part

20b, 40b‧‧‧Second conductive part

51‧‧‧voltage input pad

52‧‧‧High-side gate pad

53‧‧‧Switching pad

54‧‧‧Low-side gate pad

55‧‧‧ grounding pad

30a ~ 30d‧‧‧Conductive part

R0‧‧‧Control element

R1‧‧‧control chip

S10 ~ S12, S20 ~ S22, S22 ’, S220 ~ S222‧‧‧Process steps

FIG. 1 is a flowchart of a method for manufacturing a chip package structure according to an embodiment of the present invention.

FIG. 2 is a schematic partial cross-sectional view of the chip package structure in the step of FIG. 1 according to an embodiment of the present invention.

FIG. 3 is a schematic partial cross-sectional view of the chip package structure in the step of FIG. 1 according to an embodiment of the present invention.

FIG. 4A is a schematic partial plan view of a conductive frame according to an embodiment of the present invention.

FIG. 4B is a schematic cross-sectional view taken along the line H-H in FIG. 4A.

4C is a schematic partial cross-sectional view of a conductive frame according to another embodiment of the present invention.

FIG. 5A is a schematic partial plan view of the chip package structure in the step of FIG. 1 according to an embodiment of the present invention.

FIG. 5B is a schematic cross-sectional view of FIG. 5A along the I-I section line.

FIG. 5C is a schematic partial cross-sectional view of the chip package structure in the step of FIG. 1 according to another embodiment of the present invention.

FIG. 6A is a schematic bottom view of a part of a chip package structure according to an embodiment of the present invention in a step.

Fig. 6B is a schematic cross-sectional view taken along the J-J section line in Fig. 6A.

FIG. 7 is a schematic partial cross-sectional view of a chip package structure assembled on a circuit board according to an embodiment of the present invention.

FIG. 8 shows a flowchart of a method for manufacturing a chip package structure according to another embodiment of the present invention.

FIG. 9A is a schematic partial bottom view of a chip package structure in the step of FIG. 8 according to another embodiment of the present invention.

FIG. 9B is a schematic cross-sectional view taken along the line I'-I 'in FIG. 9A.

FIG. 10A is a schematic partial bottom view of a chip package structure according to another embodiment of the present invention during the step shown in FIG.

FIG. 10B is a schematic cross-sectional view taken along the line J'-J 'in FIG. 10A.

FIG. 11 is a schematic partial cross-sectional view of a chip package structure assembled on a circuit board according to another embodiment of the present invention.

FIG. 12A shows a chip package structure applied to a circuit according to another embodiment of the present invention. intention.

FIG. 12B is a schematic top view of a package structure according to another embodiment of the present invention.

FIG. 13A shows a schematic diagram of a chip package structure applied to a circuit according to another embodiment of the present invention.

13B is a schematic top view of a chip package structure according to another embodiment of the present invention.

FIG. 14A shows a schematic diagram of a chip package structure applied to a circuit according to another embodiment of the present invention.

14B is a schematic top view of a chip package structure according to another embodiment of the present invention.

FIG. 15A is a schematic partial bottom view of a chip package structure according to another embodiment of the present invention at the step of FIG. 8.

FIG. 15B is a schematic partial bottom view of the chip package structure in the step of FIG. 8 according to another embodiment of the present invention.

FIG. 16A is a schematic bottom view of another chip packaging structure according to an embodiment of the present invention.

FIG. 16B shows a schematic diagram of a chip package structure applied to a circuit according to another embodiment of the present invention.

FIG. 17A is a partial bottom view of a chip package structure according to another embodiment of the present invention at step S220 in FIG. 8.

FIG. 17B is a partial bottom view of the chip package structure according to another embodiment of the present invention at step S222 in FIG. 8.

18 is a schematic bottom view of a chip package structure according to another embodiment of the present invention.

Please refer to FIG. 1, which shows a flowchart of a method for manufacturing a chip package structure according to an embodiment of the present invention. The manufacturing method of the chip packaging structure provided by the embodiment of the present invention can be applied to packaging the same or different types of chips. The aforementioned chip is, for example, a power transistor, an integrated circuit element, or a diode. The power transistor is, for example, a vertical power transistor, an insulated gate bipolar transistor (IGBT), or a bottom-source lateral diffusion MOSFET (bottom-source lateral diffusion MOSFET).

In step S10, a wafer is provided, wherein the wafer has a plurality of semiconductor elements. The material of the wafer is usually silicon, but it can also be other semiconductor materials, such as gallium arsenide, gallium nitride (GaN), or silicon carbide (SiC). In the embodiment of the present invention, the original thickness of the wafer is about 350 to 680 μm. In the embodiment of the present invention, the wafer has completed a device manufacturing process and includes a plurality of semiconductor devices.

In step S11, a circuit layer is formed on each semiconductor element. The aforementioned circuit layer may include an under bump metallization (UBM) and a plurality of solder pads respectively formed on the bottom bump metal pad. In another embodiment, the line layer may also be a line redistribution layer (RDL). In step In step S12, a dicing step is performed on the wafer to form a plurality of wafers separated from each other.

In step S20, a conductive frame is provided, and the conductive frame includes a bottom plate and a plurality of partition plates, wherein the bottom plate has a bearing surface and a bottom surface opposite to the bearing surface, and a plurality of partition plates are arranged on the bearing Surface, and define multiple accommodation areas. The detailed structure of the conductive frame will be described in detail later.

In step S21, a plurality of wafers are respectively fixed in a plurality of accommodating areas, and a back surface of each of the wafers is connected to a bearing surface. Finally, in step S22, the conductive frame is cut to form a plurality of chip packaging structures separated from each other. The chip package structure formed by the above process has a conductive frame formed by cutting a conductive frame.

In the following, the details of each step in FIG. 1 will be further explained by examples. Please refer to FIG. 2 and FIG. 3, which are schematic cross-sectional views of the chip package structure in the step of FIG. 1 according to an embodiment of the present invention. In this embodiment, only a schematic cross-sectional view of two semiconductor elements S1 of the wafer is shown. The semiconductor element S1 may be a vertical MOSFET, a control chip, or a diode. In this embodiment, the semiconductor element is a vertical metal-oxide-semiconductor field-effect transistor.

Since the wafer has been polished in advance and the components are manufactured, the active surface 10 of each semiconductor element S1 already has a patterned protective layer (not shown), the gate 101 and the source 102, and the back surface 11 of the semiconductor element S1 A back electrode layer has been formed to serve as the drain 110.

Referring to FIG. 2, in this embodiment, the step of forming a circuit layer on each semiconductor element S1 includes firstly forming a plurality of bottom bump metal pads 103 and 104 on the gate 101 and the source 102 respectively, and then separately A plurality of solder pads are formed on the bottom bump metal pads 103 and 104.

The method of forming the bottom bump metal pads 103 and 104 can be made by using technical means such as electroless plating, sputtering or evaporation. In one embodiment, a material constituting the bottom bump metal pads 103 and 104 may be selected from one of nickel gold (NiAu) or titanium copper (TiCu). In addition, the bottom bump metal pads 103 and 104 may be an alloy or have a laminated structure.

Next, a plurality of solder pads are formed on the plurality of bottom bump metal pads 103 and 104, respectively. Used as a contact point for connecting external lines. In this embodiment, one of the pads is a gate pad 105 and the other pad is a source pad 106. The technical means for forming the solder pads are, for example, forming solder bumps or performing a ball implantation process. In addition, the copper pad bump method, the gold bump method, or the plating method may be used to form the aforementioned pads.

In other embodiments, if the semiconductor component S1 is subsequently soldered to the circuit board circuit, and the corresponding electrical contacts on the circuit board have been previously formed with sufficient solder and appropriate flux, and the solder pads and electrical contacts In the case where the alignment is not required to be too precise, the step of forming a plurality of solder pads 105 and 106 on the bottom bump metal pads 103 and 104 can also be omitted. Next, as described in step S12, a dicing step is performed on the wafer to form a plurality of separated wafers C1, as shown in FIG.

Please refer to FIG. 1. Next, in step S20, a conductive frame is provided. Please refer to FIG. 4A and FIG. 4B, wherein FIG. 4A shows a schematic partial plan view of a conductive frame according to an embodiment of the present invention, and FIG. 4B shows a schematic cross-sectional view taken along the line H-H in FIG. 4A.

The material constituting the conductive frame F1 may be copper, iron, nickel, or an alloy thereof. In this embodiment, the material constituting the conductive frame F1 is a copper alloy, and the thickness of the conductive frame F1 is between 25 and 500 μm. In addition, the conductive frame F1 can be manufactured by a technical means such as etching, stamping, or embossing. In an embodiment, when the material of the conductive frame F1 is copper or an alloy thereof, the outer surface of the conductive frame F1 may be plated with nickel or other metal materials or with a non-metal material to avoid copper oxidation from affecting the appearance.

Please refer to FIG. 4A and FIG. 4B together. The conductive frame F1 of this embodiment includes a bottom plate 20 and a plurality of partition plates 21. As shown in FIG. 4B, the bottom plate 20 has a bearing surface 201 and a bottom surface 202 opposite to the bearing surface 201. In addition, a plurality of partition plates 21 protrude from the bearing surface 201 of the bottom plate 20 and define a plurality of accommodating areas 200.

In detail, the conductive frame F1 has a frame (not shown), an accommodation space is defined between the frame and the bottom plate 20, and a plurality of partition plates 21 are used to divide the accommodation space into a plurality of interconnectable spaces.容 区 200。 Storage area 200. In this embodiment, the plurality of partition plates 21 are distributed in an array on the bottom plate 20, and the long axis direction of each column of partition plates 21 extends along the first direction D1 and is arranged along the second direction D2. Two adjacent dividers 21 The distance between them can be slightly larger than the width of the wafer.

In addition, a conductive layer 22 can be selectively plated on the end surface 210 of each partition plate 21. The material of the conductive layer 22 may be a metal, such as nickel, tin, silver, or an alloy thereof, which is easier to be bonded to the electrical contacts on the circuit board. In addition, please refer to FIG. 4C, which is a schematic partial cross-sectional view of a conductive frame body according to another embodiment of the present invention. In this embodiment, another conductive layer 23 may be selectively plated on the wafer bearing surface 201 to match the properties of the wafer bonding material used.

Next, the conductive frame shown in FIG. 4A and FIG. 4B is used as an example for description. Referring to FIG. 4B, the bottom surface 202 of the bottom plate 20 may correspond to the accommodating area 200, and a plurality of first cutting grooves 203 and a plurality of second cutting grooves 204 are formed in advance, wherein the plurality of first cutting grooves 203 and the plurality of second cutting grooves 204 are staggered with each other to form a boundary of a plurality of chip packaging structures. The positions of the plurality of first cutting grooves 203 and the plurality of second cutting grooves 204 and the position of the partition plate 21 are staggered.

In one embodiment, the plurality of first cutting grooves 203 are juxtaposed with each other and extend along the first direction D1. In addition, the plurality of second cutting grooves 204 are juxtaposed with each other and extend along the second direction D2. In one embodiment, the width of each of the first cutting grooves 203 and each of the second cutting grooves 204 is about 50 μm. In other embodiments, the aforementioned first cutting groove 203 and the second cutting groove 204 may be omitted.

In another embodiment, the bottom surface 202 of the bottom plate 20 may further include a plurality of cutting marks formed in advance. In one embodiment, the cutting mark is a notch, so as to define a position of the opening pattern in a subsequent cutting step.

5A to 5B. FIG. 5A is a schematic partial plan view of the chip package structure according to the embodiment of the present invention in step S21 in FIG. 1. FIG. 5B is a schematic cross-sectional view of FIG. 5A along the I-I section line.

FIG. 5A shows that the plurality of wafers C1 are respectively fixed in the plurality of accommodating areas 200, and the back surface 11 of each of the wafers C1 is disposed facing the bearing surface 201. In this embodiment, the wafer C1 shown in FIG. 3 is taken as an example for description.

After the wafer is diced, a plurality of wafers C1 are formed. These chips C1 will separate It is placed in the accommodating area 200 of the conductive frame F1. In other embodiments, the same or different wafers may be cut in advance, and then the wafers may be re-arranged in the accommodating area 200 of the conductive frame F1. These chips can be the same or different semiconductor components, such as power transistors, integrated circuit components, or diodes. The power transistor is, for example, a vertical power transistor, an insulated gate bipolar transistor (IGBT), or a bottom-source lateral diffusion MOSFET (bottom-source lateral diffusion MOSFET).

That is, these chips will be fixed in a plurality of predetermined accommodating areas 200 on the conductive frame F1 according to the needs of the actual application, which will be described in detail later with examples.

In this embodiment, each wafer C1 is fixed in the corresponding accommodating area 200 by using a bonding adhesive 3. The bonding adhesive 3 may be a conductive adhesive or an insulating adhesive, depending on the type of the wafer C1. In this embodiment, the wafer C1 is a vertical metal-oxide-semiconductor field-effect transistor, and the bonding paste 3 is a conductive paste, such as a silver paste, nano-silver, sintered silver, solder paste, solder, or copper paste. However, in other embodiments, when the wafer is a control wafer, the bonding glue is an insulating glue. After the bonding glue 3 is formed between the wafer C1 and the bearing surface 201, the bonding glue 3 is cured through a baking or reflow process, so that the wafer C1 is fixed on the conductive frame F1. The technical means for forming the bonding adhesive 3 between the wafer C1 and the bearing surface 201 may be known technical means such as dispensing or screen coating.

It should be noted that after the chip C1 is fixed on the bearing surface 201 by the bonding adhesive 3, the drain electrode 110 of the chip C1 can be electrically connected to the bottom plate 20 of the conductive frame F1 through the bonding adhesive 3 so as to be electrically connected to the partition. Plate 21. In addition, when the wafer C1 is assembled on a circuit board, the conductive layer 22 located on the end surface 210 of the partition plate 21 can be used as a drain pad of the wafer C1. In other embodiments, when the wafer is a control wafer, the bonding glue 3 is an insulating glue, which electrically isolates the wafer and the conductive frame F1 from each other, wherein the insulating glue may be an insulating high-heat-dissipating glue.

5C, a schematic partial cross-sectional view of a chip package structure according to another embodiment of the present invention at step S21. When wafer C1 is intended for high-pressure operation or severe In harsh environments, a glue dispenser can be used to form an insulating glue around the wafer C1. The insulating glue is used to cover the wafer C1 to protect the wafer C1.

Please refer to FIG. 6A and FIG. 6B. FIG. 6A is a schematic partial top plan view of the chip packaging structure in step S22 according to an embodiment of the present invention, and FIG. 6B is a schematic cross-sectional view taken along the line J-J in FIG. 6A.

As shown in FIGS. 6A and 6B, the conductive frame F1 is cut to form a plurality of chip packaging structures P1 separated from each other. When the cutting step is performed, the cutting is performed by the bottom surface 202 of the conductive frame F1, and can be completed by a mechanical cutter (such as a diamond cutter), laser cutting, or by wet etching. In addition, the cutting step further includes, according to the positions of the plurality of first cutting grooves 203 and the plurality of second cutting grooves 204, along the plurality of first cutting lines L1 in the first direction D1 (two are shown in FIG. 6A) ), And cutting along a plurality of second cutting lines L2 (two are shown in FIG. 6A) in the second direction D2.

The chip package structure P1 completed by the above process can reduce circuit resistance and parasitic inductance, and the cut conductive frame body can also provide support and heat dissipation for the chip C1, so that the chip package structure P1 still has a certain mechanical strength.

In addition, please refer to FIG. 7, which shows a schematic partial cross-sectional view of a chip package structure assembled on a circuit board according to an embodiment of the present invention.

After the cutting step described above, the chip package structure P1 includes a conductive frame F1 'and a chip C1 fixed on the conductive frame F1'. In other words, the conductive frame F1 is formed into the conductive frame F1 'of the chip package structure P1 after the cutting step described above, and the conductive frame F1' includes a bottom 20 '(the cut bottom plate 20) and a partition plate 21. As shown in FIG. 7, the bottom 20 'of the conductive frame F1' has at least one cutting end surface. The chip package structure P1 has a gap between the partition plate 21 and the chip C1.

The drain electrode 110 of the chip C1 can be electrically connected to the bottom 20 'and the partition plate 21 through the adhesive 3. In addition, since the drain electrode 110 is a drain electrode electrically connected to the chip C1, when the chip C1 is assembled on a circuit board, the conductive layer 22 on the end surface 210 of the partition plate 21 can be used as the drain pad of the chip C1.

That is, by bonding the adhesive 3 and the partition plate 21 of the conductive frame F1, The gate pad 105, the source pad 106, and the drain pad (the conductive layer 22) of the chip package structure P1 are all located on the same side of the chip package structure P1, so as to facilitate assembly on the circuit board 5. According to this, when the chip package structure P1 is assembled on the circuit board 5, the active surface 10 of the chip C1 is disposed toward the circuit board 5, so that the gate pads, source pads, and drain electrodes of the chip package structure P1 The solder pads can be soldered to corresponding electrical contacts on the circuit board 5.

In another embodiment of the present invention, different chip combinations and different cutting methods and positions can be used to form different chip packaging structures.

Referring to FIG. 8, a flowchart of a method for manufacturing a chip package structure according to another embodiment of the present invention is shown. In this embodiment, steps S10, S11, S12, S20, and S21 are similar to the embodiment in FIG. 1, and are not described in this embodiment.

In this embodiment, step S22 ′ of cutting the conductive frame further includes: in step S220, cutting through the conductive frame according to the position of the cutting mark to form an opening pattern on the bottom surface of the conductive frame; in step S221 Injecting an insulating glue into the opening pattern to adhere the conductive frame body; and in step S222, cutting the conductive frame body according to the positions of the plurality of first cutting grooves and the plurality of second cutting grooves to form mutually separated Multiple chip packaging structures.

Please refer to FIGS. 9A and 9B. FIG. 9A is a schematic bottom view of a part of a chip package structure in step S220 according to another embodiment of the present invention, and FIG. 9B is a schematic cross-sectional view taken along a line I'-I 'in FIG. 9A.

It should be noted that the conductive frame F2 of this embodiment has a plurality of cutting marks 203a, a plurality of first cutting grooves 203b, and a plurality of second cutting grooves 204 on the bottom surface 202 of the bottom plate 20. In this embodiment, the cutting mark 203a is a strip-shaped notch, and is parallel to the first cutting groove 203b. The plurality of cutting marks 203a and the plurality of first cutting grooves 203b are alternately arranged. In other embodiments, the cutting mark 203a may also be a text, a pattern, or a number printed on the bottom surface of the conductive frame F1.

In addition, in this embodiment, a first wafer C1 'and a second wafer C2 adjacent to each other among a plurality of wafers are used as an example for description. In one example, the first wafer C1 'and The second wafer C2 is a high-side transistor and a low-side transistor, and the gate (unlabeled) and source (unlabeled) of the first wafer C1 'are formed on the active surface 10a. The drain (not labeled) forms the back surface 11a of the first wafer C1 '. Similarly, the gate (not labeled) and source (not labeled) of the second wafer C2 are formed on the active surface 10b, and the drain (not labeled) is formed on the back surface 11b of the second wafer C2.

In addition, a plurality of bonding pads have been formed on the active surface 10a of the first wafer C1 ', at least two of which are used as the gate bonding pad 105a and the source bonding pad 106a, respectively. Similarly, a plurality of bonding pads have been formed on the active surface 10b of the second wafer C2, at least two of which are used as the gate bonding pad 105b and the source bonding pad 106b, respectively.

Similar to the embodiment of FIG. 5B, before the cutting step is performed on the conductive frame F2, the first wafer C1 'and the second wafer C2 have been fixed to two adjacent ones in the second direction D2 through the bonding glue 3, respectively. Within each accommodating area 200, the bonding adhesive 3 is a conductive adhesive. At this time, the drain electrode 110a of the first chip C1 'and the drain electrode 110b of the second chip C2 are electrically connected to each other through the conductive frame F2.

Please refer to FIGS. 9A and 9B. When the cutting step is performed, the conductive frame F2 can be cut through the multiple cutting lines L (one of which is shown in FIG. 9A) in the first direction D1 according to the position of the cutting mark 203a. To form an opening pattern on the bottom surface 202 of the conductive frame F2. Since the conductive frame F2 is cut, the drain electrode 110a of the first chip C1 'is electrically insulated from the drain electrode 110b of the second chip C2. In this embodiment, the opening pattern includes a plurality of first slots parallel to the first cutting groove 203b, and the plurality of first slots are alternately arranged with the plurality of first cutting grooves 203b.

10A and 10B. FIG. 10A is a schematic partial bottom view of a chip package structure according to another embodiment of the present invention after step S221 is performed. FIG. 10B is a schematic cross-sectional view taken along the line J'-J 'in FIG. 10A.

As shown in FIGS. 10A and 10B, an insulating paste is injected into the opening pattern to form an insulating pattern 6. In detail, a glue sealer can be used to inject glue into the opening pattern, or a part of the cut through conductive frame F2 is immersed in the insulating glue to fill the insulating glue into the opening pattern. After the insulating glue is injected, the insulating glue is cured so that the original The separated conductive frame F2 is adhered again. At this time, the drain of the first chip C1 'and the drain of the second chip C2 are no longer electrically connected through the conductive frame F2, but are electrically insulated from each other.

Next, according to the positions of the first cutting groove 203b and the second cutting groove 204, the conductive frame F2 is cut along the first cutting line L1 in the first direction D1 and along the second cutting line L2 in the second direction D2. A plurality of chip package structures P2 separated from each other are formed.

Please refer to Figure 11. 11 is a schematic partial cross-sectional view of a chip package structure assembled on a circuit board according to another embodiment of the present invention. The chip package structure P2 of this embodiment can be used for assembling on a circuit board 5 ', and is suitable for a voltage conversion circuit. The chip package structure P2 includes a first conductive frame F2 ', an insulating gel 6', a first chip C1 ', and a second chip C2.

In detail, the first conductive frame F2 'is formed by the conductive frame F2 through the above-mentioned cutting step, and has a bottom and a first partition plate 21a, where the bottom includes the first conductive portion 20a and the second conductive portion 20b. In addition, the first partition plate 21a protrudes from the second conductive portion 20b.

An insulating colloid 6 'is provided between the first conductive portion 20a and the second conductive portion 20b to connect the first conductive portion 20a and the second conductive portion 20b, and to make the first conductive portion 20a and the second conductive portion 20b electrically insulation.

It should be noted that after the cutting step and the glue-injection curing step described above, the bottom plate 20 of the conductive frame F2 is cut to form a bottom, and the bottom has a first conductive portion 20a and a second conductive portion 20b spaced from each other. The insulating colloid 6 'is provided between the first conductive portion 20a and the second conductive portion 20b, and insulates the first conductive portion 20a and the second conductive portion 20b from each other. In addition, the first partition plate 21a is still electrically connected to the second conductive portion 20b.

The first wafer C1 'is disposed on the first conductive portion 20a, and the drain electrode 110a of the first wafer C1' is electrically connected to the first conductive portion 20a through the conductive adhesive 3. Similarly, the second wafer C2 is disposed on the second conductive portion 20b, and the drain electrode 110b of the second wafer C2 is electrically connected to the second conductive portion 20b through the conductive adhesive 3.

Since the first partition plate 21a is electrically connected to the second conductive portion 20b, the first partition plate 21a is electrically connected to the drain electrode 110b of the second chip C2. In addition, the chip package structure P2 of this embodiment further includes a second partition plate 21b. The second partition plate 21b is formed on one side of the first conductive frame F2 'and is electrically connected to the first conductive portion 20a. That is, the first wafer C1 'is located in the accommodating area 200 defined by the first partition plate 21a and the second partition plate 21b.

When the chip package structure P2 is disposed on the circuit board 5 'and applied to a voltage conversion circuit, the source pads 106a of the first chip C1' pass through the circuit board 5 ', the first partition plate 21a, and the second conductive portion 20b. It is electrically connected to the drain 110b of the second chip C2.

Please refer to FIG. 11. In detail, a plurality of pads are provided on the circuit board 5 ′. These pads include at least a voltage input pad 51, a high-side gate pad 52, a switching pad 53, and a low-side gate. The contact pad 54 and the ground contact pad 55. When the front side of the chip package structure P2 (the side opposite to the bottom of the first conductive frame F2 ') is disposed facing the circuit board 5', the second partition plate 21b is bonded to the voltage input pad 51 through the conductive layer 22b, and the first The gate pad 105 a of one wafer C1 ′ is bonded to the high-side gate pad 52. In addition, the source pads 106a of the first wafer C1 'and the conductive layer 22a on the first partition plate 21a are bonded to the switching pads 53, while the gate pads 105b and the source pads 106b of the second wafer C2 It is bonded to the low-side gate pad 54 and the ground pad 55, respectively. Accordingly, the chip package structure P2 of the embodiment of the present invention can be directly applied to a voltage conversion circuit.

Please refer to FIG. 12A and FIG. 12B. FIG. 12A is a schematic diagram showing a chip package structure applied to a circuit according to another embodiment of the present invention. FIG. 12B is a schematic top view of a chip package structure according to another embodiment of the present invention.

It can be seen from FIG. 12A and FIG. 12B that each pad of the chip package structure P2 in FIG. 12B can be used as a contact point of an external circuit. For example, the VIN pin of the control element R0 can be electrically connected to the conductive layer 22b of the second partition plate 21b through the wiring configuration on the circuit board 5 ', and the GH pin can be electrically connected to the first chip C1' The gate pad 105a and the SW pin can be electrically connected to the source pad 106a of the first chip C1 'and the conductive layer 22a of the first partition plate 21a, and the GL pin can be electrically connected to the second chip C2. And the GND pin can be electrically connected to the source pad 106b of the second chip C2.

That is, the chip package structure manufactured by applying the method for manufacturing the chip package structure according to the embodiment of the present invention has established the electrical connection between the chips through the conductive frame. Therefore, the chip package structure of the embodiment of the present invention is actually a semi-finished product of a circuit element, and can be directly applied to a circuit.

Please refer to FIGS. 13A and 13B. FIG. 13A shows a schematic diagram of a chip package structure applied to a circuit according to another embodiment of the present invention. 13B is a schematic top view of a chip package structure according to another embodiment of the present invention.

FIG. 13A shows another voltage conversion circuit. Compared to the voltage conversion circuit of FIG. 12A, in the circuit diagram of FIG. 13A, three power transistors are used, one of which is a high-side power transistor (high-side MOSFET) and the other two are low-side power Transistor (low-side MOSFET).

In this embodiment, the chip packaging structure P3 applied in FIG. 13A can be formed by appropriately designing the cutting position. The chip package structure P3 has a first chip C1 'and two second chips C2'. The drains of the two second chips C2 'are both electrically connected to the second conductive portion 20b. In this embodiment, the dicing method for performing the dicing step to form the chip package structure P3 is the same as the previous embodiment.

In addition, the chip package structure may further include a third chip in addition to the first chip and the second chip. For details, please refer to FIGS. 14A and 14B. FIG. 14A shows a schematic diagram of a chip package structure applied to a circuit according to another embodiment of the present invention. 14B is a schematic top view of a chip package structure according to another embodiment of the present invention. In the voltage conversion circuit shown in FIG. 14A, in addition to applying a high-side power transistor and a low-side power transistor, the low-side power transistor is connected in parallel with a diode.

The chip package structure P4 shown in FIG. 14B includes a third chip C3 in addition to the first chip C1 ′ and the second chip C2 ′, wherein the first chip C1 ′ is disposed on the first conductive portion 20a, and the second The wafer C2 'and the third wafer C3 are disposed on the second conductive portion 20b, and the second wafer C2' and the third wafer C3 pass through the second conductive portion 20b. Mutual electrical connection. In this embodiment, the first wafer C1 'and the second wafer C2' are both power transistors, and the third wafer C3 is a diode. In addition, the first chip C1 ', the second chip C2', and the third chip C3 can be electrically connected through the conductive frame and the circuit layer arranged on the circuit board according to the circuit diagram shown in FIG. 14A.

As shown in FIGS. 14A and 14B, the third chip C3 has a bonding pad 30, and the source bonding pad 106b of the second chip C2 'is electrically connected to the GND pin of the control element R0. In this embodiment, the cutting method for performing the cutting step to form the packaging structure P4 is the same as the previous embodiment.

In other embodiments, another chip package structure can be formed by changing the shape and position of the opening pattern and the position of the cut. Referring to FIG. 15A, a schematic bottom view of a part of a chip package structure according to another embodiment of the present invention at step S220 in FIG. 8 is shown.

Compared to the conductive frame F2 of FIG. 9A, the bottom surface of the conductive frame F3 of FIG. 15A includes a plurality of cuts extending along the second direction D2 in addition to a plurality of cut marks 303a extending along the first direction D1. The plurality of cutting marks 304a are aligned with the plurality of second cutting grooves 304b. That is, the cutting marks 303a and 304a extend along the first direction D1 and the second direction D2, respectively. The cutting marks 304a and the second cutting grooves 304b are alternately arranged.

In this embodiment, the first chip C1 ', the second chip C2, the third chip C3', and the fourth chip C4 are commonly packaged for application in another voltage conversion circuit. In this embodiment, the first wafer C1 ', the second wafer C2, the third wafer C3', and the fourth wafer C4 are all vertical power transistors.

In the embodiment of FIG. 15A, when the cutting step is performed, the cutting direction is performed along the cutting line L according to the position of the cutting mark 303a in the first direction D1, and the cutting line L 'is performed according to the position of the cutting mark 304a in the second direction D2. A cutting step to form an opening pattern. The opening pattern formed in this embodiment includes a first slot (not shown) extending along the first direction D1 and a second slot (not shown) extending along the second direction D2.

15A, the first slot and the second slot are staggered with each other, so that the first wafer C1 ', the second wafer C2, the third wafer C3', and the fourth wafer C4 are electrically isolated from each other. edge. Next, as described in step S221 of FIG. 8, an insulating paste is injected into the opening pattern. After the insulating glue is injected, the insulating glue is cured to form an insulating pattern 6, so that the conductive frame F3, which was originally separated by cutting through, is adhered again.

Next, please refer to FIG. 15B, which illustrates a schematic bottom view of a part of the chip package structure in step S222 of FIG. 8 according to another embodiment of the present invention. As shown in FIG. 15B, according to the positions of the first and second cutting grooves 303b and 304b, the conductive frame is cut along the first cutting line L1 in the first direction D1 and along the second cutting line L2 in the second direction D2. Body F3 to form a plurality of chip packaging structures P5 separated from each other.

Please refer to FIGS. 16A and 16B. FIG. 16A shows a schematic bottom view of another chip packaging structure according to an embodiment of the present invention. This architecture is applied to multi-phase control or full-bridge rectification. FIG. 16B shows a schematic diagram of a chip package structure applied to a circuit according to another embodiment of the present invention. After the above-mentioned cutting step and the glue injection curing step, the chip package structure P5 includes an insulating glue body 6 ', which is formed by cutting the aforementioned insulating pattern 6. In this embodiment, the insulating colloid 6 'has a cross shape, so that the bottom of the conductive frame is divided into a plurality of conductive portions 30a-30d. The first wafer C1 ', the second wafer C2, the third wafer C3', and the fourth wafer C4 are respectively disposed on the plurality of conductive portions 30a to 30d.

In addition, the conductive frame has a plurality of partition plates, which are respectively disposed on the conductive portions 30a to 30d, and are electrically connected to the first wafer C1 ', the second wafer C2, the third wafer C3', and the fourth wafer C4, respectively. pole. The tops of the plurality of partition plates have conductive layers 32a to 32d respectively, and are electrically connected to the pads on the circuit board.

Referring to FIG. 16B, the chip package structure P5 of this embodiment can be applied to a full-bridge phase shift conversion circuit, in which the first chip C1 ', the second chip C2, the third chip C3', and the fourth chip C4 can pass through the conductive frame And the circuit layer arranged on the circuit board is electrically connected according to the circuit diagram shown in FIG. 16B. Each pad of the chip package structure P5 in FIG. 16A can be used as a contact of an external circuit. In this embodiment, the first chip C1 ′ and the third chip C3 ′ are both used as high-side power transistors (high-side MOSFET), and the second chip C2 and the fourth chip are used as low-side power transistors ( low-side MOSFET).

According to this, the VIN1 pin of the control element R0 can be electrically connected to the conductive layer 32a, and the GH1 pin can be electrically connected to the gate pad 105a and SW1 pin of the first chip C1 'can be electrically connected to the first chip The source pad 106a of C1 'and the conductive layer 32b, wherein the conductive layer 32b is a drain electrode electrically connected to the second chip C2. In addition, the GL1 pin can be electrically connected to the gate pad 105b of the second chip C2, and the GND pin can be electrically connected to the source pad 106b of the second chip C2.

Similarly, the GH2 pin can be electrically connected to the gate pad 105c of the third chip C3 ', and the SW2 pin can be electrically connected to the source pad 106c and the conductive layer 32c of the third chip C3', wherein the conductive layer 32c is a drain electrode electrically connected to the third chip C3. In addition, the GL2 pin can be electrically connected to the gate pad 105d of the fourth chip C4, and the GND pin can be electrically connected to the source pad 106d of the fourth chip C4.

In another embodiment of the present invention, the control chip, the high-side power transistor, and the low-side power transistor in the voltage conversion circuit may be packaged together in a chip packaging structure. Please refer to FIG. 17A, FIG. 17B and FIG. 18. FIG. 17A is a partial bottom view of a wafer package structure according to another embodiment of the present invention at step S220 in FIG. 8, and FIG. 17B is a partial bottom view of the wafer package structure of another embodiment of the present invention at step S222 in FIG. 18 is a schematic bottom view of a chip package structure according to another embodiment of the present invention.

Referring to FIG. 17A, the control wafer R1 and the first wafer C1 'are respectively disposed in two accommodation areas adjacent to each other in the first direction D1, and the second wafer C2 is placed side by side with the control wafer R1 and the first wafer C1'. In the two accommodation areas. In addition, it is to be noted that the control chip R1 is fixed to the conductive frame F4 through an insulating adhesive to electrically insulate the drain of the first chip C1 '.

As shown in FIG. 17A, when step S220 is performed, the cutting step is performed along the cutting line L according to the cutting mark 403a in the first direction D1 to electrically isolate the drains of the first wafer C1 'and the second wafer C2 and form Opening pattern. Subsequently, in step S221, an insulating paste is injected into the opening pattern to adhere the conductive frame. The insulating paste is cured to form the insulating pattern 6.

17B, when step S222 is performed, the conductive frame F4 is cut along the first cutting line L1 according to the position of the first cutting groove 403b in the first direction D1, and according to the second cutting groove 404 in the second direction D2. The conductive frame F4 is cut along the second cutting line L2 to form a plurality of chip packaging structures P6 separated from each other.

Referring to FIG. 18, the chip package structure P6 includes a conductive frame, a control chip R1, a first chip C1 ', and a second chip C2.

The conductive frame includes a bottom portion and at least one partition plate (four are shown in FIG. 18). The bottom portion has a first conductive portion 40 a and a second conductive portion 40 b that are separated from each other. The control wafer R1 and the first wafer C1 'are disposed on the first conductive portion 40a, and the control wafer R1 and the first conductive portion 40a are electrically insulated. The second wafer C2 is provided on the second conductive portion 40b.

The control chip R1 can be electrically connected to the control terminals of the first chip C1 'and the second chip C2 through the conductive frame and the circuit layer disposed on the circuit board. In this embodiment, the control wafer R1 and the first wafer C1 'are adjacent to each other but are placed in different accommodation areas, and the second wafer C2' is correspondingly placed in the two accommodation areas.

In addition, the chip package structure P6 further includes an insulating glue 6 'connected between the first conductive portion 40a and the second conductive portion 40b to electrically insulate the first conductive portion 40a and the second conductive portion 40b. When the chip package structure P6 is disposed on a circuit board, the source of the first chip C1 'can be electrically connected to the drain of the second chip C2 through the circuit board, the separator, and the second conductive portion 40b.

[Possible effects of the embodiments]

In summary, the beneficial effect of the present invention may be that, in the method for manufacturing a chip packaging structure provided by the embodiment of the present invention, placing a plurality of diced wafers on a conductive frame can reduce the use of plastic sealant. In the case, the wafer is provided with a supporting force and a mechanical strength. In addition, in the chip package structure of the embodiment of the present invention, the drain of the chip is electrically connected to the conductive frame, and the source and gate located on the active surface of the chip can be electrically connected to the circuit board. According to this, when the chip is in operation, the conductive frame and the circuit board can simultaneously dissipate heat to the chip, thereby providing a bidirectional heat dissipation effect.

In addition, when the conductive frame is cut to form a chip package structure, the positions where the insulating patterns are formed and the positions where the chips are cut can be changed to form different chip package structures to be suitable for different circuits. In addition, the chip package structure provided in the embodiment of the present invention directly forms a pad on the electrode that can be directly connected to the circuit board, which can reduce parasitic resistance and parasitic inductance. When the chip package structure of this embodiment is applied to a circuit element, the operation efficiency of the element can be improved. The above are only the preferred and feasible embodiments of the present invention, and therefore do not limit the patent scope of the present invention. Therefore, any equivalent technical changes made using the description and drawings of the present invention are included in the protection scope of the present invention. .

P1‧‧‧chip package structure

F1’‧‧‧ conductive frame

10‧‧‧ Active face

C1‧‧‧First Chip

20’‧‧‧ bottom

201‧‧‧ bearing surface

202‧‧‧ underside

5‧‧‧Circuit Board

21‧‧‧ divider

22‧‧‧ conductive layer

3‧‧‧Adhesive

105‧‧‧Gate pad

106‧‧‧Source Pad

110‧‧‧ Drain

Claims (10)

A chip packaging structure is provided on a circuit board. The chip packaging structure includes: a conductive frame having a bottom and a partition plate protruding from the bottom, and the partition plate and the The bottom is electrically connected, the conductive frame has at least one cutting end surface; and a wafer is disposed on the bottom, wherein the wafer and the partition plate are located on the same side of the bottom, and the back of the wafer has a An electrode disposed toward the bottom, and the electrode is electrically connected to the bottom; wherein the chip packaging structure has a gap between the partition plate and the wafer. The chip package structure according to claim 1, wherein when the chip package structure is disposed on the circuit board, an active surface of the wafer is disposed toward the circuit board, and the partition plate is connected to the circuit board. The electrode between the circuit board and the bottom, and located on the back of the wafer, is electrically connected to the circuit board through the bottom and the separator in order. The chip package structure according to claim 1, wherein the electrode on the back surface of the wafer is fixed to the bottom by a bonding adhesive, and the bonding adhesive is a conductive adhesive. The chip packaging structure according to claim 1, wherein the conductive frame further includes a conductive layer on one end surface of the partition plate, and the wafer further includes another electrode on the active surface of the wafer. The conductive layer and the electrodes on the active surface are both located on the same side of the chip package structure. The chip package structure according to claim 1, wherein the wafer is a power transistor Body or diode. A chip packaging structure is provided on a circuit board. The chip packaging structure includes: a conductive frame having a bottom and a plurality of partition plates, the bottom including a plurality of conductive portions insulated from each other, and a plurality of The partition plate is electrically connected to a plurality of the conductive portions, respectively; and a plurality of wafers disposed on the conductive frame, wherein each of the wafers is disposed on a corresponding one of the conductive portions, and each of the wafers The back surface of the chip has an electrode electrically connected to the corresponding conductive portion, and the back surface of each of the wafers is disposed toward the corresponding conductive portion; wherein the chip packaging structure has a plurality of separate portions located in the partitions. The space between the plate and the wafer. The chip package structure according to claim 6, further comprising an insulating gel to insulate a plurality of the conductive portions from each other. The chip package structure according to claim 7, wherein the number of the plurality of conductive portions is four, and the plan view shape of the insulating colloid is a cross shape, so that the four conductive portions pass through the insulating colloid to each other. insulation. The chip package structure according to claim 8, wherein the number of the plurality of wafers is four, and two of the four wafers are high-side power transistors and the other two are low-side power transistors. Crystal. The chip package structure according to claim 9, wherein when the chip package structure is provided on the circuit board, an active surface of each of the wafers faces the circuit board, and each of the partition boards is connected to the circuit board. Between the circuit board and the corresponding conductive portion, and a drain of one of the low-side power transistors sequentially passes through the corresponding The conductive part, the corresponding partition plate and the circuit board are electrically connected to a source of one of the high-side power transistors.