TWI678773B - Power chip scale package structure - Google Patents

Abstract

The invention discloses a power chip packaging structure. The power chip packaging structure includes a thinned wafer and a conductive support material. The thinned wafer has an active side and a back side opposite to the active side, and the thinned wafer is disposed with the active side toward the circuit substrate. A conductive support material is provided on the back side of the thinned wafer to provide mechanical strength. The conductive support material has an inner surface facing the thinned wafer, and the ratio of the area of the surface of the back side of the thinned wafer to the area of the inner surface of the conductive support ranges from 0.5 to 1.

Description

Power chip packaging structure

The invention relates to a power chip packaging structure, and more particularly to a thin power chip packaging structure.

With the development of portable and wearable electronic devices, it has become a trend to develop products with high efficiency, small size, high speed, high quality and versatility. The wafer size package manufactured by using Wafer Level Chip Scale Package (WLCSP) technology has a wafer volume close to the package size, which is beneficial to the miniaturization of the external dimensions of electronic devices.

The existing chip-size package is usually further disposed on a circuit board to be electrically connected to the main control chip. In order to further reduce the size of electronic devices, circuit boards used to provide chip-size packages are becoming thinner, and even flexible circuit boards that can be bent or flexed are used to replace rigid circuit boards.

However, since a relatively thin rigid circuit board or a flexible circuit board is easier to bend, and the thickness of the existing chip-size package is also very thin, it is easy for a wafer to be damaged due to the circuit board (thin rigid circuit board or flexible Circuit board) is bent and cracked or damaged.

One of the technical problems to be solved by the present invention is how to avoid thin wafers from being damaged due to bending of thinned circuit boards.

In order to solve the above technical problems, one of the technical solutions adopted by the present invention is to provide a power chip packaging structure. Power chip package structure includes a thin A chip and a conductive support material. The thinned wafer has an active side and a back side opposite to the active side. The conductive support material is disposed on the back side of the thinned wafer. The conductive support material has an inner surface facing the thinned wafer, and the ratio of the area of the backside surface of the thinned wafer to the inner surface area ranges from 0.5 to 1.

The beneficial effect of the present invention is that, the power chip package structure provided by the present invention, by “setting a conductive support material on the backside of the thinned wafer, and the ratio of the area of the backside surface of the thinned wafer to the area of the inner surface, It is a technical means from 0.5 to 1 ", which can increase the mechanical strength of the chip packaging structure, to avoid the thinned wafer disposed on the substrate, which is damaged due to the bending of the substrate.

In order to further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are only for reference and description, and are not intended to limit the present invention.

1‧‧‧Power Chip Package Structure

10‧‧‧ Thinned wafer

10a‧‧‧active side

10b‧‧‧ dorsal side

10S‧‧‧Side surface

T1, T2‧‧‧ Power Transistors

11‧‧‧ conductive support

11a‧‧‧Inner surface

11S‧‧‧ side

12‧‧‧ Adhesive layer

Z1, Z2‧‧‧ diodes

13‧‧‧back electrode

S1, S2‧‧‧ source pads

G1, G2‧‧‧Gate pad

2‧‧‧circuit board

21, 22‧‧‧ pads

11R‧‧‧Resistor

Components of P1‧‧‧Power Wafer Level Package Structure

FIG. 1 is a schematic perspective view of a power chip package structure according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of a power chip package structure according to an embodiment of the present invention.

FIG. 3 is a schematic circuit diagram of a power chip package structure according to an embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view of a component of a power chip package structure according to an embodiment of the present invention.

Please refer to FIG. 1 and FIG. 2. FIG. 1 is a schematic perspective view of a power chip package structure according to an embodiment of the present invention, and FIG. 2 is a schematic cross-sectional view of a power chip package structure according to an embodiment of the present invention.

The chip packaging structure 1 according to the embodiment of the present invention includes a thinned wafer 10 and a conductive support material 11. The thinned wafer 10 has an active side 10a and a back side 10b opposite to the active side 10a.

In this embodiment, the thinned wafer 10 is a semiconductor wafer, and through processes such as doping, etching, lithography, thinning, and circuit redistribution, at least one element (not shown) is formed inside the thinned wafer 10 and A circuit redistribution layer for connecting external circuits is formed on the thinned wafer 10. The line redistribution layer is located on the active side 10a, and can be customized according to actual needs. There are pads and wiring layers.

The thickness of the thinned wafer 10 ranges from 50 μm to 125 μm. Therefore, the thinned wafer 10 is easily damaged or cracked due to external stress. Accordingly, the chip packaging structure 1 of the embodiment of the present invention further includes a conductive support material 11, and the conductive support material 11 is disposed on the back side 10 b of the thinned wafer 10 to increase the mechanical strength of the chip packaging structure 1.

As shown in FIG. 1 and FIG. 2, the power chip packaging structure 1 further includes an adhesive layer 12. The adhesive layer 12 is located between the thinned wafer 10 and the conductive support material 11. The back side of the wafer 10 is thinned.

Referring to FIG. 2, in an embodiment, the conductive support material 11 completely covers the surface of the back side 10 b of the thinned wafer 10, and extends outward from the back side surface to exceed at least one edge of the back side surface. Specifically, the conductive support material 11 has an inner surface 11 a disposed facing the thinned wafer 10, and the area of the inner surface 11 a is greater than or equal to the surface area of the back side 10 b of the thinned wafer 10.

The area of the backside surface of the thinned wafer 10 is 50% to 100% of the area of the inner surface 11 a of the conductive support material 11. That is, the ratio of the area of the back surface of the thinned wafer 10 to the area of the inner surface 11 a of the conductive support material 11 ranges from 0.5 to 1.

In addition, in the power chip package structure 1 according to the embodiment of the present invention, the conductive support material 11 does not cover the side surface 10S of the thinned wafer 10, and exposes the side surface 10S of the thinned wafer 10.

In another embodiment, the side surface 11S of the conductive support material 11 is aligned with the side surface 10S of the thinned wafer 10. That is, the surface area of the back side 10 b of the thinned wafer 10 is the same as the area of the inner surface 11 a of the conductive support material 11.

According to this, the conductive support material 11 provided on the back side 10b of the thinned wafer 10 can increase the mechanical strength of the chip packaging structure 1 and protect the thinned wafer 10 to reduce the damage or cracks of the thinned wafer 10 due to external stress. Chance. In the embodiment of the present invention, the thickness of the conductive support material 11 is greater than or equal to 50 μm.

It should be noted that the power chip package structure 1 according to the embodiment of the present invention can be applied to Circuit protection element. Therefore, please refer to FIGS. 1 to 3. FIG. 3 is a schematic circuit diagram of a power chip package structure according to an embodiment of the present invention. The thinned wafer 10 may include two power transistors T1 and T2 connected in parallel with each other.

The power transistors T1 and T2 are, for example, vertical power transistors, insulated gate bipolar transistors (IGBTs), or bottom-source lateral diffusion MOSFETs (bottom-source lateral diffusion MOSFETs). ). In the embodiment of the present invention, a vertical power transistor is taken as an example for description.

Accordingly, as shown in FIG. 1, the thinned wafer 10 of this embodiment includes at least two sets of source pads S1 and S2 and two gate pads G1 and G2. One set of source pads S1 and one gate pad G1 are electrically connected to the source and gate of one power transistor T1, and the other set of source pads S2 and the other gate pad G2 It is electrically connected to the source and the gate of another power transistor T2, respectively.

In addition, the chip package structure 1 further includes a back electrode 13, and the back electrode 13 is located on the back side of the thinned wafer 10 and can be electrically connected to the drains of the two power transistors T1 and T2 as drain pads. . In other words, the drain of one power transistor T1 can be electrically connected to the drain of the other power transistor T2 through the back electrode 13.

The back electrode 13 may have a single-layer structure or a multi-layer structure. The material of the back electrode 13 can be selected from metal materials such as copper, titanium, nickel, silver, tin, and gold. In this embodiment, the back electrode 13 has a multilayer structure, and at least includes a titanium layer, a nickel layer, and a silver layer stacked on each other. However, the present invention does not limit the material of the back electrode 13.

As shown in FIG. 3, in this embodiment, each power transistor T1 (T2) is further connected in series with a diode Z1 (Z2). In detail, the source of the power transistor T1 (T2) is electrically connected to the anode of the diode Z1 (Z2), and the drain of the power transistor T1 (T2) is electrically connected to the diode The cathode of the body Z1 (Z2). Therefore, the two sets of source pads S1 and S2 shown in FIG. 1 are actually electrically connected to the positive electrodes of the two diodes Z1 and Z2 respectively. In other words, one set of source pads S1 is electrically connected to the anode of diode Z1, and the other set of source pads S2 is electrically connected to diode Z2. Positive electrode.

It should be noted that the two power transistors T1 and T2 and the two diodes Z1 and Z2 can be formed by making the thinned wafer 10 have different doped regions and doped concentrations. In addition, the two power transistors T1 and T2 and the two diodes Z1 and Z2 can establish an electrical connection relationship as shown in FIG. 3 through the redistribution layer of the line and the back electrode 13.

In addition to reducing the probability of the thin wafer 10 being damaged or cracked due to external stress, the conductive support material 11 can also reduce the resistance in the circuit when the power transistors T1 and T2 operate, and can perform the thin wafer 10 Cooling.

According to this, the conductive support material 11 may be a conductive material selected with better conductivity and heat dissipation. In an embodiment, the conductive support material 11 may be a metal sheet, such as a copper sheet or an aluminum sheet.

In this embodiment, the adhesive layer 12 located between the conductive support material 11 and the back electrode 13 of the thinned wafer 10 is a conductive adhesive layer, and the material of the conductive adhesive layer may be solder or a metal-containing adhesive material. The conductive support material 11 may be fixed to the back side 10 b of the thinned wafer 10 by a conductive adhesive layer.

Please refer to FIG. 2 and FIG. 3. That is to say, the conductive support material 11 is also electrically connected to the back electrode 13 through the conductive adhesive layer, and then electrically connected between the drains of the two power transistors T1 and T2. Therefore, when the thinned wafer 10 is used in an element, the resistance 11R of the conductive support material 11 also affects the total resistance value of the entire circuit.

Compared with using an insulating material as a supporting material or using an insulating adhesive material, in this embodiment, attaching the conductive supporting material 11 to the back side of the thinned wafer 10 through the conductive adhesive layer can not only increase the machinery of the chip packaging structure 1 Strength can also further reduce the total resistance value of the entire circuit.

An embodiment of the present invention also provides a component to which the above chip packaging structure 1 is applied. Please refer to FIG. 4, which is a schematic cross-sectional view of a component P1 of a power wafer-level package structure according to an embodiment of the present invention.

The component P1 of the power wafer-level package structure includes a circuit substrate 2 and a line substrate. Chip package structure 1 on circuit substrate 2. The circuit substrate 2 may be a rigid circuit board or a flexible circuit board. In the circuit substrate 2, a circuit has been laid out and has a plurality of pads 21, 22 for electrically connecting with the chip package structure 1.

In addition, it should be noted that although not shown in FIG. 4, it should be understood that the component P1 of the power chip-level packaging structure may actually include other chips that are disposed on the circuit substrate 2 and have other functions, such as: The wafers work together with the power transistors T1 and T2 in the thinned wafer 10 according to the embodiment of the present invention.

When the chip package structure 1 is disposed on the circuit substrate 2, the active side 10 a of the thinned wafer 10 is disposed toward the circuit substrate 2. Further, the source pads S1, S2 and the gate pads G1, G2 of the thinned wafer 10 respectively correspond to a plurality of pads 21, 22 on the circuit substrate 2, so that the thinned wafer 10 can be soldered It is provided on the circuit board 2.

On the other hand, the power transistors T1 and T2 of the thinned wafer 10 can pass through the source pads S1, S2, the gate pads G1, G2, and correspond to the source pads S1, S2, and the gate pads G1, respectively. The plurality of bonding pads 21 and 22 of G2 are electrically connected to other functional chips on the circuit board 2.

It should be noted that in order to make the electronic device as thin as possible, the circuit substrate 2 of the element P1 of the power chip-level packaging structure is also becoming thinner and thinner. Therefore, the thickness of the circuit substrate 2 in this embodiment will be less than 0.5 mm.

Since the thickness of the circuit substrate 2 is relatively thin, it is easily bent, so that the thinned wafer 10 provided on the circuit substrate 2 is stressed and damaged or cracks are generated. Therefore, the power chip package structure 1 of the embodiment of the present invention is provided with a conductive support material 11 on the back side 10 b of the thinned wafer 10, which can reduce the chance of the thinned wafer 10 being damaged due to the bending of the circuit substrate 2.

In this embodiment, the thickness of the conductive support material 11 is at least 50 μm. However, if the thickness of the conductive support material 11 is too thick, the total thickness of the element P1 of the power wafer-level packaging structure increases, and the cost increases. According to this, the thickness of the conductive support material 11 can be greater than 50 μm, and can be adjusted according to actual needs.

To sum up, the beneficial effects of the present invention are that the chip packaging structure 1 and the power chip-level packaging element P1 provided by the present invention are provided with a conductive support material 11 on the back side of the thinned wafer 10, and "Thinning the ratio of the area of the back surface of the wafer 10 to the area of the inner surface 11a is at least between 0.5 and 1", which can increase the mechanical strength of the chip package structure 1. When the chip packaging structure 1 is applied to the component P1, the conductive support material 11 can provide the supporting strength of the thinned wafer 10 to reduce the chance of the thinned wafer 10 on the circuit substrate 2 being damaged due to the bending of the circuit substrate 2.

In addition, in addition to reducing the probability of the thin wafer 10 being damaged or cracked due to external stress, the conductive support material 11 can also reduce the resistance of the circuit when the power transistors T1 and T2 are operating. In addition, the conductive support material 11 can also increase the heat dissipation path of the thinned wafer 10 to improve the heat dissipation efficiency of the thinned wafer 10 during operation.

The content disclosed above is only the preferred and feasible embodiment of the present invention, and therefore does not limit the scope of patent application of the present invention. Therefore, any equivalent technical changes made by using the description and drawings of the present invention are included in the application of the present invention. Within the scope of the patent.

Claims (8)

A power chip packaging structure includes: a thinned wafer having an active side and a back side opposite to the active side; and a conductive support material disposed on the back side of the thinned wafer Wherein, the conductive support material has an inner surface facing the thinned wafer, and a ratio of an area of a backside surface of the thinned wafer to an area of the inner surface ranges from 0.5 to 1, and The conductive support material does not have a portion extending from the back side to the active side along one side surface of the thinned wafer. The power chip package structure according to claim 1, further comprising a conductive adhesive layer, the conductive adhesive layer is located between the thinned wafer and the conductive support material, and the conductive support material passes the conductive The glue is fixed on the back side of the thinned wafer. The power chip package structure according to claim 2, wherein the conductive adhesive layer is a solder layer or a metal-containing adhesive layer. The power chip package structure according to claim 1, wherein the thinned wafer has at least two power transistors connected in parallel with each other. The power chip package structure according to claim 4, wherein each of the power transistors is connected in series with a diode. The power chip package structure according to claim 4, further comprising: a back electrode, the back electrode is located on the back side of the thinned wafer, and is electrically connected to two drains of the two power transistors. pole. The power chip package structure according to claim 1, wherein the thickness of the thinned wafer ranges from 50 μm to 125 μm. The power chip package structure according to claim 1, wherein the thickness of the conductive support material is greater than or equal to 50 μm.