CN208954972U - Power chip encapsulating structure - Google Patents
Power chip encapsulating structure Download PDFInfo
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- CN208954972U CN208954972U CN201821805402.9U CN201821805402U CN208954972U CN 208954972 U CN208954972 U CN 208954972U CN 201821805402 U CN201821805402 U CN 201821805402U CN 208954972 U CN208954972 U CN 208954972U
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- chip
- thinned
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- encapsulating structure
- supporting material
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Abstract
The utility model discloses a kind of power chip encapsulating structure.Power chip encapsulating structure includes thinned chip and conductive supporting material.Thinned chip has master end and the back side in contrast to the master end, and thinned chip is arranged with master end towards circuit base plate.Conductive supporting material is set to the back side of thinned chip, to provide mechanical strength.Conductive supporting material has the inner surface towards thinned chip, and the ratio range of the area of the inner surface of the area and conductive supporting material on the surface of a back side of thinned chip is by between 0.5 to 1.Accordingly, the mechanical strength of chip-packaging structure can be increased, to avoid the thinned chip being disposed on the substrate, be damaged because of the bending of substrate.
Description
Technical field
The utility model relates to a kind of power chip encapsulating structures, more particularly to a kind of slim power chip encapsulation knot
Structure.
Background technique
With portable and wearable electronic device development, exploitation has high-effect, small in size, high speed, high quality
And multi-functional product becomes trend.Due to utilizing crystal wafer chip dimension encapsulation (Wafer Level Chip Scale
Package, WLCSP) in chip size packages body manufactured by technology, the volume and package dimension of chip are close, and are conducive to
Make the outer dimension of electronic device towards miniaturization.
Existing chip size packages body would generally be further disposed upon on a circuit board, to be electrically connected at master control core
Piece.In order to reduce the size of electronic device further, for be arranged chip size packages body circuit board it is also more next
It is thinner, or even hard circuit board can be replaced using bent or flexure flexible circuit board.
However, since the relatively small hard circuit board of thickness either flexible circuit board is easier to be bent, and it is existing
Chip size packages body thickness it is also very thin, therefore, chip is easy to that (slim hard circuit board is soft because of circuit board
Property circuit board) bending and rupture or damage.
Utility model content
The technical problem to be solved by the utility model is to circuit of the chip for how avoiding thickness partially thin because of thinning
Plate bends and damages.
In order to solve the above technical problems, wherein a technical solution is to provide a kind of function used by the utility model
Rate chip-packaging structure.Power chip encapsulating structure includes a thinned chip and a conductive supporting material.Thinned chip has one
Master end and one in contrast to master end back side.Conductive supporting material is set to the back side of thinned chip.Conductive supporting material has
An inner surface towards thinned chip, and the ratio range of the area of the area and inner surface on the surface of a back side of thinned chip
It is by 0.5 to 1.
Further, power chip encapsulating structure still further comprises a conductive adhesive layer, and conductive adhesive layer is located at thinning core
Between piece and conductive supporting material, and conductive supporting material is fixed on the back side of thinned chip by conducting resinl.
Further, conductive adhesive layer is solder layer either metalliferous glue-line.
Further, thinned chip has at least two power transistors parallel with one another.
Further, each power transistor and a Diode series.
Further, power chip encapsulating structure may further comprise: that a back electrode, back electrode are located at thinned chip
Back side, and it is electrically connected at two drain electrodes of two power transistors.
Further, the thickness range of thinned chip is by 50 μm to 125 μm.
Further, the thickness of conductive supporting material is at least greater than or equal to 50 μm.
The beneficial effects of the utility model are that power chip encapsulating structure provided by the utility model passes through and " sets
Conductive supporting material is set in the back side of thinned chip, and the ratio of the area of the area and inner surface on the surface of a back side of thinned chip
Value range is by 0.5 to 1 " technological means, the mechanical strength of chip-packaging structure can be increased, to avoid what is be disposed on the substrate
Thinned chip is damaged because of the bending of substrate.
For the enabled feature and technology contents for being further understood that the utility model, please refer to below in connection with the utility model
Detailed description and accompanying drawings, however provided attached drawing is merely provided for reference and description, is not used to add the utility model
With limitation.
Detailed description of the invention
Fig. 1 is the stereoscopic schematic diagram of the utility model wherein power chip encapsulating structure of an embodiment.
Fig. 2 is the diagrammatic cross-section of the utility model wherein power chip encapsulating structure of an embodiment.
Fig. 3 is the circuit diagram of the power chip encapsulating structure of an embodiment of the present invention.
Fig. 4 is the diagrammatic cross-section of the component of the power chip encapsulating structure of an embodiment of the present invention.
Specific embodiment
Please refer to Fig. 1 and Fig. 2.Fig. 1 is power chip encapsulating structure (the Power Chip of an embodiment of the present invention
Scale Package) stereoscopic schematic diagram, and Fig. 2 is the utility model wherein power chip encapsulating structure of an embodiment
Diagrammatic cross-section.
The chip-packaging structure 1 of the utility model embodiment includes a thinned chip 10 and a conductive supporting material 11.It is thin
Changing chip 10 has a master end 10a and back side 10b opposite with the master end 10a.
In the present embodiment, thinned chip 10 is semiconductor chip, and through overdoping, etching, lithographic, thinning, route weight
The processing procedures such as cloth, and form an at least element (not shown) inside thinned chip 10 and formed in thinned chip 10 to even
Connect the route redistribution layer of outside line.Route redistribution layer is located at master end 10a, and can according to actual needs and have connection pad and
Line layer.
The thickness range of thinned chip 10 is by 50 μm to 125 μm.Therefore, thinned chip 10 is easy to because being answered by outside
Power, and it is damaged or generates crack.Accordingly, the chip-packaging structure 1 of the utility model embodiment further includes a conductive supporting
Material 11, and conductive supporting material 11 is set to the back side 10b of thinned chip 10, to increase the mechanical strength of chip-packaging structure 1.
As shown in Figures 1 and 2, power chip encapsulating structure 1 still further comprises a glue-line 12, and glue-line 12 is to be located at thinning
Between chip 10 and conductive supporting material 11, and conductive supporting material 11 is fixed on the back side of thinned chip 10 by glue-line 12.
Referring to figure 2., in one embodiment, conductive supporting material 11 can be completely covered by the table of the back side 10b of thinned chip 10
Face, and extend outwardly past by the surface of back side 10b an at least edge on the surface of back side 10b.Specifically, conductive supporting
Material 11 has the inner surface 11a being arranged towards thinned chip 10, and the area of inner surface 11a can be greater than or equal to thinned chip
The area on the surface of 10 back side 10b.
The area of the back surface of thinned chip 10 is the 50% to 100% of the inner surface 11a area of conductive supporting material 11.
That is, the ratio range of the inner surface 11a area of the surface area of the back side 10b of thinned chip 10 and conductive supporting material 11
It is by 0.5 to 1.
In addition, in the power chip encapsulating structure 1 of the utility model embodiment, conductive supporting material 11 and uncoated thinning
The side surface 10S of chip 10, and expose the side surface 10S of thinned chip 10.
In another embodiment, the side 11S of conductive supporting material 11 can be trimmed with the side surface 10S of thinned chip 10.?
That is the surface area of the back side 10b of thinned chip 10 is identical as the inner surface 11a area of conductive supporting material 11.
Accordingly, the conductive supporting material 11 for being set to 10 back side 10b of thinned chip can increase the machinery of chip-packaging structure 1
Intensity, and thinned chip 10 is protected, the probability in crack is damaged or generated to reduce thinned chip 10 due to by external stress.?
In the utility model embodiment, the thickness of conductive supporting material 11 is greater than or equal to 50 μm.
It should be noted that the power chip encapsulating structure 1 of the utility model embodiment can be applied in circuit protecting assembly.
Therefore, please cooperate referring to figs. 1 to Fig. 3.Fig. 3 shows the circuit signal of the power chip encapsulating structure of an embodiment of the present invention
Figure.Thinned chip 10 may include two power transistor T1, T2 parallel with one another.
Power transistor T1, T2 are, for example, rectilinear power transistor, insulated gate bipolar transistor (Insulated
Gate Bipolar Transistor, IGBT) or bottom source lateral double diffusion metal oxide semiconductor field-effect transistor
(bottom-source lateral diffusion MOSFET).In the utility model embodiment, with rectilinear power crystal
It is illustrated for pipe.
Accordingly, as shown in Figure 1, the thinned chip 10 of the present embodiment includes at least two groups of source electrode connection pad S1, S2 and two
Grid connection pad G1, G2.Wherein one group of source electrode connection pad S1 and wherein a grid connection pad G1 is electrically connected at a wherein power crystal
The source electrode and grid of pipe T1, and another group of source electrode connection pad S2 and another grid connection pad G2 are electrically connected in another
The source electrode and grid of a power transistor T2.
In addition, chip-packaging structure 1 further includes a back electrode 13, and back electrode 13 is the back side positioned at thinned chip 10,
And can be electrically connected at two power transistors T1, T2 drain electrode and as drain electrode connection pad.In other words, one of power is brilliant
The drain electrode of body pipe T1 can be electrically connected at the drain electrode of another power transistor T2 by back electrode 13.
Back electrode 13 can have single layer structure either multilayered structure.The material of back electrode 13 can choose copper, titanium,
The metal materials such as nickel, silver, tin, gold.In the present embodiment, back electrode 13 has multilayered structure, and includes at least and be stacked with
Titanium layer, nickel layer and silver layer.However, the utility model is not limiting as the material of back electrode 13.
As shown in figure 3, in the present embodiment, each power transistor T1 (T2) also connects a diode Z1 (Z2).In detail
For thin, the source electrode of power transistor T1 (T2) can be electrically connected at the anode (anode) of diode Z1 (Z2), and power crystal
The drain electrode of pipe T1 (T2) can be electrically connected at the cathode (cathode) of diode Z1 (Z2).Therefore, two groups shown in Fig. 1
Source electrode connection pad S1, S2 can actually be electrically connected in the anode of two diodes Z1, Z2.That is, wherein one group of source
Pole connection pad S1 can be electrically connected at the anode of diode Z1, and another group of source electrode connection pad S2 can be electrically connected at diode Z2 just
Pole.
It should be noted that can be formed by making that there is different doped region and doping concentration inside thinned chip 10
Above-mentioned two power transistor T1, T2 and two diodes Z1, Z2.In addition, two power transistors T1, T2 and two
Diode Z1, Z2 can establish electrical connection as shown in Figure 3 by route redistribution layer and back electrode 13.
Conductive supporting material 11 in addition to reduce thinned chip 10 damage or generate due to by external stress crack probability it
Outside, the resistance in circuit can also be reduced, and can radiate to thinned chip 10 when power transistor T1, T2 are run.
Accordingly, conductive supporting material 11 can be selection electric conductivity and the preferable conductive material of thermal diffusivity.In one embodiment,
Conductive supporting material 11 can be metal sheet, such as: copper sheet or aluminium flake.
In this embodiment, the glue-line 12 between conductive supporting material 11 and the back electrode of thinned chip 10 13 is
Conductive adhesive layer, and the material of conductive adhesive layer can be solder either metalliferous glue material.Conductive supporting material 11 can pass through conduction
Glue-line is fixed on the back side 10b of thinned chip 10.
Referring to figure 2. and Fig. 3, that is to say, that conductive supporting material 11 can also be electrically connected at back electricity by conductive adhesive layer
Pole 13, and then be electrically connected between the drain electrode of two power transistors T1, T2.Therefore, when thinned chip 10 is applied to component
When middle, the resistance 11R of conductive supporting material 11 also will affect the total resistance value of entire circuit.
Compared to using insulating materials either to use insulation glue material as fid, in the present embodiment, by conduction branch
Timbering 11 is attached at 10 back side of thinned chip by conductive adhesive layer, can not only increase the mechanical strength of chip-packaging structure 1, can also
To further decrease the total resistance value of entire circuit.
The utility model embodiment simultaneously provides a kind of component using said chip encapsulating structure 1.Referring to figure 4., it shows
The diagrammatic cross-section of the component P1 of the power chip class encapsulation structure of an embodiment of the present invention.
The component P1 of power chip class encapsulation structure includes circuit base plate 2 and the chip being set on circuit base plate 2 envelope
Assembling structure 1.Circuit base plate 2 can be rigid wiring board or flexible circuit board.In circuit base plate 2, route has been laid simultaneously
With multiple weld pads 21,22 to be electrically connected with chip-packaging structure 1.
Although in addition, it is noted that not showed that in Fig. 4, it should be appreciated that the component of power chip class encapsulation structure
P1 substantially may also contain other and be set on circuit base plate 2 and have other function chip, such as: main control chip, with cooperation
Power transistor T1, T2 in the thinned chip 10 of the utility model embodiment are operated together.
It is with the master end 10a of thinned chip 10 towards route when chip-packaging structure 1 is set on circuit base plate 2
Substrate 2 and be arranged.Furthermore, source electrode connection pad S1, S2 of thinned chip 10 and grid connection pad G1, G2 can be corresponded respectively to
Multiple weld pads 21,22 on circuit base plate 2, and be set to thinned chip 10 can by welding on circuit base plate 2.
On the other hand, power transistor T1, T2 of thinned chip 10 can pass through source electrode connection pad S1, S2, grid connection pad G1, G2
And multiple weld pads 21,22 of source electrode connection pad S1, S2 and grid connection pad G1, G2 are corresponded respectively to, it is electrically connected at circuit base plate 2
On other function chip.
It should be noted that for thinned electronic as far as possible, the route of the component P1 of power chip class encapsulation structure
Substrate 2 is also more and more thinner.Therefore, the thickness of the circuit base plate 2 of the present embodiment can be less than 0.5mm.
It since the thickness of circuit base plate 2 is partially thin, and is easy to be bent, to make the thinning being set on circuit base plate 2
Chip 10 is damaged or generates crack by stress.Therefore, the power chip encapsulating structure 1 of the utility model embodiment is in thinning
Conductive supporting material 11 is arranged in the back side 10b of chip 10, can reduce the probability that thinned chip 10 is damaged because circuit base plate 2 is bent.
In the present embodiment, the thickness of conductive supporting material 11 is equal to or more than 50 μm.However, the thickness of conductive supporting material 11
Du Ruotai is thick, the overall thickness of the component P1 of power chip class encapsulation structure can be made to increase, and increase cost.Accordingly, conductive supporting
The thickness of material 11 can be greater than 50 μm, and adjust according to actual needs.
In summary, the beneficial effects of the utility model are, chip-packaging structure 1 provided by the utility model and answer
With the component P1 of its power chip class encapsulation structure, by " setting conductive supporting material 11 thinned chip 10 back side, and
The area of one back surface of thinned chip 10 and the ratio range of inner surface 11a area are by 0.5 to 1 " technological means, can increase
The mechanical strength of concrete-cored chip package 1.When chip-packaging structure 1 is applied in component P1, conductive supporting material 11 be can provide
10 support strength of thinned chip, it is impaired because circuit base plate 2 is bent to reduce the thinned chip 10 on circuit base plate 2
Probability.
In addition, conductive supporting material 11 damages or generates the several of crack due to by external stress in addition to reducing thinned chip 10
Except rate, the resistance of circuit can also be reduced when power transistor T1, T2 are run.In addition, conductive supporting material 11 can also increase
The heat dissipation path of thinned chip 10, to improve radiating efficiency when thinned chip 10 is run.
Content disclosed above is only the preferred possible embodiments of the utility model, not thereby limits to the utility model
Claims protection scope, so all equivalence techniques for being done with the utility model specification and accompanying drawing content become
Change, is both contained in the protection scope of claims of the utility model.
Claims (8)
1. a kind of power chip encapsulating structure, which is characterized in that the power chip encapsulating structure includes:
One thinned chip, with a master end and one in contrast to the master end back side；And
One conductive supporting material is set to the back side of the thinned chip, wherein the conductive supporting material has towards institute
State an inner surface of thinned chip, the ratio of the area of the area and inner surface on the surface of a back side of the thinned chip
Range is by 0.5 to 1.
2. power chip encapsulating structure according to claim 1, which is characterized in that the power chip encapsulating structure also into
One step includes: a conductive adhesive layer, and the conductive adhesive layer described is led between the thinned chip and the conductive supporting material
Electric fid is fixed on the back side of the thinned chip by the conducting resinl.
3. power chip encapsulating structure according to claim 2, which is characterized in that the conductive adhesive layer be solder layer or
It is metalliferous glue-line.
4. power chip encapsulating structure according to claim 1, which is characterized in that the thinned chip has at least two
Power transistor parallel with one another.
5. power chip encapsulating structure according to claim 4, which is characterized in that each power transistor and one or two
Pole pipe series connection.
6. power chip encapsulating structure according to claim 4, which is characterized in that the power chip encapsulating structure also into
One step includes: a back electrode, and the back electrode is located at the back side of the thinned chip, and it is brilliant to be electrically connected at two power
Two drain electrodes of body pipe.
7. power chip encapsulating structure according to claim 1, which is characterized in that the thickness range of the thinned chip by
50 μm to 125 μm.
8. power chip encapsulating structure according to claim 1, which is characterized in that the thickness of the conductive supporting material is greater than
Or it is equal to 50 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821805402.9U CN208954972U (en) | 2018-11-02 | 2018-11-02 | Power chip encapsulating structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821805402.9U CN208954972U (en) | 2018-11-02 | 2018-11-02 | Power chip encapsulating structure |
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| Publication Number | Publication Date |
|---|---|
| CN208954972U true CN208954972U (en) | 2019-06-07 |
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ID=66743947
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| Application Number | Title | Priority Date | Filing Date |
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| CN201821805402.9U Active CN208954972U (en) | 2018-11-02 | 2018-11-02 | Power chip encapsulating structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111146157A (en) * | 2018-11-02 | 2020-05-12 | 尼克森微电子股份有限公司 | Power chip packaging structure |
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2018
- 2018-11-02 CN CN201821805402.9U patent/CN208954972U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111146157A (en) * | 2018-11-02 | 2020-05-12 | 尼克森微电子股份有限公司 | Power chip packaging structure |
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