TWM575188U - Power chip scale package structure - Google Patents

Abstract

A power chip package structure is provided. The power chip scale package structure includes a thin chip and a metal sheet. The thin chip has an active side and a back side opposite thereto, and the thin chip is disposed on the circuit board with the active side facing to the circuit board. The conductive supporting sheet is disposed at the back side of the thin chip to enhance the mechanical strength of the chip scale package structure. The conductive supporting sheet has an inner surface facing to the thin chip, and a ratio of the backside surface area to the inner surface area of the supporting sheet is at least between 0.5 and 1.

Description

Power chip package structure

The present invention relates to a power chip package structure, and more particularly to a thin power chip package structure.

With the development of portable and wearable electronic devices, the development of products with high efficiency, small size, high speed, high quality and versatility has become a trend. In the wafer size package manufactured by the wafer level wafer scale package (WLCSP) technology, the volume of the wafer is close to the package size, which is advantageous for miniaturization of the electronic device.

The existing chip size package is usually further disposed on a circuit board to be electrically connected to the main control chip. In order to further reduce the size of the electronic device, the circuit board for setting the wafer size package is also becoming thinner and thinner, and even a flexible circuit board that can be bent or flexed is used instead of the rigid circuit board.

However, since a rigid circuit board or a flexible circuit board having a relatively small thickness is easily bent, and the thickness of the existing wafer size package is also very thin, the wafer is easily formed by a circuit board (thin hard board or soft). The board is bent and broken or damaged.

One of the technical problems to be solved by the present invention is how to avoid that a wafer having a thin thickness is damaged due to bending of a thinned circuit board.

In order to solve the above technical problem, one of the technical solutions adopted by the present invention is to provide a power chip package structure. The power chip package structure includes a thinning A wafer and a conductive support material. The thinned wafer has an active side and a back side opposite the active side. A conductive support is disposed on the back side of the thinned wafer. The conductive support has an inner surface facing the thinned wafer, and the ratio of the area of the back side surface of the thinned wafer to the inner surface area ranges from 0.5 to 1.

The beneficial effect of the present invention is that the power chip package structure provided by the present invention passes the "setting of the conductive support material on the back side of the thinned wafer, and thinning the ratio of the area of the back side surface of the wafer to the inner surface area" It is a 0.5 to 1" technique that increases the mechanical strength of the chip package structure to avoid thinned wafers disposed on the substrate, which are damaged by bending of the substrate.

In order to further understand the features and technical contents of the present invention, please refer to the following detailed description of the present invention and the accompanying drawings. However, the drawings are provided for reference and description only, and are not intended to limit the creation.

1‧‧‧Power chip package structure

10‧‧‧Thin wafer

10a‧‧‧active side

10b‧‧‧ Back side

10S‧‧‧ side surface

T1, T2‧‧‧ power transistor

11‧‧‧ Conductive support

11a‧‧‧ inner surface

11S‧‧‧ side

12‧‧‧ glue layer

Z1, Z2‧‧‧ diode

13‧‧‧ Back electrode

S1, S2‧‧‧ source pads

G1, G2‧‧‧ gate pads

2‧‧‧Line substrate

21, 22‧‧‧ solder pads

11R‧‧‧resistance

P1‧‧‧Power Wafer Level Package Components

FIG. 1 is a perspective view of a power chip package structure according to an embodiment of the present invention.

2 is a cross-sectional view showing a power chip package structure of one embodiment of the present invention.

FIG. 3 is a circuit diagram of a power chip package structure according to an embodiment of the present invention.

4 is a cross-sectional view showing the components of a power chip package structure in accordance with an embodiment of the present invention.

Please refer to Figure 1 and Figure 2. 1 is a perspective view of a power chip scale package according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing a power chip package structure according to an embodiment of the present invention.

The chip package structure 1 of the present embodiment includes a thinned wafer 10 and a conductive support member 11. The thinned wafer 10 has an active side 10a and a back side 10b opposite the active side 10a.

In this embodiment, the thinned wafer 10 is a semiconductor wafer, and is doped, etched, lithographic, thinned, line rewired, etc., and at least one component (not shown) is formed inside the thinned wafer 10 and A line redistribution layer for connecting external lines is formed on the thinned wafer 10. The line redistribution layer is located on the active side 10a and can be provided according to actual needs. There are pads and circuit layers.

The thickness of the thinned wafer 10 ranges from 50 μm to 125 μm. Therefore, the thinned wafer 10 is easily damaged or cracked due to external stress. Accordingly, the wafer package structure 1 of the present embodiment further includes a conductive support member 11 and the conductive support member 11 is disposed on the back side 10b of the thinned wafer 10 to increase the mechanical strength of the wafer package structure 1.

As shown in FIG. 1 and FIG. 2, the power chip package structure 1 further includes a glue layer 12 between the thinned wafer 10 and the conductive support member 11, and the conductive support member 11 is fixed to the conductive layer 11 by the glue layer 12. The back side of the wafer 10 is thinned.

Referring to FIG. 2, in an embodiment, the conductive support 11 completely covers the surface of the back side 10b of the thinned wafer 10 and extends outwardly from the back side surface beyond at least one edge of the back side surface. Specifically, the conductive support 11 has an inner surface 11a disposed facing the thinned wafer 10, and the area of the inner surface 11a may be greater than or equal to the surface area of the back side 10b of the thinned wafer 10.

The area of the back side surface of the thinned wafer 10 is 50% to 100% of the area of the inner surface 11a of the conductive support member 11. That is, the ratio of the area of the back side surface of the thinned wafer 10 to the area of the inner surface 11a of the conductive support 11 is in the range of 0.5 to 1.

Further, in the power chip package structure 1 of the present embodiment, the conductive support member 11 is not coated with the side surface 10S of the thinned wafer 10, and the side surface 10S of the thinned wafer 10 is exposed.

In another embodiment, the side surface 11S of the conductive support 11 will be aligned with the side surface 10S of the thinned wafer 10. That is, the surface area of the back side 10b of the thinned wafer 10 is the same as the area of the inner surface 11a of the conductive support member 11.

Accordingly, the conductive support 11 disposed on the back side 10b of the thinned wafer 10 can increase the mechanical strength of the wafer package structure 1 and protect the thinned wafer 10 to reduce damage or cracking of the thinned wafer 10 due to external stress. Probability. In the present embodiment, the thickness of the conductive support 11 is greater than or equal to 50 μm.

It should be noted that the power chip package structure 1 of the present embodiment can be applied to In circuit protection components. Therefore, please refer to FIG. 1 to FIG. 3 together. 3 is a circuit diagram showing a power chip package structure of an embodiment of the present invention. The thinned wafer 10 can include two power transistors T1, T2 connected in parallel with each other.

The power transistors T1 and T2 are, for example, a vertical power transistor, an insulated gate bipolar transistor (IGBT) or a bottom-source lateral diffusion MOSFET (bottom-source lateral diffusion MOSFET). ). In the present embodiment, a vertical power transistor is taken as an example for description.

Accordingly, as shown in FIG. 1, the thinned wafer 10 of the present embodiment includes at least two sets of source pads S1, S2 and two gate pads G1, G2. One set of source pads S1 and one of the gate pads G1 are electrically connected to the source and gate of one of the power transistors T1, and the other set of source pads S2 and the other gate pads G2 They are electrically connected to the source and gate of another power transistor T2, respectively.

In addition, the chip package structure 1 further includes a back electrode 13 , and the back electrode 13 is located on the back side of the thinned wafer 10 and can be electrically connected to the drains of the two power transistors T1 and T2 as a drain pad. . In other words, the drain of one of the power transistors T1 can be electrically connected to the drain of the other power transistor T2 through the back electrode 13.

The back electrode 13 may have a single layer structure or a multilayer structure. The material of the back electrode 13 may be selected from metallic materials such as copper, titanium, nickel, silver, tin, gold, and the like. In the present embodiment, the back electrode 13 has a multilayer structure including at least a titanium layer, a nickel layer, and a silver layer which are stacked one on another. However, this creation does not limit the material of the back electrode 13.

As shown in FIG. 3, in the present embodiment, each power transistor T1 (T2) is also connected in series with a diode Z1 (Z2). In detail, the source of the power transistor T1 (T2) is electrically connected to the anode of the diode Z1 (Z2), and the drain of the power transistor T1 (T2) is electrically connected to the diode. The cathode of the body Z1 (Z2). Therefore, the two sets of source pads S1 and S2 shown in FIG. 1 are actually electrically connected to the positive electrodes of the two diodes Z1 and Z2, respectively. That is to say, one set of source pads S1 is electrically connected to the positive pole of the diode Z1, and the other set of source pads S2 is electrically connected to the diode Z2. The positive pole.

It should be noted that the two power transistors T1 and T2 and the two diodes Z1 and Z2 can be formed by having different doping regions and doping concentrations inside the thinned wafer 10. In addition, the two power transistors T1, T2 and the two diodes Z1, Z2 can pass through the line redistribution layer and the back electrode 13, thereby establishing an electrical connection relationship as shown in FIG.

In addition to reducing the probability that the thinned wafer 10 is damaged or cracked by external stress, the conductive support 11 can also reduce the resistance in the circuit when the power transistors T1 and T2 operate, and can perform the thinning of the wafer 10. Cooling.

Accordingly, the conductive support member 11 may be a conductive material that is preferably selected for conductivity and heat dissipation. In an embodiment, the conductive support 11 may be a metal sheet such as a copper sheet or an aluminum sheet or the like.

In this embodiment, the adhesive layer 12 between the conductive support 11 and the back electrode 13 of the thinned wafer 10 is a conductive adhesive layer, and the conductive adhesive layer may be made of solder or a metal-containing adhesive. The conductive support 11 may be fixed to the back side 10b of the thinned wafer 10 by a conductive adhesive layer.

Referring to FIG. 2 and FIG. 3 , the conductive support material 11 is also electrically connected to the back electrode 13 through a conductive adhesive layer, and is electrically connected between the drains of the two power transistors T1 and T2 . Therefore, when the thinned wafer 10 is applied to an element, the resistance 11R of the conductive support 11 also affects the total resistance value of the entire circuit.

In the present embodiment, the conductive support material 11 is attached to the back side of the thinned wafer 10 through the conductive adhesive layer, which not only increases the mechanical structure of the wafer package structure 1 , but also uses the insulating material as the support material or the insulating adhesive material. The strength can also further reduce the total resistance of the entire circuit.

The present embodiment and an element for applying the above-described chip package structure 1 are provided. Referring to FIG. 4, a cross-sectional view of an element P1 of a power chip level package structure according to an embodiment of the present invention is shown.

The component P1 of the power chip level package structure includes the circuit substrate 2 and is disposed on the line The chip package structure 1 on the substrate 2. The circuit substrate 2 may be a rigid wiring board or a flexible wiring board. In the circuit substrate 2, a wiring has been laid and has a plurality of pads 21, 22 for electrically connecting to the chip package structure 1.

In addition, it should be noted that although not shown in FIG. 4, it should be understood that the component P1 of the power chip level package structure may substantially include other chips disposed on the circuit substrate 2 and having other functions, such as: The wafers cooperate to operate in conjunction with the power transistors T1, T2 in the thinned wafer 10 of the presently-created embodiment.

When the chip package structure 1 is disposed on the circuit substrate 2, the active side 10a of the thinned wafer 10 is disposed toward the circuit substrate 2. Further, the source pads S1 and S2 and the gate pads G1 and G2 of the thinned wafer 10 respectively correspond to the plurality of pads 21 and 22 on the circuit substrate 2, so that the thinned wafer 10 can be soldered. It is disposed on the circuit substrate 2.

On the other hand, the power transistors T1, T2 of the thinned wafer 10 can pass through the source pads S1, S2, the gate pads G1, G2, and the source pads S1, S2 and the gate pads G1, respectively. The plurality of pads 21 and 22 of G2 are electrically connected to other functional wafers on the circuit substrate 2.

It should be noted that in order to make the electronic device as thin as possible, the circuit substrate 2 of the component P1 of the power chip-level package structure is also thinner and thinner. Therefore, the thickness of the circuit substrate 2 of the present embodiment may be less than 0.5 mm.

Since the thickness of the wiring substrate 2 is thin, it is easily bent, so that the thinned wafer 10 provided on the wiring substrate 2 is subjected to stress to be damaged or cracked. Therefore, the power chip package structure 1 of the present embodiment is provided with the conductive support member 11 on the back side 10b of the thinned wafer 10, which can reduce the probability that the thinned wafer 10 is damaged by the bending of the circuit substrate 2.

In the present embodiment, the conductive support 11 has a thickness of at least 50 μm. However, if the thickness of the conductive support member 11 is too thick, the total thickness of the component P1 of the power wafer level package structure is increased and the cost is increased. Accordingly, the thickness of the conductive support 11 can be greater than 50 μm and adjusted according to actual needs.

In summary, the present invention has the beneficial effects of the chip package structure 1 provided by the present invention and the component P1 of the power chip level package structure using the same, by "providing the conductive support member 11 on the back side of the thinned wafer 10, and The technique of thinning the ratio of the area of the back side surface of the wafer 10 to the area of the inner surface 11a of at least 0.5 and 1 "can increase the mechanical strength of the wafer package structure 1. When the chip package structure 1 is applied to the element P1, the conductive support member 11 can provide the support strength of the thinned wafer 10 to reduce the probability that the thinned wafer 10 on the circuit substrate 2 is damaged due to the bending of the circuit substrate 2.

In addition, the conductive support member 11 can reduce the resistance of the circuit when the power transistors T1, T2 operate, in addition to reducing the probability that the thinned wafer 10 is damaged or cracked by external stress. In addition, the conductive support 11 can also increase the heat dissipation path of the thinned wafer 10 to improve the heat dissipation efficiency of the thinned wafer 10 during operation.

The above disclosure is only a preferred and feasible embodiment of the present invention, and is not intended to limit the scope of the patent application of the present invention. Therefore, any equivalent technical changes made by using the present specification and the contents of the drawings are included in the application for this creation. Within the scope of the patent.

Claims (8)

A power chip package structure comprising: a thinned wafer having an active side and a back side opposite to the active side; and a conductive support material disposed on the back side of the thinned wafer The conductive support member has an inner surface facing the thinned wafer, and a ratio of an area of a back side surface of the thinned wafer to an area of the inner surface ranges from 0.5 to 1. The power chip package structure of claim 1, further comprising a conductive adhesive layer between the thinned wafer and the conductive support, and the conductive support passes the conductive A glue is secured to the back side of the thinned wafer. The power chip package structure of claim 2, wherein the conductive adhesive layer is a solder layer or a metal-containing adhesive layer. The power chip package structure of claim 1, wherein the thinned wafer has at least two power transistors connected in parallel with each other. The power chip package structure of claim 4, wherein each of the power transistors is connected in series with a diode. The power chip package structure of claim 4, further comprising: a back electrode located on a back side of the thinned wafer and electrically connected to two of the two power transistors pole. The power chip package structure of claim 1, wherein the thinned wafer has a thickness ranging from 50 μm to 125 μm. The power chip package structure of claim 1, wherein the conductive support has a thickness greater than or equal to 50 μm.