TWI701747B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device includes a substrate, a first semiconductor component, a second semiconductor component and an encapsulation component. The first semiconductor component includes a first metal pad facing the substrate. The second semiconductor component id disposed above the first semiconductor component in a stack direction and includes a base and a second metal pad. The second metal pad faces the first semiconductor component. The second semiconductor component is disposed between the first semiconductor component and the base in the stack direction. The encapsulation component covers the first semiconductor component.

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a stacked semiconductor device with no bonding wires and a manufacturing method thereof.

In order to electrically connect two semiconductor elements in a semiconductor device, bonding wires are usually used to connect the two semiconductor elements. However, wire bonding will cause parasitic inductance and parasitic resistance. These parasitic inductances and parasitic resistances are not expected during circuit design. Therefore, the parasitic elements in these semiconductor devices will affect the operation of these semiconductor devices. For example, the additional energy loss caused by the current passing through the parasitic resistance will affect the overall circuit Operational efficiency and parasitic inductances cause voltage overshoots when the semiconductor device is rapidly switched on and off, so that the semiconductor device is subjected to additional voltage, which affects the operating conditions of the semiconductor device. Therefore, semiconductor devices using bonding wires are not suitable for working at high frequencies.

Therefore, the present invention provides a semiconductor device and a manufacturing method thereof, which can improve the aforementioned problems.

According to an embodiment of the present invention, a semiconductor device is provided. The semiconductor device includes a carrier, a first semiconductor element, a second semiconductor element and a glue material. The first semiconductor device includes a first metal pad facing the carrier. The second semiconductor element is arranged above the first semiconductor element along a stacking direction and includes a substrate and a second metal pad. The second metal pad faces the first semiconductor element, and the second metal pad is located between the first semiconductor element and the substrate along the stacking direction. The glue material covers the first semiconductor element.

According to another embodiment of the present invention, a method of manufacturing a semiconductor device is provided. The manufacturing method includes the following steps. Along a stacking direction, a first semiconductor element and a second semiconductor element are connected, wherein the first semiconductor element includes a first metal pad, the second semiconductor element includes a substrate and a second metal pad, and the second metal pad faces The first semiconductor element and the second metal pad are located between the first semiconductor element and the substrate along the stacking direction; the first semiconductor element and the second semiconductor element are arranged on a carrier; and a glue is formed to cover the first Semiconductor components.

In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are given in conjunction with the accompanying drawings to describe in detail as follows:

Please refer to FIGS. 1A and 1B. FIG. 1A shows a top view of the semiconductor device 100 according to an embodiment of the present invention (the heat sink 150 is not shown), and FIG. 1B shows the semiconductor device 100 in FIG. 1A along the line 1B. Sectional view of -1B'.

The semiconductor device 100 includes a carrier 110, a first semiconductor element 120, a second semiconductor element 130, a glue 140, a heat sink 150, a fifth metal pad 134 and a sixth metal pad 135.

The carrier 110 has an upper surface 110u and a lower surface 110b opposite to each other and includes a first upper pad 111, a second upper pad 112, a third upper pad 113, a first lower pad 114, a second lower pad 115, The third bottom pad 116 and a plurality of conductive holes 117. The first upper pad 111, the second upper pad 112, and the third upper pad 113 are located on the upper surface 110u, and the first lower pad 114, the second lower pad 115, and the third lower pad 116 are located on the lower surface 110b . Each conductive hole 117 extends from the upper surface 110u to the lower surface 110b, and is electrically connected to the corresponding upper and lower pads.

The first semiconductor device 120 and the second semiconductor device 130 can pass through the upper pads (first upper pad 111, second upper pad 112, and third upper pad 113), conductive holes 117 and lower pads of the carrier 110 (The first bottom pad 114, the second bottom pad 115, and the third bottom pad 116) are electrically connected to external electronic components, such as a circuit board.

The first semiconductor device 120 includes a first metal pad 121 facing the carrier 110 and a third metal pad 122 away from the carrier 110. The second semiconductor element 130 is disposed above the first semiconductor element 120 along a stacking direction P1 and includes a substrate 131, a semiconductor layer 132 and a second metal pad 133. The second metal pad 133 faces the first semiconductor device 120, and the second metal pad 133 is located between the first semiconductor device 120 and the substrate 131 along the stacking direction P1. Since the first semiconductor element 120 and the second semiconductor element 130 are electrically connected by the third metal pad 122 and the second metal pad 133, the problem of parasitic inductance caused by the bonding wire can be avoided. In this way, the parasitic inductance of the semiconductor device 100 of the embodiment of the present invention is small, and is suitable for working at high frequencies.

In addition, compared to the connection through the bonding wire, the connection through the metal pad provides a shorter electrical transmission path, allowing the electrical signal to be transmitted between the first semiconductor element 120 and the second semiconductor element 130 more quickly.

As shown in Figure 1B, the second semiconductor element 130 is located above the first semiconductor element 120, so even if the second semiconductor element 130 generates higher heat than the first semiconductor element 120, the heat generated by the second semiconductor element 130 can be transferred upward to Heat dissipation member 150. The heat sink 150 can exchange heat with the external environment through conduction, natural or forced convection.

As shown in FIG. 1B, the heat sink 150 is disposed on the second semiconductor element 130 and above the second semiconductor element 130. The heat dissipation element 150 preferably has excellent thermal conductivity, so that the heat of the second semiconductor element 130 can be transferred in the heat dissipation element 150 more quickly, and then escapes to the external environment through the heat dissipation element 150. The heat dissipation member 150 is, for example, a heat dissipation fin. The semiconductor device 100 further includes a thermal conductive glue 155 which can be disposed between the heat sink 150 and the second semiconductor device 130 to bond the heat sink 150 and the second semiconductor device 130. The heat sink 150 includes a carrier board 151 and at least one heat sink 152, wherein the heat sink 152 is connected to the carrier board 151. The carrier 151 is bonded to the second semiconductor element 130 through the thermally conductive adhesive 155. In one embodiment, the thermal conductive adhesive 155 is selected from diamond material (Diamond), aluminum nitride (AlN), silicon carbide (SiC) or other transparent or translucent materials with high thermal conductivity.

In one embodiment, the first semiconductor device 120 is, for example, a transistor. The first semiconductor element 120 may be a low voltage metal-oxide-semiconductor field-effect transistor (LV MOSFET), such as a silicon-based low-voltage metal-oxide field-effect transistor (Si-based LV MOSFET). MOSFET). In addition, the first semiconductor element 120 may also be an enhanced metal oxide semi-field effect transistor (E-mode MOS). In one embodiment, the second semiconductor element 130 is a high electron mobility transistor (HEMT), for example, a gallium nitride-based high electron mobility transistor (GaN-based HEMT), However, the embodiment of the present invention is not limited by this. More specifically, please refer to the description in paragraph [00020] for the materials contained in the GaN-based HEMT (GaN-based HEMT). In addition, the second semiconductor element 130 may also be a depletion type high electron mobility crystal transistor (D-mode HEMT).

As shown in FIG. 1B, the first semiconductor device 120 includes a first metal pad 121, a third metal pad 122, a fourth metal pad 123, and a semiconductor layer 124. The first metal pad 121, the third metal pad 122, and the fourth metal pad The metal pad 123 is formed on the semiconductor layer 124. The first metal pad 121 and the third metal pad 122 are located on one side of the semiconductor layer 124, and the third metal pad 122 is located on the opposite side of the semiconductor layer 124. As shown in the figure, the third metal pad 122 is butted with the second metal pad 133 of the second semiconductor element 130, and the fourth metal pad 123 faces the carrier board 110 and is electrically connected to the second upper pad 112 and the carrier board 110. The second lower pad 115. In an embodiment, the material of the first metal pad 121 includes gold, copper, silver or a combination thereof. The materials of the third metal pad 122 and the fourth metal pad 123 are similar to the first metal pad 121. The material of the semiconductor layer 124 includes silicon.

The first metal pad 121 may be one of the source, drain, and gate, the third metal pad 122 may be the other of the source, drain, and gate, and the fourth metal pad 123 may be the source, The other of drain and gate. In this embodiment, the first metal pad 121, the third metal pad 122, and the fourth metal pad 123 are illustrated by using the source electrode, the drain electrode and the gate electrode respectively, but the embodiment of the present invention is not limited thereto.

As shown in FIG. 1B, the semiconductor device 100 includes a first adhesive layer 160, which can bond the third metal pad 122 and the second metal pad 133. The first adhesive layer 160 has conductivity, and therefore can provide an electrical transmission path between the third metal pad 122 and the second metal pad 133. In one embodiment, the first adhesive layer 160 is, for example, silicone resin.

As shown in FIG. 1B, the second semiconductor device 130 includes a seventh metal pad 136 and an eighth metal pad 137. The seventh metal pad 136 and the eighth metal pad 137 are located on the lower surface 130 b of the second semiconductor device 130. The fifth metal pad 134 is located between the seventh metal pad 136 and the carrier board 110 and is electrically connected to the seventh metal pad 136 and the carrier board 110. The sixth metal pad 135 is located between the eighth metal pad 137 and the carrier board 110 and is electrically connected to the eighth metal pad 137 and the carrier board 110. In one embodiment, the aforementioned substrate 131 is, for example, sapphire (sapphire), gallium nitride, silicon carbide (SiC) or silicon wafer cut, and the material of the semiconductor layer 132 includes gallium nitride, aluminum gallium nitride, and Aluminum or indium gallium nitride, and the material of the second metal pad 133, the seventh metal pad 136 and the eighth metal pad 137 includes gold, copper, silver or a combination thereof.

In this embodiment, the fifth metal pad 134 and the sixth metal pad 135 are solder balls. Compared with the wire, the parasitic inductance generated by the solder ball is lower. In this way, the parasitic inductance of the semiconductor device 100 of the embodiment of the present invention is small, and is suitable for working at high frequencies. Since the fifth metal pad 134 and the sixth metal pad 135 are directly connected to the second semiconductor element 130 and the carrier 110, the heat of the second semiconductor element 130 can also be conducted to the carrier through the fifth metal pad 134 and the sixth metal pad 135 110, and then conduction to the outside of the semiconductor device 100 through the upper pads, conductive holes, and lower pads of the carrier 110. Compared with the bonding wire, the solder ball has a larger cross-sectional area, so it can absorb and conduct more heat generated by the first semiconductor element 120 and the second semiconductor element 130 in the same time, and pass through the heat sink 150 and the carrier. The board 110 exchanges heat with the external environment to achieve the effect of improving heat dissipation efficiency.

In addition, the second metal pad 133, the seventh metal pad 136 and the eighth metal pad 137 of the second semiconductor element 130 can be used as the source, drain, and gate of the second semiconductor element 130, respectively, as required. In this embodiment, the second metal pad 133, the seventh metal pad 136, and the eighth metal pad 137 are illustrated by using the source electrode, the gate electrode and the drain electrode respectively, but the embodiment of the present invention is not limited thereto.

As shown in FIG. 1B, the seventh metal pad 136 and the first metal pad 121 are jointly arranged on the first upper pad 111 of the carrier 110 to be electrically connected through the first upper pad 111 and through the conductive hole 117 It is electrically connected to the first lower pad 114. The fourth metal pad 123 is electrically connected to the second upper pad 112. The eighth metal pad 137 is electrically connected to the third upper pad 113. In this way, the signals of the first semiconductor device 120 and the second semiconductor device 130 can be transmitted to the electronic components outside the semiconductor device 100 through the upper pads, through the conductive holes 117 and the lower pads, or external signals can pass through these The lower pads, the conductive holes 117 and the upper pads are transmitted to the inside of the semiconductor device 100.

As shown in FIG. 1B, the semiconductor device 100 includes a second adhesive layer 165 and a third adhesive layer 170. The second adhesive layer 165 can bond the first metal pad 121 and the first upper pad 111, and the third adhesive layer 170 can bond the fourth metal pad 123 and the second upper pad 112. The second adhesive layer 165 and the third adhesive layer 170 have conductivity. In one embodiment, the material of the second adhesive layer 165 and the third adhesive layer 170 is, for example, silicone resin.

As shown in FIG. 1A, the connection line between the fifth metal pad 134 and the sixth metal pad 135 is approximately parallel to the diagonal of the second semiconductor element 130 or approximately two diagonally adjacent to each other. In this way, the second semiconductor device 130 can be stably stacked on the carrier 110 through the fifth metal pad 134 and the sixth metal pad 135. The relative positions of the fifth metal pad 134, the sixth metal pad 135 and the second metal pad 133 of the second semiconductor element 130 are not limited by FIG. 1A, and can be adjusted appropriately.

As shown in FIG. 1B, the adhesive material 140 is formed between the first semiconductor element 120 and the second semiconductor element 130, and is used as an underfill to fill the semiconductor device to prevent these metal pads from being exposed to the environment. Damage, such as oxidation. As shown in the figure, the adhesive material 140 covers the first semiconductor element 120, the fifth metal pad 134, the sixth metal pad 135, the second metal pad 133, the seventh metal pad 136, and the eighth metal pad of the second semiconductor element 130. 137 and the first upper pad 111, the second upper pad 112 and the third upper pad 113 of the carrier board 110.

Please refer to FIG. 1C, which shows an equivalent circuit diagram of the semiconductor device 100 in FIG. 1A. The second metal pad 133, the seventh metal pad 136, and the eighth metal pad 137 in FIG. 1B are used as the source S1, the gate G1, and the drain D1 of the second semiconductor element 130, respectively, and the first metal pad in FIG. 1B 121, the fourth metal pad 123, and the third metal pad 122 are used as the source S2, the gate G2, and the drain D2 of the first semiconductor device 120, respectively. The first bottom pad 114 and the second bottom pad 114 of FIG. 1B The gate of the pad 115 and the third bottom pad 116 are the source S, the gate G, and the drain S of the overall circuit, respectively.

Please refer to FIG. 2, which shows a cross-sectional view of a semiconductor device 200 according to another embodiment of the present invention. The semiconductor device 200 includes a carrier 110, a first semiconductor element 120, a second semiconductor element 130, a glue 140, a heat sink 250, a fifth metal pad 134 and a sixth metal pad 135. Compared with the semiconductor device 100, the semiconductor device 200 has the heat sink 250 as a cover, which can completely cover the first semiconductor element 120, the second semiconductor element 130, and the glue 140, wherein the glue 140 can cover the heat sink. All of the wall surfaces 250 s that are not in contact with the second semiconductor element 130 in 250. In another embodiment, the glue 140 may only contact a part of the wall surface 250s. In addition, the heat sink 250 is, for example, a metal cover.

Please refer to FIGS. 3A to 3F, which illustrate the manufacturing process diagram of the semiconductor device 100 in FIG. 1A.

As shown in FIG. 3A, a first semiconductor element 120 and a second semiconductor element 130 are provided. The first semiconductor device 120 includes a first metal pad 121, a third metal pad 122, a fourth metal pad 123, and a semiconductor layer 124. The third metal pad 122 and the fourth metal pad 123 are located on the same side of the semiconductor layer 124, and the The three metal pads 122 are located on the opposite side of the semiconductor layer 124. The second semiconductor device 130 includes a second metal pad 133, a seventh metal pad 136, and an eighth metal pad 137. The second metal pad 133, the seventh metal pad 136 and the eighth metal pad 137 are all located on the second semiconductor device 130. Same side. The fifth metal pad 134 and the sixth metal pad 135 are formed on the second semiconductor element 130 by coating, such as printing. The material of the fifth metal pad 134 and the sixth metal pad 135 is, for example, a tin-antimony alloy. The fifth metal pad 134 and the sixth metal pad 135 may be formed on the seventh metal pad 136 and the eighth metal pad 137 of the second semiconductor device 130 by coating technology after the second semiconductor device 130 is formed.

Then, the third metal pad 122 of the first semiconductor device 120 and the second metal pad 133 of the second semiconductor device 130 are connected to each other along the stacking direction P1. As shown in the figure, in the docking step, the second semiconductor element 130 is located below the first semiconductor element 120, so that the first semiconductor element 120 with a smaller area (top view area) is arranged downward on the second semiconductor element with a larger area (top view area). The second semiconductor element 130 can improve the success rate of docking.

Then, as shown in Figures 3B1 and 3B2, Figure 3B2 shows a cross-sectional view of the structure of Figure 3B1 along the direction 3B2-3B2'. After stacking, the second metal pad 133 of the second semiconductor element 130 faces the first semiconductor element 120, and the second metal pad 133 is located between the first semiconductor element 120 and the third metal pad 122 along the stacking direction P1. As shown in the figure, the second metal pad 133 and the third metal pad 122 can be bonded through the first adhesive layer 160.

As shown in FIG. 3C, a reflow process is used to heat the stacked first semiconductor device 120 and the second semiconductor device 130. After heating, the fifth metal pad 134 and the sixth metal pad 135 transform into a high-temperature flow state and condense into a spherical shape. After cooling, the fifth metal pad 134 and the sixth metal pad 135 in the high temperature flow state solidify. The height of the spherical fifth metal pad 134 and the sixth metal pad 135 is increased, and the height of the apex is approximately the same as or higher than the first metal pad 121 and the fourth metal pad 123 of the first semiconductor element 120. The pad 121 and the fourth metal pad 123 can avoid stacking the second semiconductor element 130 on the carrier (for example, stacking the second semiconductor element 130 on the carrier 110 in a subsequent step), the first semiconductor element 120 and the carrier The board 110 affects the bonding, and can ensure that the fifth metal pad 134 and the sixth metal pad 135 can actually contact the carrier board 110. In one embodiment, the height of the apex of the fifth metal pad 134 and the sixth metal pad 135 is slightly lower than that of the first metal pad 121 and the fourth metal pad 123, and when the semiconductor elements 120 and 130 are bonded to the carrier 110 Conductive materials such as solder are added between the fifth metal pad 134 and the sixth metal pad 135 and the carrier 110 to ensure electrical connection between the carrier 110 and the second semiconductor element 130 and the first semiconductor element 120.

In addition, after heating, the first adhesive layer 160 transforms into a high temperature flow state to bond the third metal pad 122 and the second metal pad 133. The first adhesive layer 160 with high temperature flow state is cooled and solidified to tightly bond the third metal pad 122 and the second metal pad 133.

Then, as shown in FIG. 3D, the stacked first semiconductor device 120 and the second semiconductor device 130 are turned over so that the fifth metal pad 134, the sixth metal pad 135, the first metal pad 121 and the fourth metal pad 123 face So as to facilitate the docking of the carrier board 110 in the subsequent steps. The flip mode can be flipped left and right, or flipped back and forth. As long as the fifth metal pad 134, the sixth metal pad 135, the first metal pad 121, and the fourth metal pad 123 can face downward, the embodiment of the present invention does not limit the inversion method.

Then, as shown in FIG. 3E, the structure of FIG. 3D is placed on the carrier 110. Since the fifth metal pad 134, the sixth metal pad 135, the first metal pad 121, and the fourth metal pad 123 face downward, the fifth metal pad 134, the sixth metal pad 135, the first metal pad 121, and the fourth metal pad 123 is respectively butted to the first upper pad 111, the third upper pad 113, the first upper pad 111 and the second upper pad 112 with the carrier board 110 facing upward.

As shown in FIG. 3E, the first metal pad 121 and the first upper pad 111 can be bonded through the second adhesive layer 165, and the fourth metal pad 123 and the second upper pad 112 can be bonded through the third adhesive layer 170. The second adhesive layer 165 and the third adhesive layer 170 have conductivity.

Then, heat the first semiconductor element 120, the second semiconductor element 130, and the carrier 110 through heating methods such as reflow, so that the fifth metal pad 134 and the first upper pad 111, and the first metal pad 121 and the first upper pad are heated. The pad 111, the fourth metal pad 123 and the second upper pad 112, and the sixth metal pad 135 and the third upper pad 113 are tightly combined.

As shown in FIG. 3F, the glue material 140 can be formed between the first semiconductor device 120 and the second semiconductor device 130 by dispensing. The glue 140 covers the first semiconductor element 120, the fifth metal pad 134, the sixth metal pad 135, the second metal pad 133 of the second semiconductor element 130, and the first upper pad 111 and the second upper pad of the carrier 110 Pad 112 and the third upper pad 113.

Then, the heat sink 150 as shown in FIG. 1B is disposed on the second semiconductor element 130 to complete the semiconductor device 100 as shown in FIG. 1B.

The manufacturing process of the semiconductor device 200 in FIG. 2 is that after the steps in FIG. 3E, the heat sink 250 shown in FIG. 2 is arranged on the carrier 110 and covers the first semiconductor element 120 and the second semiconductor element 130. Then, the glue 140 is formed to fill the internal space of the heat sink 250 by dispensing glue.

In summary, although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those who have ordinary knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

100、200‧‧‧Semiconductor device 110‧‧‧Carrier board 110b, 130b‧‧‧Bottom surface 110u‧‧‧Upper surface 111‧‧‧First upper pad 112‧‧‧Second upper pad 113‧‧‧ The third upper pad 114‧‧‧The first lower pad 115‧‧‧The second lower pad 116‧‧‧The third lower pad 117‧‧‧Conducting hole 120‧‧‧The first semiconductor element 121‧‧‧ The first metal pad 122‧‧‧The third metal pad 123‧‧‧The fourth metal pad 124,132‧‧‧Semiconductor layer 130‧‧‧Second semiconductor element 131‧‧‧Substrate 133‧‧‧Second metal pad 134 ‧‧‧The fifth metal pad 135‧‧‧The sixth metal pad 136‧‧‧The seventh metal pad 137‧‧‧The eighth metal pad 140‧‧‧Adhesive 150,250 Plate 152‧‧‧Heat sink 155‧‧‧Thermal glue 160‧‧‧First adhesive layer 165‧‧‧Second adhesive layer 170‧‧‧Third adhesive layer 250s‧‧‧Wall D, D1, D2‧‧‧ Drain G, G1, G2‧‧‧Gate S, S1, S2‧‧‧Source P1‧‧‧Stacking direction 1B-1B'‧‧‧Line segment

FIG. 1A is a top view of a semiconductor device (the heat sink is not shown) according to an embodiment of the invention. FIG. 1B shows a cross-sectional view of the semiconductor device of FIG. 1A along the direction 1B-1B'. FIG. 1C is an equivalent circuit diagram of the semiconductor device of FIG. 1A. FIG. 2 is a cross-sectional view of a semiconductor device according to another embodiment of the invention. Figures 3A to 3F show the manufacturing process diagrams of the semiconductor device of Figure 1A.

100‧‧‧Semiconductor device

110‧‧‧Carrier Board

110b, 130b‧‧‧lower surface

110u‧‧‧Upper surface

111‧‧‧First upper pad

112‧‧‧Second upper pad

113‧‧‧The third upper pad

114‧‧‧First bottom pad

115‧‧‧Second lower pad

116‧‧‧The third bottom pad

117‧‧‧Conductive hole

120‧‧‧First Semiconductor Device

121‧‧‧The first metal pad

122‧‧‧The third metal pad

123‧‧‧The fourth metal pad

130‧‧‧Second semiconductor element

131‧‧‧Substrate

132‧‧‧Semiconductor layer

133‧‧‧Second metal pad

134‧‧‧The fifth metal pad

135‧‧‧The sixth metal pad

140‧‧‧Glue

150‧‧‧Radiator

155‧‧‧Heat Conductive Adhesive

160‧‧‧First adhesive layer

165‧‧‧Two bonding layer

170‧‧‧Third adhesive layer

P1‧‧‧Stacking direction

Claims (10)

A semiconductor device includes: a carrier board; a first semiconductor element, including a first metal pad and a third metal pad, the first metal pad faces the carrier board; a second semiconductor element arranged along a stacking direction Above the first semiconductor element and including a substrate and a second metal pad, the second metal pad faces the first semiconductor element, and the second metal pad is located between the first semiconductor element and the substrate along the stacking direction And a glue material covering the first semiconductor element, wherein the second metal pad is butted with the third metal pad. According to the semiconductor device described in item 1 of the scope of patent application, the adhesive material is in direct contact with the second metal pad. The semiconductor device described in claim 1, wherein the first semiconductor device further includes a fourth metal pad, and the fourth metal pad and the first metal pad are located on the same side of the first semiconductor device and face parallel It is electrically connected to the carrier board. The semiconductor device described in item 1 of the scope of the patent application further includes a fifth metal pad connecting the lower surface of the second semiconductor device and the carrier board. The semiconductor device described in item 1 of the scope of patent application includes: A heat sink is arranged on the first semiconductor element. A method for manufacturing a semiconductor device includes: butting a first semiconductor element and a second semiconductor element along a stacking direction, wherein the first semiconductor element includes a first metal pad and a third metal pad, and the second semiconductor The device includes a substrate and a second metal pad, the second metal pad faces the first semiconductor device, and the second metal pad is located between the first semiconductor device and the substrate along the stacking direction; the docked configuration The first semiconductor element and the second semiconductor element are on a carrier board; and a glue material is formed to cover the first semiconductor element, wherein the second metal pad is butted with the third metal pad. According to the manufacturing method described in claim 6, wherein in the step of butting the first semiconductor element and the second semiconductor element along the stacking direction, the second semiconductor element is located below the first semiconductor element. According to the manufacturing method described in item 6 of the scope of patent application, the glue material is in direct contact with the second metal pad. According to the manufacturing method described in claim 6, wherein the first semiconductor device further includes a fourth metal pad and the first metal pad are located on the same side of the first semiconductor device. The manufacturing method described in item 6 of the scope of the patent application further includes a fifth metal pad formed by coating and in the step of connecting the first semiconductor element and the second semiconductor element Then heat the fifth metal pad.

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