JP2007053148A - Semiconductor module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce thermal resistance of a semiconductor module of a flip-chip connection type. <P>SOLUTION: A joining member only for heat dissipation which does not exchange electric signals is formed in a range overlapping a MOSFET region. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor module, and more particularly to a semiconductor module such as a power amplifier used in a so-called wireless communication field for exchanging high-frequency signals wirelessly.

  Semiconductor modules such as power amplifiers used in mobile phones, etc., reduce the occupied area because the number of functions and parts to be mounted is greatly increased despite the fact that the housing dimensions of mobile phones do not change much The market demand is always working. For this reason, the dimensions of semiconductor modules that perform the same work continue to decrease with time, and the electrical efficiency has also improved, but in general, the trend toward smaller dimensions tends to improve efficiency. Since the semiconductor modules that transmit radio waves with the same output tend to have the same or lower value, the heat generation density tends to increase.

  For example, as one method for reducing the occupied area, a semiconductor chip is formed by forming a bonding member called a bump using metal or solder on the main surface (element forming surface) of the semiconductor chip and directly bonding it to the wiring board. The number of so-called flip-chip connection type modules for mounting the IC has increased. In flip chip connection, the electrical connection between the semiconductor chip and the wiring board can be made within the area occupied by the semiconductor chip, so that the module can be downsized compared to conventional wire bonding connection type modules. There is.

  On the other hand, in the case of the flip chip connection as described above, the members that electrically and thermally connect the wiring board and the semiconductor chip are only bumps, and the total cross-sectional area of the bumps is much smaller than the area of the semiconductor chip. A lot of things. For this reason, even if a filling material called underfill or resin between chip substrates is filled in the area between the wiring board and the semiconductor chip without bumps, the thermal conductivity of the filling material is bumps. Since it is often an order of magnitude smaller than metal or solder, the filler is not very effective as a heat dissipation path for effectively transferring heat from the semiconductor chip to the wiring board. As a result, the surface including the active region of the semiconductor chip ( There is a problem that heat dissipation is more difficult than when mounting by the so-called face-up mounting method in which the element formation surface is directed to the side not facing the wiring substrate and the entire back surface of the semiconductor chip is bonded to the wiring substrate by a bonding member. .

  As a technique for improving the efficiency of the heat dissipation path from the flip-chip connected semiconductor chip to the wiring board, for example, a technique such as Patent Document 1 is disclosed.

Japanese Patent Laid-Open No. 11-26633

  FIG. 7 is a schematic cross-sectional view showing a schematic configuration of a conventional flip chip-connected semiconductor module, and FIG. 8 is a schematic plan view showing a schematic configuration of the semiconductor chip of FIG.

  7A is a schematic cross-sectional view at a position along the line cc ′ in FIG. 8, and FIG. 7B is a schematic cross-sectional view at a position along the line dd ′ in FIG. 8. FIG. 7 and 8 is a semiconductor chip in which a field effect transistor (MOSFET: Metal Oxide Semiconductor Field Effect Transistor) made of, for example, a metal oxide semiconductor is mounted in an active region as a power transistor. is there.

  As shown in FIGS. 7 and 8, in the conventional flip chip connection type semiconductor module, the material for physically connecting the active region 2 of the semiconductor chip 31 and the wiring substrate 33 is the above-mentioned filler. There are only 32. An electrical signal is transmitted to the electrode 4 located slightly away from the active region 2 by the internal wiring layer, and from there through the signal bump 5 (in the case of MOSFET, source, drain, gate), the wiring substrate 3. To be told. At this time, if the semiconductor chip 31 is formed of a silicon substrate, since silicon is a material having a relatively high thermal conductivity, heat is first diffused in the lateral direction in FIG. Then, heat is radiated to the wiring board 3 side through the signal bumps 5. The filler 32 also has an effect of transferring heat, but the degree of this effect is affected by the number, height, and cross-sectional area of the signal bumps 5. The smaller the total of the cross-sectional areas of the bumps, the more the filler 32 dissipates heat. On the other hand, if the total of the cross-sectional areas of the bumps is large, the filler 32 loses its importance as a heat dissipation path.

  In such a mounting structure, in any case, a long heat dissipation path in which heat is first diffused in the semiconductor chip 31 and then radiated to the wiring board 3 via the signal bumps 5 is used as a main heat dissipation path. As a result, the thermal resistance of the heat dissipation path rises, the temperature of the heat generation region near the gate electrode of the MOSFET rises beyond a predetermined range, the element is destroyed, or the protection circuit functions. There was a problem that the power supply of the element was cut off.

  An object of the present invention is to provide a method for reducing an increase in temperature of an element due to such a long heat dissipation path.

  The above-described problems can be solved by forming so-called bumps dedicated to heat dissipation that do not exchange electrical signals in the active region forming range of the semiconductor chip.

  According to the present invention, the temperature increase due to heat generation in the active region can be kept below a predetermined value, and deterioration of characteristics due to abnormal temperature increase and destruction of components due to heat can be prevented. A semiconductor module is obtained.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  In the first embodiment, an example in which the present invention is applied to a semiconductor module in which a semiconductor chip on which a MOSFET is mounted as a power transistor is mounted on a wiring board by a flip chip method will be described.

1 to 4 are diagrams related to a semiconductor module according to Embodiment 1 of the present invention.
1A and 1B are diagrams showing a schematic configuration of a semiconductor module (FIG. 1A is a schematic cross-sectional view at a position along the line aa ′ in FIG. 2, and FIG. 1B is a position along the line bb ′ in FIG. Schematic cross section at)
FIG. 2 is a schematic plan view showing a schematic configuration of the semiconductor chip of FIG.
FIG. 3 is a schematic cross-sectional view enlarging a part of FIG.
4A and 4B are diagrams showing the internal structure of the semiconductor chip of FIG. 2 (a is a schematic cross-sectional view in an active region, and (b) is a schematic cross-sectional view in an inactive region).

  As shown in FIGS. 1A and 1B, the semiconductor module of the first embodiment has a configuration in which the semiconductor chip 1 is mounted on the main surface of the wiring board 3 by the face-down method. As shown in FIG. 2, the semiconductor chip 1 has a rectangular planar shape that intersects the thickness direction. In the first embodiment, the semiconductor chip 1 is, for example, rectangular.

  The semiconductor chip 1 is mainly configured to have a semiconductor substrate and a thin film stack in which a plurality of insulating layers and conductive layers are stacked on the main surface of the semiconductor substrate. On the main surface of the semiconductor substrate, a field effect transistor (MOSFET) made of, for example, a metal oxide semiconductor is formed as a power transistor. This MOSFET has a configuration in which a plurality of fine transistor cells are connected in parallel in order to obtain high power. A region where such a power transistor is formed is called an active region (heat generation region) 2. In the first embodiment, the active region 2 is arranged in the center on the main surface side of the semiconductor chip 1 as shown in FIG.

  On the main surface (element formation surface) of the semiconductor chip 1, a plurality of electrodes 4 are arranged along the two sides (long sides in this embodiment) of the semiconductor chip 1 facing each other. The plurality of electrodes 4 are disposed at a position (between the side of the semiconductor chip 1 and the active region 2) that does not overlap the active region 2 in plan view. A plurality of connection pads 4 a are disposed on the main surface of the semiconductor chip 1. The plurality of connection pads 4 a are arranged at a position (on the active region 2) that overlaps the active region 2 in a plane, and are arranged along the same direction as the arrangement direction of the electrodes 4. A signal bump 5 is disposed on each electrode 4, and a heat dissipation bump 6 is disposed on each connection pad 4 a. These signal bumps 5 and heat radiation dedicated bumps 6 are formed on the main surface of the semiconductor chip 1 and the main surface of the wiring board 3 in the mounting process of the semiconductor chip 1 as shown in FIG. 1 ((a), (b)). It is interposed between.

  As shown in FIGS. 1A and 1B, the semiconductor chip 1 is mounted by a so-called face-down method in which an active region (heating region) 2 such as a MOSFET is mounted facing the wiring substrate 3 side. ing. In the case of a MOSFET, the signal bumps 5 connect the source, drain, and gate electrodes 4 to the wiring board 3. As the signal bump 5, a metal bump using a metal or an alloy such as gold (Au) or copper (Cu), a solder, or a solder bump configured by stacking them is used. As for the melting point of the signal bump 5, it is desirable to use a material having a melting point higher than the reflow temperature when the semiconductor module of the first embodiment is mounted on a larger substrate in the reflow process.

  Although not shown in FIG. 1 ((a), (b)), various conductive interlayer through-holes and wiring layers exist in the wiring board 3 connected to the signal bumps 5. The wiring pattern laid out on the back surface (the surface opposite to the main surface) and the layout of the electrode pattern on the larger substrate on which the semiconductor module of the first embodiment is mounted are electrically connected to form a semiconductor module. Demonstrate the function. The positional relationship of the electrode 4 for exchanging electrical signals with the active region 2 is as shown in FIG. 2, for example. The electrode 4 is arranged outside the range occupied by the active region 2, and the electrode 4 The signal bumps 5 are formed so as to be physically connected. Although not shown in FIG. 1 ((a), (b)), between the semiconductor chip 1 and the wiring substrate 3, a filler called an underfill or a resin between chip substrates is filled. There may be. In addition, the entire semiconductor chip 1 is often molded (sealed) with a molding material such as a resin together with other mounted components.

  In FIG. 1 ((a), (b)), the wiring board 3 is a multilayer wiring board such as a build-up board. However, the wiring board 3 is not necessarily a resin board, and is a glass-based or alumina-based ceramic substrate. Of course, the same resin substrate or a build-up substrate may be used. In the wiring substrate 3, a heat dissipation path for efficiently radiating heat generated as a loss in the semiconductor chip 1 (heat generated by driving the transistor element) to the back side of the substrate is formed. Hereinafter, this heat dissipation path is referred to as a heat dissipation via 8. The structure of the heat dissipation via 8 is that a through hole is formed by forming a through hole with a drill after the substrate 3 is formed, metal plating is applied to the side surface, and the remaining space is filled with a filler. There are various methods such as stacked vias that form heat-dissipating vias every time, but those that satisfy thermal resistance and reliability specifications and can be formed within the scope of cost target specifications. Any method may be used, however, in FIG. 1 ((a) and (b)), the through-hole method is shown as a representative.

  In the embodiment of the present invention shown in FIG. 1, a heat radiation exclusive bump 6 that does not exchange electrical signals is formed within the range occupied by the active region 2 in the semiconductor chip 1. Preferably, the heat-dissipating bumps 6 are formed by the same material and the same process as the signal-dedicated bumps 5, thereby reducing material and manufacturing costs. By disposing a heat radiation common solid wiring layer 7 as a heat radiation path on the surface (main surface) on the side of the wiring board 3 to which the heat radiation dedicated bump 6 is bonded, the heat radiation dedicated bumps 6 are transmitted discretely. The heat is once received by the heat radiation common solid wiring layer 7 and transferred to the heat radiation via 8 by heat conduction, so that the positions of the heat radiation dedicated bump 6 and the heat radiation via 8 do not coincide with each other in the plane (plane Even if they do not overlap, heat can be transferred well to the heat dissipation via 8 without increasing the temperature difference so much. The material for the heat radiation common solid wiring layer may be the same material as the electrode on the wiring board 3 side that receives the signal bump 5. Further, by providing the same heat radiation common solid wiring layer 7 on the back surface side of the wiring board 3 as well, it is possible to efficiently perform heat radiation to a larger board on which the semiconductor module of the first embodiment is mounted. However, these heat radiation common solid wiring layers 7 may be divided into a plurality of regions, and although the heat radiation effect is slightly reduced, even if there is no heat radiation common solid wiring layer 7, Obviously, it has little effect on the nature of the invention.

  Further, as a feature of the present invention, the heat dissipation dedicated via 6 does not exchange electrical signals between the semiconductor chip 1 and the wiring board 3. For this reason, as shown in FIG. 3, there may be an insulating layer 9 between the active region 2 and the heat-dissipating bump 6. Since the thickness of the insulating layer 9 is sufficiently thin compared to the area of the semiconductor chip 1, even if the insulating layer 9 is present, it is preferable to release heat to the heat radiation dedicated bump 6 rather than to release heat to the signal bump 5. This is effective for releasing heat generated in the active region 2 to the wiring board 3 side.

  On the other hand, the positional relationship of the heat-exclusive bump 6 and the signal-dedicated bump 5 will be described with reference to FIGS. 4 (a) and 4 (b). 4 (a) and 4 (b) are diagrams showing a case of MOSFET as a representative, and a semiconductor circuit layer is formed on a semiconductor substrate 10 such as silicon by an epitaxial growth method or the like. In FIG. 4 ((a), (b)), this layer is the Epi-Si layer 11, but it is not necessarily formed only of silicon, and may be a material such as SiGe or a compound semiconductor layer. . On this Epi-Si layer 11, a gate electrode 12, a gate wiring 12a, a source electrode 13, and a drain electrode 14 are formed using a metal wiring layer, polysilicon, or the like.

  Although the current flowing between the source and drain is controlled by the gate voltage, microscopically, the MOSFET generates heat in a region called a channel layer immediately below the gate electrode 12. Therefore, although the active region 2 itself is originally discrete, macroscopically, a large number of such regions are repeatedly arranged to form one or a small number of active regions 2 as a whole. The heat generated in the channel layer immediately below the gate electrode 12 is generated by the insulating film 15 and the connection pad via the gate, source and drain electrodes, the wirings connecting the electrodes to the outside of the semiconductor chip 1, and the insulating film 15 between the layers. It is transmitted to the surface of 4a. In the prior art, as shown in FIG. 8, the signal bumps 5 are often connected to positions away from the active region. The known technique shown in Patent Document 1 shows a method of forming a source electrode within a range occupied by the active region 2 and mounting it using a dedicated huge source electrode pad. Even if there is no problem in terms of heat dissipation, forming a pad with different thicknesses and materials to form a module mounting structure will be expensive in terms of manufacturing cost because the materials are different and the processes are different. However, in this embodiment, since the heat-dissipating bump 6 and the signal bump 5 can be formed by the same material, the same height, and the same process, there is an advantage that the cost can be reduced.

  Further, as shown in FIGS. 4A and 4B, the heat dissipation bumps 6 are formed on the surface (main surface) of the semiconductor chip 1 via the insulating film 15, whereas the signal bumps are formed. 5 is formed by being electrically connected to a circuit by a conductive penetrating material 17 penetrating the insulating film 15. Of course, as in Patent Document 1, even if all or a part of these gate, source, and drain electrodes and signal bumps 5 connected to the gate, source, and drain electrodes are disposed within the range occupied by the active region 2, it is the same from the viewpoint of heat dissipation. The effect of can be obtained. 4 (a) and 4 (b) are illustrated with the semiconductor substrate 10 on the bottom and the signal bumps 5 and the heat dissipation bumps 6 on the top, so-called face-down flip chip connection is shown. In this case, the semiconductor chip 1 is mounted on the wiring board 3 so that the top and bottom are reversed.

  FIGS. 1A and 1B show the case where one semiconductor chip 1 is mounted. Several other semiconductor chips 1 are stacked on the stack on the semiconductor chip 1. In this case, the semiconductor chip 1 having the largest heat generation amount is arranged on the side closest to the wiring substrate 3, and the heat generated from the semiconductor chip 1 having the large heat generation amount is disposed on the wiring substrate by using the heat radiation dedicated bumps 6. 3 is effective in suppressing the temperature rise of the semiconductor chip 1.

  In the first embodiment, the example in which the main active region (heat generation region) 2 is formed in the central portion of the main surface of the semiconductor chip 1 has been described. However, the present invention is not limited to this, for example, As shown in FIG. 9 (schematic plan view showing a schematic configuration of a semiconductor chip which is a modification of the first embodiment), the present invention can also be applied to a semiconductor chip 1a in which main active regions 2 are formed on both ends of the main surface. is there.

  In the second embodiment, an example in which the present invention is applied to a semiconductor module in which a semiconductor chip on which a heterojunction bipolar transistor (HBT) is mounted is mounted on a wiring board by a flip chip method will be described.

5 and 6 are diagrams relating to a semiconductor module which is Embodiment 2 of the present invention.
FIG. 5 is a schematic cross-sectional view showing a schematic configuration of a semiconductor module;
6 is a diagram showing a schematic configuration of the semiconductor chip of FIG. 5 ((a) is a schematic sectional view along the X direction, and (b) is a schematic sectional view along the Y direction orthogonal to the X direction). .

  In the second embodiment of the present invention shown in FIG. 5, heat radiation vias 18 a and electrodes 18 b are formed on the wiring board 3. The heat dissipating vias 18a and the electrodes 18b are wiring layers in which the front and back surfaces are made of a conductive / high heat conductive material such as copper plating, and the layers are electrically and thermally connected by a through-hole method or the like. It is. The heat generated in the collector layer of the bipolar transistor is transmitted to the emitter / heat dissipation bump 20 via the emitter wiring 19 to the heat dissipation via 18a and the electrode 18b, and finally the heat dissipation via 18a and the electrode 18b. To the outside of the wiring board 3. A semiconductor chip (hereinafter referred to as an HBT element) 21 on which a heterojunction bipolar transistor is mounted as a power transistor is not necessarily made of silicon, and may be a compound semiconductor such as gallium arsenide (GaAs). In particular, when gallium arsenide or the like having a lower thermal conductivity than silicon is used as the HBT element 21, it is important to create an effective heat dissipation path because the thermal resistance in the HBT element 21 tends to increase. In the present embodiment, the heat generated in the HBT element 21 can be directly released to the wiring substrate 3 through the emitter wiring 19, so that there is no effective heat dissipation path other than the bumps 5 and 20, and the flip chip connection method Even the HBT element 21 can efficiently dissipate heat without greatly increasing the thermal resistance.

  6 (a) and 6 (b) are cross-sectional views showing a part of the internal structure of the HBT element 21 of the present embodiment. As in FIGS. 4 (a) and 4 (b), a wiring board is shown. When mounted on 3, the mounting structure is upside down. As shown in FIGS. 6A and 6B, in this embodiment, heat is generated as a loss in the collector layer of the semiconductor substrate (and the emitter / base / collector layer) 22. When the wiring board 3 is mounted, the wiring board 3 comes to be above the emitter wiring 19, so that the heat diffusing the semiconductor substrate 22 is finally upward in FIG. 6 ((a), (b)). The heat is radiated to the wiring substrate 3 through the emitter / heat dissipation bumps 20 and the signal bumps 5 of FIG. 6 ((a) and (b)) and a filler such as underfill not shown in the figure. As an actual structure, in addition to the emitter electrode 26 and the emitter wiring 19, there are a collector electrode and wiring 23, a base electrode and wiring 24, but heat is generated in the collector region immediately below the emitter electrode. Since the distance to the collector electrode / collector wiring 23 is much larger than the distance to the emitter electrode 26 and the emitter wiring 19, the design of the heat radiation path via the emitter wiring 19 is very important at the time of flip-chip connection. The insulating layer 25 that is most likely to generate a temperature difference has a structure in which heat can be directly released in the thickness direction from a region where only the emitter wiring 19 generates heat in the case of the configuration shown in FIGS. Since the collector and base wirings are not shown in the figure and become longer as a heat dissipation path, it is effective to directly release the heat from the emitter wiring 19 again.

  As described above, the effects of the present invention have been described in the first and second embodiments. However, the heat generated in the active region 2 is efficiently generated by disposing the heat radiation bumps 6 or 20 in the range occupied by the active region 2. It can escape to the wiring board 3 side well. For this reason, in the semiconductor module of the present invention, the temperature increase due to heat generation in the active region 2 can be kept below a predetermined value, preventing deterioration of characteristics due to abnormal temperature increase and destruction of the component members due to heat, A highly reliable semiconductor module can be provided.

The figure which shows schematic structure of the semiconductor module which is Example 1 of this invention ((a) is typical sectional drawing in the position in alignment with the aa 'line of FIG. 2, (b) is bb' of FIG. It is a typical sectional view in a position along a line. FIG. 2 is a schematic plan view showing a schematic configuration of the semiconductor chip of FIG. 1. It is the typical sectional view which expanded a part of Drawing 1 (a). 2A and 2B are diagrams showing the internal structure of the semiconductor chip of FIG. 2 (a is a schematic cross-sectional view in an active region, and (b) is a schematic cross-sectional view in an inactive region). It is typical sectional drawing which shows schematic structure of the semiconductor module which is Example 2 of this invention. FIG. 6A is a schematic cross-sectional view taken along the X direction, and FIG. 6B is a schematic cross-sectional view taken along the Y direction. The figure which shows schematic structure of the conventional flip-chip-connected semiconductor module ((a) is typical sectional drawing in the position along the cc 'line of FIG. 8, (b) is the dd' line of FIG. It is typical sectional drawing in the position which follows. FIG. 8 is a schematic plan view showing a schematic configuration of the semiconductor chip of FIG. 7. It is a typical top view which shows schematic structure of the semiconductor chip which is a modification of Example 1 of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip, 2 ... Active area | region, 3 ... Wiring board, 4 ... Electrode, 4a ... Connection pad, 5 ... Signal bump, 6 ... Heat radiation exclusive bump, 7 ... Heat radiation common solid wiring layer, 8 ... Heat radiation Via ... 9 ... Insulating layer 10 ... Semiconductor substrate 11 ... Epi-Si layer 12 ... Gate electrode 12a ... Gate wiring 13 ... Source electrode / wiring 14 ... Drain electrode / wiring 15 ... Insulating film 17 ... Conductive penetrating material, 18a ... heat dissipation via, 18b ... electrode, 19 ... emitter wiring, 20 ... emitter / heat dissipation bump, 21 ... HBT element, 22 ... semiconductor substrate, 23 ... collector electrode and wiring, 24 ... base electrode and Wiring, 25 ... insulating layer, 26 ... emitter electrode.

Claims (5)

  In a flip-chip connection type semiconductor module in which an active region is formed on a main surface of a semiconductor substrate and the active region is bonded to a wiring substrate by a bonding member, the wiring is connected from the active region via a signal wiring. A semiconductor module comprising: a joining member that connects an electrical signal path to a substrate; and a joining member that includes a part thereof on a surface on which an active region is formed and does not form an electrical signal path . The semiconductor module according to claim 1,
A semiconductor module, wherein the semiconductor element formed on the semiconductor substrate is a field effect transistor made of a metal oxide semiconductor or a lateral diffusion metal oxide semiconductor. The semiconductor module according to claim 1,
A semiconductor module, wherein the joining member that forms the signal path and the joining member that does not form the signal path are formed through the same material and process.   In a flip-chip connection type semiconductor module in which an active region is formed on a main surface of a semiconductor substrate and the active region is bonded to a wiring substrate by a bonding member, the semiconductor substrate is a heterojunction bipolar transistor, Emitter wiring extending from the emitter fingers of the heterojunction bipolar transistor is made common to at least two or more transistors, and an electrical connection is made between the emitter wiring thus made common and the wiring electrode on the wiring board side by a joining member. Semiconductor module characterized by mechanical and thermal bonding. The semiconductor module according to claim 1,
In addition to the bonding member for connecting the source, drain, and gate signal, a fourth bonding member for connecting the semiconductor substrate and the wiring substrate is formed, and the fourth bonding member is an active region inside the semiconductor element. A semiconductor module characterized in that at least a part thereof overlaps in the plane.

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