JP2012199314A - Semiconductor device, printing apparatus, and manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the influence of the stress applied to bumps when the bumps arranged along the longitudinal direction are connected onto a common wiring pattern.SOLUTION: A semiconductor device of the present invention comprises a plurality of bumps connected to a common wiring line on a substrate. The plurality of bumps are arranged side by side along a predetermined direction. The plurality of bumps are formed so that at least a part of a cross-section of each of the plurality of bumps becomes a circular arc shape.

Description

  The present invention relates to a semiconductor device, a printing apparatus, and a manufacturing method.

  COF (COF: electrically connecting the semiconductor chip and the FPC) by collectively connecting electrodes called bumps formed on the semiconductor chip (IC) on a wiring pattern of a flexible printed circuit (FPC). Chip on Film) mounting technology is known. In the COF mounting technology, when the bonding pitch to be mounted is wide, compression is performed between the bump and the wiring pattern by sandwiching an anisotropic conductive film (ACF) between the FPC and the semiconductor chip and thermocompression bonding. When the formed particles have electrical conductivity and electrically connect them, and when the bonding pitch is narrow, metal eutectic by thermocompression represented by bonding of tin and gold, represented by bonding of gold and gold Ultrasonic metal bonding technology is known. The COF mounting technology is widely used in various precision devices such as a printing device, a mobile phone, and a liquid crystal display device.

JP 2003-303852 A

  The linear expansion coefficient is different between the FPC and the semiconductor chip. Generally, the FPC has a larger thermal expansion. For this reason, when both are thermocompression bonded, the FPC contracts more than the semiconductor chip after heat dissipation.

  On the other hand, there are cases where a plurality of bumps are arranged along the longitudinal direction of a rectangular semiconductor chip and these bumps are connected to a common wiring pattern of the FPC. In such a case, since the difference in the amount of expansion in the longitudinal direction during heating is large, a large stress is applied to the bumps along the wiring direction of the wiring pattern after heat dissipation. As a result, there is a possibility that a crack is generated in the connection portion or the semiconductor chip is deformed. Here, the connection portion refers to a connection portion between the FPC and the bump and a connection portion between the bump and the semiconductor chip, and the crack is generated in any of the connection portions and the protective film of the semiconductor chip.

  An object of the present invention is to reduce the influence of stress applied to bumps when connecting a plurality of bumps arranged along the longitudinal direction on a common wiring pattern.

  A main invention for achieving the above object includes a plurality of bumps to be connected to a common wiring of a substrate, and the plurality of bumps are arranged side by side along a predetermined direction, and the plurality of bumps The semiconductor device is characterized in that the plurality of bumps are formed so that at least a part of each of the cross sections thereof has an arc shape.

  Other features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

FIG. 1A is an explanatory diagram of a positional relationship between a wiring pattern and bumps. FIG. 1B is a side view of the semiconductor chip IC and the FPC. FIG. 1C is an explanatory diagram of the state of contraction during heat dissipation. FIG. 2A is an explanatory diagram of bumps of a comparative example. FIG. 2B is an explanatory diagram of an example of a bump according to the present embodiment. FIG. 3 is a block diagram of the configuration of the printer 1. FIG. 4 is a perspective view of the printer 1. FIG. 5 is a view of the head 41 as viewed from below. FIG. 6 is an explanatory diagram of the head controller HC. FIG. 7 is an explanatory diagram of various signals in the head controller HC. FIG. 8 is an explanatory diagram of a wiring pattern of a flexible printed circuit board (FPC) on which the head controller HC is mounted. FIG. 9 is an explanatory diagram of a wiring pattern at the mounting position of the head controller HC and bumps of the head controller HC. FIG. 10 is an explanatory diagram of wiring patterns and bumps according to the first modification. FIG. 11 is an explanatory diagram of wiring patterns and bumps of the second modification. FIG. 12 is an explanatory diagram of wiring patterns and bumps according to the third modification. FIG. 13 is an explanatory diagram of a wiring pattern and bumps of a fourth modification. FIG. 14 is an explanatory diagram of another embodiment of the wiring of the drive signal COM in the semiconductor chip. FIG. 15 is an explanatory diagram of another embodiment of a semiconductor chip and a wiring pattern. FIG. 16 is an explanatory diagram of still another embodiment of a semiconductor chip and a wiring pattern.

  At least the following matters will become clear from the description of the present specification and the accompanying drawings.

A plurality of bumps to be connected to a common wiring of the substrate, wherein the plurality of bumps are arranged side by side along a predetermined direction, and at least a part of a cross section of each of the plurality of bumps has an arc shape; Thus, the semiconductor device is characterized in that the plurality of bumps are respectively formed.
According to such a semiconductor device, the influence of the stress applied to the bump can be reduced.

  The plurality of bumps are preferably formed so that the cross section is elliptical. Thereby, generation | occurrence | production of a crack can be suppressed.

  The plurality of bumps are preferably formed so that the cross section has an elliptical shape in which the predetermined direction has a minor axis. Thereby, a deformation | transformation of a board | substrate can be suppressed.

  Preferably, the plurality of bumps are formed so that the cross section is circular. Thereby, generation | occurrence | production of a crack can be suppressed.

  It is desirable that the plurality of bumps are arranged in a staggered pattern along the predetermined direction. Thereby, stress can be disperse | distributed and generation | occurrence | production of a crack can be suppressed.

  It is desirable that the plurality of bumps be formed so that the cross-sectional area of the bump located on the outside increases. Thereby, the stress concerning the bump located outside can be suppressed and generation | occurrence | production of a crack can be suppressed more.

A substrate on which wiring for driving signals for driving a plurality of elements for ejecting ink is formed, and a semiconductor device for controlling application of the driving signals to each of the elements In the printer, the semiconductor device includes a plurality of bumps commonly connected to the wiring, and the plurality of bumps are arranged side by side along a direction of the wiring, and a cross section of each of the plurality of bumps The printer is characterized in that the plurality of bumps are formed so that at least a part of each of the bumps has an arc shape.
According to such a printing apparatus, the influence of the stress applied to the bump can be reduced.

A plurality of bumps arranged side by side in a predetermined direction, and a semiconductor device including the plurality of bumps formed so that at least a part of each cross section has an arc shape, and the semiconductor device are mounted The manufacturing method of the mounting substrate which has the process of preparing the board | substrate for this, and connecting by heating the said several bump to the common wiring of the said board | substrate becomes clear.
According to such a manufacturing method, the influence of the stress applied to the bump can be reduced.

=== Overview ===
FIG. 1A is an explanatory diagram of a positional relationship between a wiring pattern and bumps. The dotted lines in the figure indicate the position of the semiconductor chip IC (semiconductor device) and the position of the bump of the semiconductor chip IC to be disposed on the wiring pattern of the FPC (substrate). Thus, a plurality of bumps may be arranged along the wiring direction of the wiring pattern. The plurality of bumps are provided on the semiconductor chip IC so as to be arranged side by side along the wiring direction.

  FIG. 1B is a side view of the semiconductor chip IC and the FPC.

When connecting the FPC and the semiconductor chip IC, both are heat-pressed. In FPC, a copper wiring pattern as a conductor is formed on a polyimide film as an insulator. The linear expansion coefficient of the polyimide film is 22 × 10 ⁻⁶ (per 1 ° C.), and the linear expansion coefficient of copper is 16 8 × 10 ⁻⁶ (per 1 ° C.). On the other hand, the linear expansion coefficient of silicon constituting the semiconductor chip IC is 2.4 × 10 ⁻⁶ (per 1 ° C.). For this reason, the linear expansion coefficient of the FPC is larger than the linear expansion coefficient of the semiconductor chip IC.

  On the other hand, in this embodiment, as shown in FIG. 1A, both the semiconductor chip IC and the wiring pattern are elongated. For this reason, the difference in the linear expansion coefficient between the FPC and the semiconductor chip IC causes a large difference in the deformation amount (displacement amount) in the wiring direction during heating. At the time of thermocompression bonding between the FPC and the semiconductor chip IC, the FPC is fixed to the semiconductor chip IC via the bumps in a state where the FPC is greatly expanded in the wiring direction.

  Even if the expansion amounts of the two differ during heating, the plurality of bumps continue to be positioned on the wiring pattern, so that the bumps do not need to be detached from the wiring pattern and fixed at the time of heat pressing. This is an advantage of a configuration in which a plurality of bumps are arranged along the wiring direction. However, with such a configuration, the problem described below also occurs.

  FIG. 1C is an explanatory diagram of the state of contraction during heat dissipation. At the time of heat dissipation, the FPC contracts greatly with respect to the semiconductor chip IC. However, at the time of contraction, unlike heating, both are fixed through bumps. For this reason, when the FPC contracts more than the semiconductor chip IC, a large stress is applied to the bumps along the wiring direction of the wiring pattern. As a result, there is a risk that cracks may occur in the connection portion or the protective film of the semiconductor chip, or the semiconductor chip may be deformed.

  FIG. 2A is an explanatory diagram of bumps of a comparative example. According to the comparative example, the bump has a quadrangular prism shape. For this reason, the connection part of a bump and a wiring pattern becomes a square shape. In other words, in the comparative example, the cross-sectional shape of the bump in the plane parallel to the wiring pattern is a square shape. In the case of such a shape, when stress is applied in the wiring direction of the wiring pattern, stress concentration occurs at the corners of the bumps, and the connection portion between the FPC and the semiconductor chip IC or the connection portion between the bump and the semiconductor chip, There is a risk of cracks in the protective film.

  FIG. 2B is an explanatory diagram of an example of a bump according to the present embodiment. According to this embodiment, at least a part of the cross section of the bump has an arc shape. As a result, even if stress is applied in the wiring direction of the wiring pattern, stress concentration is unlikely to occur as in the comparative example, and the generation of cracks can be suppressed.

  Hereinafter, details of the present embodiment will be described in order.

=== Printer configuration ===
First, a printer using the semiconductor chip IC of this embodiment will be described.
FIG. 3 is a block diagram of the configuration of the printer 1. FIG. 4 is a perspective view of the printer 1.

  The printer 1 includes a controller 10, a transport unit 20, a carriage unit 30, a head unit 40, and a sensor group 50. The printer 1 that has received the print data from the computer 110 that is a print control apparatus controls each unit by the controller 10.

The controller 10 is a control device for controlling the printer 1. The controller 10 controls each unit according to a program stored in the memory 11. Further, the controller 10 controls each unit based on the print data received from the computer 110 and prints an image on the medium S. Various detection signals detected by the sensor group 50 are input to the controller 10.
The controller 10 includes a drive signal generation circuit 12. The drive signal generation circuit 12 includes a drive signal generation circuit 12 that generates a drive signal COM for driving a piezo element (described later). The driving signal COM of the driving signal generation circuit 12 and driving of the piezo elements will be described later.

  The transport unit 20 is a mechanism for transporting the medium S (for example, paper, film, etc.) in the transport direction. The transport direction is a direction that intersects the moving direction of the carriage 31.

  The carriage unit 30 is a mechanism for moving the carriage 31 in the movement direction. The carriage can reciprocate along the movement direction. The carriage 31 is provided with the head 41 of the head unit 40.

  The head unit 40 is for ejecting ink onto the medium S. The head unit 30 includes a head 41 and a head control unit HC for controlling the head 31. Various signals necessary for controlling the head 41 are sent from the controller 10 to the head unit 40 via the cable CBL.

  FIG. 5 is a view of the head 41 as viewed from below. The head 41 includes nozzle rows of six colors (black K, yellow Y, dark magenta DM, light magenta LM, dark cyan DC, and light cyan LC). The six nozzle rows are arranged along the movement direction of the carriage 31. Each nozzle row includes 180 nozzles that are ejection ports for ejecting ink. The 180 nozzles are arranged at an interval of 1/180 inch along the transport direction.

  Each nozzle is provided with an ink chamber (not shown) and a piezo element (reference numeral 47 in FIG. 6). By driving the piezo element, the ink chamber expands and contracts, and ink droplets are ejected from the nozzles. From each nozzle, a plurality of types of inks having different amounts can be ejected. Thereby, dots of different sizes can be formed on the paper.

  FIG. 6 is an explanatory diagram of the head controller HC. The head controller HC is a member configured as the above-described semiconductor chip IC.

  The head controller HC controls the application of the drive signal COM to the piezo elements 47 provided in the nozzles of the head 41. The head controller HC includes a first shift register 42A, a second shift register 42B, a first latch circuit 43A, a second latch circuit 43B, a signal selector 44, a control logic 45, and a switch 46. ing. Each part other than the control logic 45 of the head controller HC is provided for each piezo element 47 (in other words, for each nozzle). The control logic 45 includes a shift register group 452 that stores setting data SP and a selection signal generation unit 454 that generates selection signals q0 to q3 based on the setting data SP.

  A signal composed of a clock signal CLK, a latch signal LAT, a change signal CH, pixel data SI, and setting data SP is input from the controller 10 to the head controller HC via the cable CBL. In addition, the drive signal COM is input to the head controller HC from the drive signal generation circuit 12 of the controller 10 via the cable CBL.

  FIG. 7 is an explanatory diagram of various signals in the head controller HC.

  The drive signal COM is repeatedly generated every repetition period T. The repetition period T is a period required for the carriage 31 to move a distance of one pixel. Thus, every time the carriage 31 moves by a predetermined distance, the drive signal COM having the same waveform is repeatedly generated from the drive signal generation circuit 12. Each repetition period T can be divided into five sections T1 to T5. The first interval T1 includes the drive pulse PS1, the second interval T2 includes the drive pulse PS2, the third interval T3 includes the drive pulse PS3, and the fourth interval T4 includes the drive pulse PS4. Thus, the drive signal COM is generated so that the fifth interval T5 includes the drive pulse PS5. The waveforms of the drive pulses PS1 to PS5 are determined based on the operation that the piezo element 47 performs.

  The latch signal LAT is a signal that defines the repetition period T. The pulse signal of the latch signal LAT is output every time the carriage 31 moves a predetermined distance. The change signal CH is a signal for dividing the repetition period T into five sections T1 to T5. The selection signals q0 to q3 are signals output from the selection signal generation unit 454. The selection signal generation unit 454 determines the L level or the H level in each of the five sections T1 to T5 of the selection signals q0 to q3 based on the setting signal SP, and outputs the selection signals q0 to q3. The applied signal applied to the piezo element 47 has a different waveform according to the content of the pixel data corresponding to each piezo element 47. The pixel data is data indicating the dot size to be formed in each pixel, and here is 2-bit data.

  Next, an operation until an application signal is applied to the piezo element 47 by the head controller HC will be described.

  When the setting data SP and the pixel data SI are input to the head controller HC in synchronization with the clock CLK, the lower bit data of the pixel data, which is 2-bit data, is set in the first shift register 42A, and the upper bit data is The setting data SP is set in the shift register group 452 of the control logic 45, respectively, in the second shift register 42B. Then, in accordance with the pulse of the latch signal LAT, the lower bit data is latched by the first latch circuit 43A, the upper bit data is latched by the second latch circuit 43B, and the setting data SP is latched by the selection signal generator 454. .

  The signal selection unit 44 selects one of the selection signals q0 to q3 according to the 2-bit pixel data latched by the first latch circuit 43A and the second latch circuit 43B. When the pixel data is [00] (when the lower bit is [0] and the upper bit is [0]), the selection signal q0 is selected, and when the pixel data is [01], the selection signal q1 is selected. When the pixel data is [10], the selection signal q2 is selected, and when the pixel data is [11], the selection signal q3 is selected. The signal selection unit 44 outputs the selected selection signal to the switch 46 as the switch signal SW.

  A drive signal COM and a switch signal SW are input to the switch 46. When the switch signal SW is at the H level, the switch 46 is turned on and the drive signal COM is applied to the piezo element 47. When the switch signal SW is at the L level, the switch 46 is turned off and the drive signal COM is not applied to the piezo element 47.

  When the pixel data is [00], the switch 46 is turned ON / OFF by the selection signal q0, the drive pulse PS1 of the drive signal COM is applied to the piezo element 47, and the piezo element 47 is driven by the drive pulse PS1. As a result, pressure fluctuations that do not eject ink occur in the ink in the chamber, and the ink meniscus (the free surface of the ink exposed at the nozzle portion) vibrates slightly.

  When the pixel data is [01], the switch 46 is turned ON / OFF by the selection signal q1, the drive pulse PS3 of the drive signal COM is applied to the piezo element 47, and the piezo element 47 is driven by the drive pulse PS3. As a result, a small ink droplet of 2.5 pl is ejected from the nozzle, and a small dot is formed on the medium S.

  When the pixel data is [10], the switch 46 is turned ON / OFF by the selection signal q2, the drive pulse PS2 of the drive signal COM is applied to the piezo element 47, and the piezo element 47 is driven by the drive pulse PS2. As a result, 7 pl medium ink droplets are ejected from the nozzles, and medium dots are formed on the medium S.

  When the pixel data is [11], the switch 46 is turned on / off by the selection signal q3, the drive pulses PS2, PS4 and PS5 of the drive signal COM are applied to the piezo element 47, and the piezo element 47 is driven by these drive pulses. To do. As a result, a large ink droplet of 21 pl is ejected, and a large dot is formed on the medium S.

  By the way, the drive signal COM drives the piezo element 47, and thus becomes a high voltage / current signal unlike other signals (for example, the clock signal CLK and the latch signal LAT). For this reason, if there is only one input portion of the drive signal COM, the wiring between at least one of the 180 switches 46 and the input portion becomes long, and driving is performed with the wiring width in the semiconductor chip. It becomes difficult to supply the signal COM. Or, if there is only one input portion of the drive signal COM, if the drive signal COM is supplied to all the switches 48, the wiring in the semiconductor chip may be damaged, and the life of the head controller HC may be shortened. .

  Therefore, in the present embodiment, a plurality of bumps are formed on the semiconductor chip constituting the head control unit HC, and the drive signal COM is supplied from each bump. Specifically, one bump is provided for 10 to 20 piezo elements 47, and a drive signal COM is supplied from each bump to 10 to 20 switches 46, respectively. As a result, for example, the locations where the drive signal COM is input to the switches 48 corresponding to the nozzles at both ends (nozzle # 1, nozzle # 180) can be made different (see FIG. 6). Wiring can be shortened.

  On the other hand, the head controller HC outputs an applied signal to the 180 piezo elements 47, so that the semiconductor chip becomes a long semiconductor chip in the direction in which the piezo elements 47 are arranged. In order to shorten the wiring between the input portion of the drive signal COM and the switch 46, the plurality of bumps are provided along the longitudinal direction of the semiconductor chip.

=== Bump Arrangement ===
FIG. 8 is an explanatory diagram of a wiring pattern of a flexible printed circuit board (FPC) on which the head controller HC is mounted. In the figure, the FPC wiring pattern is drawn in black.

  In the figure, a rectangle with a thick dotted line in the center indicates a mounting position of a semiconductor chip constituting the head controller HC.

  On the left side of the drawing, there is provided a wiring pattern for inputting a signal composed of a clock signal CLK, a latch signal LAT, a change signal CH, pixel data SI and setting data SP to the head controller HC. . In addition to these signals, a wiring pattern GND for grounding and wiring patterns of VDD (3 V) and VHV (42 V) as power sources for the head controller HC are also provided.

  On the right side of the figure, there is provided a wiring pattern for outputting signals to be applied to 180 piezo elements 47 from the head controller HC (a part of this wiring pattern is omitted). . In order to output an applied signal to a large number of piezoelectric elements 47, the head controller HC is a semiconductor chip that is long in the vertical direction in the figure.

  A wiring pattern for inputting the drive signal COM to the head controller HC is provided across the mounting position of the head controller HC. This wiring pattern is a pattern along the longitudinal direction (vertical direction in the drawing) of the head controller HC at the mounting position of the head controller HC. A plurality of bumps of the head controller HC are connected on this wiring pattern.

  FIG. 9 is an explanatory diagram of a wiring pattern at the mounting position of the head controller HC and bumps of the head controller HC. The dotted line in the figure indicates the mounting position of the head controller HC (semiconductor chip IC). The black part in the figure shows the wiring pattern. The white line in the wiring pattern indicates the shape / position of the bump. In other words, the white line in the wiring pattern indicates the shape and position of the connection portion between the bump and the wiring pattern. For example, the width of the wiring pattern is 250 μm, and the width of the bump is about 80 μm.

  As shown in the drawing, a plurality of bumps are arranged along the wiring direction of the wiring pattern. For example, the drive signal COM to be applied to the piezo element 47 of the nozzle # 1 is supplied from the uppermost bump in the drawing to the head control unit HC and applied to the piezo element 47 of the nozzle # 180. COM is supplied to the head controller HC from the bottom bump in the drawing. Thereby, the wiring in the head controller HC (semiconductor chip IC) between each bump and each switch 46 can be shortened.

  Since the plurality of bumps of the head control unit HC are arranged on a common wiring pattern (wiring pattern of the drive signal COM), the same situation as in FIGS. 1A to 1C occurs. That is, a large difference occurs in the deformation amount in the wiring direction at the time of heating due to the difference in linear expansion coefficient between the FPC and the semiconductor chip IC constituting the head controller HC. At the time of thermocompression bonding between the FPC and the semiconductor chip IC, the FPC is fixed to the semiconductor chip IC via the bumps in a state where the FPC is greatly expanded in the wiring direction. On the other hand, at the time of heat dissipation, the FPC contracts more than the semiconductor chip IC in a state where both are fixed via the bumps, so that a large stress is applied to the bumps along the wiring direction of the wiring pattern.

  On the other hand, according to the bump of this embodiment, the bump has an elliptical column shape. For this reason, as shown in FIG. 9, the connection part of a bump and a wiring pattern becomes elliptical. In other words, in this embodiment, the cross-sectional shape of the bump in the plane parallel to the wiring pattern is an ellipse. As a result, even if stress in the wiring direction is applied to the bumps, the outer shape is an arc shape, so that stress concentration hardly occurs, and generation of cracks can be suppressed.

  Furthermore, according to this embodiment, the bump has an elliptical column shape in which the wiring direction has a short diameter. For this reason, as shown in FIG. 9, the connection part of a bump and a wiring pattern becomes elliptical shape in which a wiring direction becomes a short diameter. In other words, in this embodiment, the cross-sectional shape of the bump is an ellipse having a minor axis in the wiring direction. As a result, when the stress in the wiring direction is applied to the bump, the width of the bump in the wiring direction is short, so that a force that deforms the semiconductor chip IC in the direction indicated by the dotted line in FIG. Can be suppressed. By making the cross section elliptical, it is possible to secure a cross sectional area necessary for connection with the FPC while narrowing the width of the bump in the wiring direction.

=== Modification ===
FIG. 10 is an explanatory diagram of wiring patterns and bumps according to the first modification.
In the above-described embodiment, a plurality of bumps are arranged on the wiring pattern of the drive signal COM. However, the present invention is not limited to this. For example, a wiring pattern that supplies a power supply voltage VHV (42 V) of 42 V to the head control unit HC may be provided across the mounting position of the head control unit HC, and a plurality of bumps may be disposed on the wiring pattern. The wiring pattern of the 42V power supply voltage VHV is for supplying the power supply voltage of a transistor (not shown) constituting the switch 46 (see FIG. 6) for controlling ON / OFF of the 42V drive signal COM. .
In the above embodiment, a large number of bumps are arranged on the same wiring pattern. However, as shown in FIG. 10, two bumps may be used. This is because a situation similar to that shown in FIGS. 1A to 1C can occur if at least two bumps are arranged on the same wiring pattern.

FIG. 11 is an explanatory diagram of wiring patterns and bumps of the second modification.
According to the above-described embodiment, the bump has an elliptical column shape, but the shape of the bump is not limited to this. For example, as shown in the figure, the bumps may be cylindrical. If it is such a shape, the connection part of a bump and a wiring pattern will become circular, and even if the stress of a wiring direction will apply to a bump, it will become difficult to produce stress concentration and generation | occurrence | production of a crack can be suppressed. However, as compared with the case of FIG. 9, if the cross-sectional area required for connection with the FPC is to be secured, the width of the bump in the wiring direction is increased. As a result, when stress in the wiring direction is applied to the bumps, a force that deforms the semiconductor chip IC in the direction indicated by the dotted line in FIG. 2A is likely to work, and the deformation of the semiconductor chip IC increases.

FIG. 12 is an explanatory diagram of wiring patterns and bumps according to the third modification.
In the above-described embodiment, the plurality of bumps are arranged on a straight line, but the present invention is not limited to this. A plurality of bumps may be arranged in a staggered pattern on the same wiring pattern. By arranging in this way, stress is applied to the bump not only in the wiring direction but also in the direction intersecting with the wiring direction, and the stress applied to the bump is dispersed. As a result, the occurrence of cracks can be further suppressed. Further, since the stress applied in the wiring direction is dispersed, the force for deforming the semiconductor chip IC in the direction indicated by the dotted line in FIG. 2A is weakened, and the deformation of the semiconductor chip IC can be suppressed.

FIG. 13 is an explanatory diagram of a wiring pattern and bumps of a fourth modification.
In the above-described embodiment, all the bumps have the same shape, but the present invention is not limited to this. Each bump may have a different shape.
In particular, as shown in the drawing, the bumps may be configured so that the cross-sectional area of the bumps located on the outer side among the plurality of bumps arranged on the same wiring pattern increases. When the FPC and the semiconductor chip IC are shrunk by heat dissipation, a larger force is applied to the outer bump. Therefore, if the cross-sectional area of the outer bump is increased, the stress applied to the bump can be suppressed, and the generation of cracks can be further suppressed.

=== Other Embodiments ===
The above-described embodiments are for facilitating the understanding of the present invention, and are not intended to limit the present invention. The present invention can be changed and improved without departing from the gist thereof, and it is needless to say that the present invention includes equivalents thereof.

<About the printer>
In the above embodiment, the semiconductor chip IC used in the printer 1 has been described. However, the present invention is not limited to this. For example, in various precision devices such as a mobile phone and a liquid crystal display device, if it is necessary to arrange a plurality of bumps on the same wiring pattern, the same thing as the above embodiment can be performed.

<About the wiring of the drive signal COM in the semiconductor chip>
According to the wiring of the drive signal COM in the semiconductor chip constituting the head controller HC shown in FIG. 6 described above, one bump is provided for 10 to 20 piezo elements 47, and 10 to 10 from each bump. The drive signal COM is supplied to each of ˜20 switches 46. However, the present invention is not limited to this.

  FIG. 14 is an explanatory diagram of another embodiment of the wiring of the drive signal COM in the semiconductor chip. Here, a plurality of driving signal COM lines are commonly connected in the semiconductor chip. Even in this case, the wiring from the input portion of the drive signal COM to the switch 46 can be substantially shortened.

<About wiring pattern>
According to the wiring pattern shown in FIG. 8 described above, in order to output an applied signal to a large number of piezo elements 47, wiring for piezo elements from only one long side of the semiconductor chip constituting the head controller HC. Had been placed. However, the configuration of the semiconductor chip and the configuration of the FPC wiring pattern are not limited to this.

  FIG. 15 is an explanatory diagram of another embodiment of a semiconductor chip and a wiring pattern. FIG. 16 is an explanatory diagram of still another embodiment of a semiconductor chip and a wiring pattern. As shown in these drawings, a wiring pattern of a semiconductor chip or FPC may be configured. Also, piezoelectric element wirings may be arranged on the two long sides of the semiconductor chip.

1 printer, 10 controller, 11 memory,
20 transport unit, 30 carriage unit, 31 carriage,
40 head units, 41 heads,
42A first shift register, 42B second shift register,
43A first latch circuit, 43B second latch circuit, 44 signal selection unit,
45 control logic, 452 shift register group, 454 selection signal generation unit,
46 switches, 47 piezo elements,
50 sensor groups, 110 computer FPC flexible printed circuit board,
IC semiconductor chip, HC head controller CLK clock signal, LAT latch signal, CH change signal,
SI pixel data, SP setting data, COM drive signal,
PS1 to PS5 drive pulse,
VDD power supply voltage (3V), VHV power supply voltage (42V)

Claims (8)

With multiple bumps that will be connected to common wiring on the board,
The plurality of bumps are arranged side by side along a predetermined direction,
The semiconductor device, wherein the plurality of bumps are formed so that at least a part of a cross section of each of the plurality of bumps has an arc shape. The semiconductor device according to claim 1,
The semiconductor device, wherein the plurality of bumps are formed so that the cross section is elliptical. The semiconductor device according to claim 2,
The semiconductor device is characterized in that the plurality of bumps are formed so that the cross section has an elliptical shape in which the predetermined direction has a minor axis. The semiconductor device according to claim 1,
The semiconductor device, wherein the plurality of bumps are formed so that the cross section is circular. A semiconductor device according to claim 1,
The semiconductor device, wherein the plurality of bumps are arranged in a staggered pattern along the predetermined direction. A semiconductor device according to claim 1,
The semiconductor device, wherein the plurality of bumps are formed so that a cross-sectional area of the bump located on the outer side increases. A substrate on which wiring for driving signals for driving a plurality of elements for discharging ink is formed;
A semiconductor device for controlling application of the drive signal to each of the elements;
A printer equipped with
The semiconductor device includes a plurality of bumps commonly connected to the wiring,
The plurality of bumps are arranged side by side along the direction of the wiring,
The printer, wherein the plurality of bumps are formed so that at least a part of a cross section of each of the plurality of bumps has an arc shape. A plurality of bumps arranged side by side in a predetermined direction, and a semiconductor device including the plurality of bumps formed so that at least a part of each cross section has an arc shape, and the semiconductor device are mounted Preparing a substrate for
Connecting the plurality of bumps to the common wiring of the substrate by heating;
Manufacturing method of mounting substrate having

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