CN112992699B

CN112992699B - Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly

Info

Publication number: CN112992699B
Application number: CN202110137354.0A
Authority: CN
Inventors: 李维平
Original assignee: Shanghai Yibu Semiconductor Co ltd
Current assignee: Shanghai Yibu Semiconductor Co ltd
Priority date: 2021-02-01
Filing date: 2021-02-01
Publication date: 2024-03-22
Anticipated expiration: 2041-02-01
Also published as: KR20220112173A; TWI803162B; TW202232611A; CN112992699A

Abstract

The application discloses a semiconductor packaging method, a semiconductor component and electronic equipment comprising the semiconductor component, wherein the semiconductor packaging method comprises the following steps: the self-alignment capability of a first-stage alignment welding spot between the first-stage device and the carrier plate is utilized to automatically and accurately align and fix the first-stage device to a target position on the carrier plate; the plastic packaging process is realized by injection molding through the through opening of the carrier plate or the clamping plate while supporting one side of the first-stage device by the carrier plate and supporting the other side of the first-stage device by the clamping plate; and utilizing the self-alignment capability of the second level alignment pads between the first level assembly and the second level device to automatically and precisely align and fix the second level device to a target location on the first level assembly, thereby significantly improving the speed of pick and place operations of the first level device and the second level device, further improving process efficiency and reducing process costs.

Description

Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly

Technical Field

Embodiments of the present disclosure relate to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor packaging method, a semiconductor component, and an electronic device including the semiconductor component.

Background

Semiconductor packages and systems have been pursued to be compact, small, light, thin in design, while achieving high integration and versatility in functional aspects. Various packaging techniques are currently proposed to meet the above requirements, such as Fan-out (Fan-out) wafer level packaging, chiplet packaging (chiplet), heterogeneous integration (heterogeneous integration), 2.5-dimensional/three-dimensional (2.5D/3D) packaging. These packaging techniques possess respective different advantages and characteristics, but all present some technical challenges. Taking the existing fan-out package as an example, it faces a number of technical problems such as warpage (warp), chip drift (die shift), surface flatness (toporgram), non-coplanarity (chip-to-mold non-flatness) between the chip and the plastic package, package Reliability (Reliability), etc. Despite the ongoing efforts in the industry to improve these technical problems by improving the equipment, materials, process links, there is still no economical and efficient solution to some technical problems, especially for warpage, chip drift and surface coplanarity problems between different chips.

In addition, there are some commonalities in the various high-end semiconductor package and system manufacturing processes that often involve high precision placement and attachment of semiconductor devices. This process step is usually performed by high precision die bonding (pick and place or die bonder) equipment, but its mounting speed is limited, making the production speed very slow and the equipment cost expensive, which is a major bottleneck in the development and popularization of technology.

The present application aims to solve several core technical problems described above.

Disclosure of Invention

The present application is directed to a new and novel semiconductor packaging method, a semiconductor device and an electronic apparatus including the same, which at least solve the above and other technical problems in the prior art.

An aspect of the present application provides a semiconductor packaging method, including:

s310: providing at least one first level device, at least one second level device, a carrier plate and a clamping plate, wherein the first level device is formed with a plurality of first level interconnection pads on a first level first surface and a plurality of first level first alignment welds on a first level second surface opposite the first level first surface; the at least one second level device has a plurality of second level interconnect terminals and a plurality of second level first alignment welds formed on a second level first surface; a plurality of first-stage second alignment welding parts corresponding to the plurality of first-stage first alignment welding parts respectively are formed on the carrier plate; and at least one of the carrier plate and the clamping plate is penetrated with an opening for injection molding;

s320: placing the at least one first stage device on the carrier plate such that the plurality of first stage first alignment welds are substantially aligned with the plurality of first stage second alignment welds;

S330: forming a plurality of first-stage alignment pads by welding the plurality of first-stage first alignment welds and the plurality of first-stage second alignment welds such that the at least one first-stage device is precisely aligned and fixed to the carrier plate;

s340: injection molding is carried out through the opening so as to form a plastic package body which covers the at least one first-stage device between the carrier plate and the clamping plate which is attached to the first-stage first surface in advance;

s350: removing the clamping plate to expose the first stage first surface;

s360: sequentially forming an interconnection layer and a plurality of transfer terminals respectively corresponding to the plurality of second-stage interconnection terminals on one side of the plastic package body exposing the first-stage first surface, so that at least one part of the plurality of first-stage interconnection pads is respectively electrically connected to the plurality of transfer terminals through the interconnection layer, and a plurality of second-stage second alignment welding parts respectively corresponding to the plurality of second-stage first alignment welding parts are also formed on the interconnection layer, thereby forming a first-stage assembly;

s370: placing the at least one second stage device on the first stage assembly such that the plurality of second stage first alignment welds are substantially aligned with the plurality of second stage second alignment welds;

S380: forming a plurality of second-stage alignment pads by soldering the plurality of second-stage first alignment pads and the plurality of second-stage second alignment pads such that the at least one second-stage device is precisely aligned to the first-stage assembly, and bonding the plurality of second-stage interconnect terminals and the plurality of transit terminals, respectively, while pressing the at least one second-stage device and the first-stage assembly toward each other in a state in which the plurality of second-stage alignment pads are at least partially melted to form a plurality of interconnect joints; and

s390: releasing the pressing.

Another aspect of the present application provides a semiconductor packaging method, including:

s410: providing at least one first level device, at least one second level device, a carrier plate and a clamping plate, wherein the first level device is formed with a plurality of first level interconnection pads on a first level first surface and a plurality of first level first alignment welds on a first level second surface opposite the first level first surface; the at least one second-level device is provided with a plurality of second-level interconnection bumps and a plurality of second-level first alignment welding parts on a second-level first surface, wherein the second-level interconnection bumps respectively correspond to at least one part of the first-level interconnection pads; a plurality of first-stage second alignment welding parts corresponding to the plurality of first-stage first alignment welding parts respectively are formed on the carrier plate; and at least one of the carrier plate and the clamping plate is penetrated with an opening for injection molding;

S420: placing the at least one first stage device on the carrier plate such that the plurality of first stage first alignment welds are substantially aligned with the plurality of first stage second alignment welds;

s430: forming a plurality of first-stage alignment pads by welding the plurality of first-stage first alignment welds and the plurality of first-stage second alignment welds such that the at least one first-stage device is precisely aligned and fixed to the carrier plate;

s440: injection molding is carried out through the opening so as to form a plastic package body which covers the at least one first-stage device between the carrier plate and the clamping plate which is attached to the first-stage first surface in advance;

s450: removing the clamping plate to expose the first stage first surface, thereby forming a first stage assembly;

s460: placing the at least one second stage device on the first stage assembly such that the plurality of second stage first alignment welds are substantially aligned with a plurality of second stage second alignment welds on the first stage assembly, wherein the plurality of second stage second alignment welds are preformed on a side of the first stage assembly that exposes the first stage first surface and correspond to the plurality of second stage first alignment welds, respectively;

S470: forming a plurality of second level alignment pads by soldering the plurality of second level first alignment pads and the plurality of second level second alignment pads such that the at least one second level device is precisely aligned to the first level component and, in a state in which the plurality of second level alignment pads are at least partially melted, bonding the plurality of second level interconnect bumps and corresponding first level interconnect pads, respectively, while pressing the at least one second level device and the first level component toward each other to form a plurality of interconnect joints; and

s480: releasing the pressing.

Yet another aspect of the present application provides a semiconductor assembly packaged by the above semiconductor packaging method.

Yet another aspect of the present application provides an electronic device comprising the above semiconductor assembly.

It is to be understood that the foregoing description is only a summary of the application so that the technical solutions of the application may be more clearly understood, and thus may be implemented in accordance with the content of the specification. The following detailed description of the present application will provide further clarity in the understanding of the above and other objects, features and advantages of the present application.

Drawings

Fig. 1 shows a schematic diagram of chip drift and chip rotation phenomena caused by placement misalignment or mold flow (mold flow) pushing during a chip-first fan-out package according to the prior art.

Fig. 2 shows a schematic diagram of a state where Under Bump Metallization (UBM) and re-routing layer (RDL) trace position mismatch (or misalignment) occurs after the chip shown in fig. 1 has drifted and rotated.

Fig. 3 shows a flow chart of a packaging method according to an embodiment of the present application.

Fig. 4A to 4L show cross-sectional views for schematically illustrating a packaging method according to an exemplary embodiment of the present application.

Fig. 5 shows a flow chart of a packaging method according to another embodiment of the present application.

Fig. 6A to 6E show cross-sectional views for schematically illustrating a packaging method according to an exemplary embodiment of the present application.

Detailed Description

The present application includes at least one embodiment in the following description with reference to the figures, in which like numerals represent the same or similar elements throughout the several figures. Although the following description is based primarily on specific embodiments, it will be appreciated by those skilled in the art that the following description is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following description and drawings. In the following description, certain specific details are set forth, such as specific configurations, compositions, and processes, etc., in order to provide a thorough understanding of the present application. In other instances, well-known processes and manufacturing techniques have not been described in detail in order to avoid unnecessarily obscuring the present application. Furthermore, the various embodiments shown in the figures are schematically illustrated and not necessarily to scale.

Semiconductor assemblies (also referred to as semiconductor packages) are core components of modern electronic devices or products. Semiconductor components can be broadly divided in terms of device count and density: discrete semiconductor devices, i.e., single chip devices, such as single digital logic processors, diodes, and transistors; a multi-chip assembly, such as a stack of a module of an image sensor (CIS) and an image processor (ASIC), a Central Processing Unit (CPU) and a dynamic memory (DRAM); and system level components such as radio frequency Front End Modules (FEM) in cell phones, display screen modules in cell phones and smart watches. In general, system-level components include a wide variety of devices, including passive components (resistors, capacitors, inductors) and other devices and even components, in addition to semiconductor devices.

Semiconductor assemblies herein may include active and passive devices including, but not limited to, active devices such as bipolar transistors, field effect transistors, integrated circuits, and passive devices such as chip resistors, capacitors, inductors, integrated passive components (IPD), microelectromechanical systems (MEMS), and the like. Various electrical connections are established between the various active and passive devices to form circuits that enable the semiconductor assembly to perform high-speed calculations and other useful functions.

Currently, semiconductor fabrication typically involves two complex fabrication processes, namely front-end wafer fabrication and back-end package fabrication, each of which may involve hundreds of steps. Previous wafer fabrication involves forming a plurality of dies (die) on the surface of a wafer. Each chip is typically identical and internally contains circuitry formed by electrically connecting active and/or passive cells. Subsequent package fabrication involves separating individual chips from the completed wafer and packaging into semiconductor components to provide electrical connection, structural support, and environmental isolation while providing convenience for subsequent assembly of the electronic product.

An important goal of semiconductor manufacturing is to produce smaller semiconductor devices, packages, and assemblies. Smaller products, generally with higher integration, less power consumption, higher performance and smaller area/volume, are important to the market performance of the final product. On the one hand, smaller integrated circuits can be fabricated by improving the previous wafer process, thereby shrinking chips, increasing density, and improving performance. On the other hand, subsequent packaging processes may further reduce the size, increase the density, and improve the performance of the semiconductor assembly by improving the package design, process, and packaging materials.

In the subsequent packaging process, a novel and efficient packaging mode is fan-out type packaging. Fan-out packages typically employ a packaging technique in which a molding compound encapsulates a single or multiple passing chips (die) from a singulated wafer and leads interconnect traces from the connection pads of the chips to external solder balls via a redistribution layer (RDL) to achieve higher I/O density and flexible integration. The fan-out type package may be largely classified into a chip-first (chip-first) type package and a chip-last (chip-last) type package. The chip-first type package can be further classified into an active surface-down (face-down) type and an active surface-up (face-up) type.

The chip-first/face-down type packaging mainstream process can comprise the following main steps: pick up the chip from the cut wafer and place on the carrier plate with adhesive film to make its active surface face the adhesive film; molding the side on which the chip is mounted with a molding compound; removing the carrier plate (together with the adhesive film) to expose the active surface of the chip; forming an interconnect layer (including an RDL layer and Under Bump Metallization (UBM)) on an active surface of the chip; forming solder balls on the interconnection layer, wherein the interconnection pads or the interconnection bumps of the chip are electrically connected with the solder balls through the interconnection layer; and dicing to form individual semiconductor elements.

The chip-first/face-up type packaging process may be substantially the same as the chip-first/face-down type packaging process, with the main differences being that: when the chip is picked up and placed on the carrier plate attached with the adhesive film, the active surface of the chip is back to the adhesive film; thinning the molding compound on one side of the active surface of the chip after plastic packaging to expose the interconnection bumps on the active surface of the chip; and the carrier plate may be removed after the interconnect layer and solder balls are formed.

In the current technical problems of fan-out type packaging, high-precision placement and position fixing of chips still lack an efficient and economical method. Often, the higher the placement precision of the chip is, the higher the equipment cost is, the lower the production efficiency is, and the precision of the chip mounting equipment is difficult to break through the limit of 0.5 micrometer. In addition, after the chip is placed on the adhesive film, the adhesive film is adhered to a fixed position, but the adhesive film has deformability, and the chip can be pushed by the flow of plastic packaging materials in the plastic packaging process, so that the chip is displaced and rotated on the adhesive film. The higher temperatures used in the molding process exacerbate this problem. Another source of chip displacement and rotation is internal stress within the plastic package. In the existing chip-first/face-up packaging technology, the plastic packaging process comprises three stages of heating injection molding, partial solidification of plastic packaging materials in high-temperature maintenance and cooling. There is typically a subsequent step of complete curing of the thermostatically heated plastic encapsulant. The thermal expansion coefficients of the chip, the plastic packaging material, the adhesive film, the carrier plate and the like are different, so that the mismatch of the thermal expansion coefficients of various materials and the curing shrinkage of the plastic packaging material in the plastic packaging process lead to uneven internal stress of the plastic packaging body, and further cause chip drift and/or rotation (as shown by chip arrangement at the lower right part of fig. 1) and warpage of the plastic packaging body (the shape of the chip and the carrier plate which are formed by coating the plastic packaging material). The chip drift and/or rotation in turn causes subsequently formed re-wiring (RDL) traces and Under Bump Metallization (UBM) position mismatches or misalignments (as shown in the upper right-hand side of fig. 2 where the chip drift and rotation occurs), which may lead to a substantial reduction in yield. Warpage of the plastic package body may cause difficulty in subsequent packaging processes (including formation of RDL and UBM), and even may not be able to continue with subsequent processes if serious.

In addition, in a subsequent packaging process, it may be necessary to further implement interconnection integration of a substrate (e.g., in a system-in-package), an interposer (e.g., in a 2.5D package), or another layer of chips (e.g., in a 3D package) in the Z-axis direction on the basis of two-dimensional integration of an X-Y plane (e.g., a plane parallel to the active or passive surfaces of the chips) according to specific packaging specifications. At this time, at least the face of high precision placement and positional fixation of the upper device on the lower device is lacking in an efficient and economical method similar to the fan-out package described above. In addition, as for the interconnection between the upper and lower devices in the 3D package (e.g., integrated fanout (InFO), coWoS (chip on substrate), soIC (system on chip)), hybrid bonding (hybrid bonding) is a key technology currently mainstream. However, there are various technical difficulties in hybrid bonding, besides the common problems of high cost and low production efficiency, there are also a few other problems, such as difficulty in meeting strict requirements on pad recessing in Chemical Mechanical Polishing (CMP), influence of pad density differences in different areas on a chip on the depth of recessing, easiness in oxidation of a pad (metal copper) at high temperature, and easiness in pollution of a chip in hybrid bonding of a chip and a wafer (die-to-wafer).

The present application aims to propose a completely new and breakthrough packaging method which at least solves the above technical problems.

The packaging method according to the embodiment of the application utilizes the self-alignment capability of the first-stage alignment welding spot (joint) between the first-stage device and the carrier plate when soldering tin is at least partially molten to enable the first-stage device to automatically and accurately align the target position on the carrier plate and achieve the position fixing of the first-stage device after the soldering tin is solidified, wherein a first-stage first-alignment welding part and a corresponding first-stage second-alignment welding part (for example, one of the first-stage alignment welding parts is a first-stage alignment welding lug, the other is a first-stage alignment welding lug) are respectively formed on the first-stage second surface (namely, the opposite surface of the first-stage first surface) of the first-stage device and one side of the carrier plate in advance, or the first-stage second-alignment welding parts are respectively formed on the first-stage second surface (namely, the opposite surface of the first-stage first surface) of the first-stage device and the corresponding first-stage second-alignment welding part. The packaging method includes, after a first stage device is placed at a target position on a carrier plate so that a first stage first alignment solder joint and a first stage second alignment solder joint are in contact with each other, melting one (or both) of the first stage first alignment solder joint and the first stage second alignment solder joint to form a first stage alignment solder joint, when the first stage device is not precisely aligned to the target position on the carrier plate (i.e., the first stage first alignment solder joint and the first stage second alignment solder joint are not centered), the first stage device in an at least partially melted state (liquid or partially liquid state) is automatically introduced to the target position based on a minimum surface energy principle to minimize the surface energy, and the first stage alignment solder joint keeps the first stage device firmly fixed at the target position after solidification. The first stage first alignment weld and the first stage second alignment weld (in terms of including but not limited to volume, geometry, composition, location, distribution, and number, etc.) are optimally designed to achieve the most accurate, efficient, effective, and reliable self-alignment capability. Because the bonding mode is adopted to replace the adhesive film bonding mode to fix the first-stage device on the carrier plate, the warping problem is improved, the possible drifting and rotation problems of the first-stage device in the plastic packaging process are prevented through a firm welding mode, a certain degree of placement deviation can be allowed when the first-stage device is picked and placed in view of the self-alignment capability of the first-stage alignment welding spots, the requirement on the placement precision of the first-stage device (particularly on a pick and place or die bonding) can be remarkably reduced, the speed of the picking and placement operation of the first-stage device can be remarkably improved, the process efficiency is further improved, and the process cost is reduced.

Secondly, according to the packaging method of the embodiment of the application, the carrier plate is used for supporting one side of the first-stage second surface of the first-stage device, and the clamping plate is used for supporting the first-stage first surface of the first-stage device, and meanwhile, the plastic packaging process is realized through injection molding of the through opening of the carrier plate or the clamping plate, so that compared with the existing chip-first/face-up packaging process, the plastic packaging body does not need to be drilled after the plastic packaging process is performed to expose the interconnection bonding pads, or the surface of the plastic packaging body only needs to be slightly cleaned (for example, plasma cleaning) after the plastic packaging process is performed to clean the surface of the interconnection bonding pads, so that not only can the efficiency of the plastic packaging process be improved, but also accidental damage of the first-stage first surface of the first-stage device caused by the processes such as thinning (for example, grinding) or drilling can be avoided, and the yield can be improved.

In addition, according to the packaging method of the embodiment of the application, when the first-stage component including the first-stage device is subjected to the Z-axis direction interconnection integration of the second-stage device (for example, a substrate or an interposer) or the semiconductor device), the second-stage device is automatically and precisely aligned to a target position on the first-stage component by utilizing the self-alignment capability of a second-stage alignment welding spot between the first-stage device and the second-stage device when soldering tin is at least partially melted, and the position of the second-stage device is fixed after the soldering tin solidifies, wherein a second-stage first alignment welding part and a corresponding second-stage second alignment welding part (for example, one of the second-stage first alignment welding part and the corresponding second-stage second alignment welding part is a second-stage alignment welding bump, or both of the second-stage first alignment welding parts and the corresponding second-stage second alignment welding bump are respectively formed on the second-stage first surface of the second-stage device and the corresponding surface of the first-stage component. Similarly, a degree of placement bias can be tolerated when picking and stacking the second level devices on the first level assembly in view of the self-alignment capability of the second level alignment pads, thereby significantly reducing the requirements on the placement accuracy of the second level devices, particularly on the pick and place or die bonder, and significantly increasing the speed of the second level device pick and place operations, thereby further increasing process efficiency and reducing process costs. In addition, by replacing the hybrid bonding mode, the technical difficulties existing in the hybrid bonding can be avoided, so that the simple and efficient 3D packaging is realized.

The term "semiconductor device" as used herein may refer to a chip (also interchangeably referred to as a die, a grain, a die, an integrated circuit) produced at a foundry (fab), i.e., a chip that has not yet been packaged after dicing and testing, and may typically have only interconnect pads (pads) for external connection on the chip. The semiconductor device may also be a pre-processed (at least partially packaged) chip, for example with interconnect bumps (bumps) formed on the interconnect pads, or may have additional structures, for example stacked chips or packaged chips or semiconductor components, as desired.

The term "active surface" as used herein generally refers to a side surface of a semiconductor device having circuit functions with interconnect pads (or interconnect bumps formed thereon), which may also be interchangeably referred to as a front side or functional side. The active surface of the semiconductor device and the other side surface (which may be interchangeably referred to as the passive surface or the back surface) that does not have a circuit function are opposite to each other.

The term "interconnect terminal" as used herein generally refers to an interconnect pad or interconnect bump on the active surface of a semiconductor device.

The term "alignment weld" as used herein generally refers to a structure that can be welded to a corresponding other alignment weld for alignment by welding methods known in the art.

Fig. 3 shows a flow diagram of a packaging method according to an embodiment of the present application. As shown in fig. 3, the packaging method includes the following steps:

s310: at least one first-stage device, at least one second-stage device, a carrier plate and a clamping plate are provided, wherein the first-stage device is provided with a plurality of first-stage interconnection pads on a first-stage first surface and a plurality of first-stage first alignment welding parts on a first-stage second surface opposite to the first-stage first surface, the at least one second-stage device is provided with a plurality of second-stage interconnection terminals and a plurality of second-stage first alignment welding parts on a second-stage first surface, and a plurality of first-stage second alignment welding parts corresponding to the plurality of first-stage first alignment welding parts respectively are formed on the carrier plate, and an opening for injection molding is formed on at least one of the carrier plate and the clamping plate in a penetrating manner.

In some embodiments, the first stage device is a plurality of. As an example, the plurality of first stage devices may be at least partially different from each other in function, size, or shape, or may be identical to each other. In some embodiments, the second level device is a plurality of. As an example, the plurality of second stage devices may be at least partially different from each other in function, size, or shape, or may be identical to each other. It should be appreciated that the type and specific number of the first stage devices and the second stage devices may be appropriately selected according to specific process conditions or actual requirements (e.g., the size or shape of the carrier board, the first stage devices and the second stage devices, the placement pitch of the first stage devices and the second stage devices, package size or shape, manufacturing process specifications, or functional design of the final semiconductor assembly, etc.), and the present application is not particularly limited thereto.

In some embodiments, the carrier is a glass carrier, a ceramic carrier, a metal carrier, an organic polymer material carrier, or a silicon wafer, or is made of a combination of two or more of the foregoing materials. Optionally, the carrier plate has an interconnect structure or product functionality. As an example, an interconnection board, which is a substrate (such as a package substrate) or an interposer (interposer), is employed as the carrier board. For example, the interposer provides interconnection in a horizontal and/or vertical direction. As an example, the first-stage second alignment solder portion serves as an interconnection terminal of the interconnection board.

In some embodiments, the first level device is a first level semiconductor device. When the first level device is a first level semiconductor device, the plurality of first level interconnect pads are formed on an active surface of the first level semiconductor device and the plurality of first level first alignment bonds are formed on a passive surface. In other embodiments, the first level device is an interconnect board. The interconnect board is, for example, a substrate (such as a package substrate) or an interposer (interposer). For example, the interposer provides interconnection in a horizontal and/or vertical direction.

In some embodiments, either of the first level first alignment bond pad and the first level second alignment bond pad is a first level alignment bond bump, and the other is a first level alignment bond pad corresponding to the first level alignment bond bump. In other embodiments, the first stage first alignment solder joint and the first stage second alignment solder joint are both first stage alignment solder bumps and may have the same melting point or different melting points. As an example, the first level alignment solder bumps may be pre-fabricated on the first level device and/or carrier using bump fabrication processes known in the art (e.g., electroplating, ball placement, stencil printing, evaporation/sputtering, etc.). As an example, the first level alignment pads may be pre-fabricated on the first level device or carrier using a deposition (e.g., metal layer) -photolithographic-etching process. It should be appreciated that the first stage first alignment weld and the first stage second alignment weld may take any other configuration or form as long as they are capable of being welded to one another for alignment purposes.

In some embodiments, the first stage first alignment welds correspond to the first stage second alignment welds in terms of volume, size, geometry, composition, distribution, location, and number, etc., such that the first stage devices can be precisely aligned to respective target locations on the carrier plate by welding to each other.

It should be appreciated that the specific volume, size, geometry, composition, distribution, location, and number of the first stage first alignment welds and/or the first stage second alignment welds may be appropriately selected according to specific process conditions or actual requirements (e.g., the size or shape of the carrier plate and the first stage device, the placement pitch of the first stage device, package size or shape, etc.), and the application is not particularly limited thereto. For example, for a plurality of first level devices, the first level first alignment welds may be formed to be substantially the same volume, size, geometry, or composition, regardless of whether the function, size, or shape are the same as each other, and the first level second alignment welds on the carrier plate may be formed to be substantially the same volume, size, geometry, or composition, in order to reduce subsequent process complexity and improve packaging efficiency. For another example, for a plurality of first stage devices that differ in function, size, or shape, the first stage first alignment weld and the first stage second alignment weld may be formed in different volumes, sizes, geometries, or compositions so that different solder joint heights may be formed after subsequent welds to achieve a particular function or meet a particular requirement. In some embodiments, for a plurality of first level devices, the first level first alignment bond and/or the first level second alignment bond are configured such that first level first surfaces of the plurality of first level devices can lie in a same plane parallel to the carrier plate after subsequent bonds form first level alignment bond pads. For another example, each of the first stage devices may have at least three first stage first alignment welds formed thereon that are substantially regularly distributed so as to enable the first stage second surface of the first stage device to be firmly and stably maintained in a plane substantially parallel to the carrier plate by welding of the first stage first alignment welds and the first stage second alignment welds. For another example, the first level first alignment bond sites may be formed in areas on the first level second surface near the edges on each of the first level devices so as not to interfere with subsequent processing and product applications.

Optionally, the first level device is further provided with at least one through electrode for vertical interconnection. For example, for the first level semiconductor device, the through electrode is a Through Silicon Via (TSV). For another example, for the interposer, the through electrode is a TSV or a glass via (TGV). For another example, the through electrode is a Plated Through Hole (PTH) or a via (via) with respect to the substrate. It will be appreciated that at this time, the first stage device may also be formed with further interconnect terminals (e.g., the first stage first alignment solder may also be at least a portion thereof) on a first stage second surface opposite the first stage first surface, and that one end of the at least one through electrode is electrically connected to at least a portion of the plurality of first stage interconnect pads, respectively, and the other end of the at least one through electrode is electrically connected to the further interconnect terminals, respectively.

In some embodiments, the second level device is a second level semiconductor device. When the second level device is a second level semiconductor device, the plurality of second level interconnection terminals and the plurality of second level first alignment welds are formed on an active surface of the second level semiconductor device. In other embodiments, the second level device is an interconnect board. The interconnect board is, for example, a substrate (such as a package substrate) or an interposer (interposer). For example, the interposer provides interconnection in a horizontal and/or vertical direction.

As an exemplary embodiment, at least one of the at least one first level device and the at least one second level device comprises at least one semiconductor device.

In some embodiments, the second level first alignment bond is a second level alignment bond bump or a second level alignment pad. As an example, the second level alignment solder bumps may be pre-fabricated on the second level device using bump fabrication processes known in the art (e.g., electroplating, ball placement, stencil printing, evaporation/sputtering, etc.). As an example, the second level alignment pads may be pre-fabricated on the second level device using a deposition (e.g., metal layer) -photolithographic-etching process.

It should be appreciated that the specific volume, size, geometry, composition, distribution, location, and number of the second level first alignment welds may be appropriately selected according to specific process conditions or actual requirements (e.g., the size or shape of the first level devices and the second level devices, the placement pitch of the first level devices and the second level devices, package size or shape, etc.), and the application is not particularly limited thereto. For example, for a plurality of second level devices, the second level first alignment welds may be formed to be substantially the same volume, size, geometry, or composition, regardless of whether the functions, sizes, or shapes are identical to each other, in order to reduce subsequent process complexity and improve packaging efficiency. For another example, for a plurality of second level devices that differ in function, size, or shape, the second level first alignment welds may be formed in different volumes, sizes, geometries, or compositions so that different solder joint heights may be formed after subsequent welds to achieve a particular function or meet a particular requirement. As another example, at least three second-stage first alignment welds substantially regularly distributed may be formed on each of the second-stage devices, so that the second-stage first surfaces of the second-stage devices can be firmly and stably maintained in a plane substantially parallel to the carrier plate by second-stage alignment welds formed by welding, which will be described later. As another example, on each of the second level devices, the second level first alignment solder connections may be routed on edges sufficiently distant from the second level interconnect terminals so as not to interfere with subsequent processing and product applications.

In some embodiments, the second level interconnect terminals are second level interconnect bumps. As an example, the second level interconnect bump may be pre-fabricated on the interconnect pad of the second level device using bump fabrication processes known in the art (e.g., electroplating, ball-plating, stencil printing, evaporation/sputtering, etc.). For example, the second level interconnect bumps may be in the form of conductive pillars. In an alternative embodiment, the second level interconnect terminal is a second level interconnect pad. Optionally, the second level device is further provided with at least one through electrode for vertical interconnection. For example, for the second level semiconductor device, the through electrode is a Through Silicon Via (TSV). For another example, for the interposer, the through electrode is a TSV or a glass via (TGV). For another example, the through electrode is a Plated Through Hole (PTH) or a via (via) with respect to the substrate. It is understood that at this time, the second-stage device may be further formed with further interconnection terminals on a second-stage second surface opposite to the second-stage first surface, and one end of the at least one through electrode is electrically connected to at least a part of the plurality of second-stage interconnection terminals, respectively, and the other end of the at least one through electrode is electrically connected to the further interconnection terminals, respectively.

In some embodiments, the opening is formed on the carrier plate such that the opening is spaced apart from the first stage second alignment weld. As an example, the opening is provided outside an area defined by a target location of the at least one first stage device on the carrier plate. For example, in the case where there are a plurality of first stage devices, the opening is provided in a region between target positions of the plurality of first stage devices. In some embodiments, the opening is formed in the cleat such that the opening is spaced apart from the first stage first surface of the at least one first stage device when the cleat is attached to the first stage first surface. In some embodiments, the openings are formed on both the carrier plate and the clamping plate. It should be understood that the size, geometry, number or distribution of the openings may be appropriately selected according to the process conditions or actual requirements (e.g., molding materials) associated with the subsequent molding, and the application is not particularly limited as long as the injection molding can be effectively performed to achieve the purpose of the molding.

As an exemplary embodiment, as shown in fig. 4A, two first stage semiconductor devices 410, 410', a second stage semiconductor device 460, a carrier 420, and a clamping plate 430 are provided. The two first level semiconductor devices 410, 410' are not identical, e.g., are different in size and/or function. It will be appreciated that although only the first stage semiconductor device 410 is shown with reference numerals for relevant portions thereof in fig. 4A for ease of illustration and will be described below in connection therewith, the description applies equally to corresponding similar portions of the first stage semiconductor device 410'. Each first level semiconductor device 410, 410' is formed with a plurality of first level interconnect pads 412 distributed on the active surface 411 and a plurality of first level alignment solder bumps 414 formed on the passive surface 413. The second level semiconductor device 460 is formed with a plurality of second level interconnect bumps 462 and a plurality of second level alignment solder bumps 464 distributed over the active surface 461. A plurality of first level alignment pads 424 are formed on a surface of the carrier 420 in the same arrangement (or relative positional relationship) as the first level alignment solder bumps 414 on each of the first level semiconductor devices 410, 410'. Openings 428 for injection molding are formed through the carrier 420 in regions between the target locations corresponding to the first stage semiconductor devices 410, 410'. Alternatively, passive devices may be provided in a similar structure in addition to the first-stage semiconductor device and the second-stage semiconductor device. For example, reference numeral 410' as shown in fig. 4A may be replaced with a passive device.

S320: the at least one first stage device is placed on the carrier plate such that the plurality of first stage first alignment welds are substantially aligned with the plurality of first stage second alignment welds.

In some embodiments, the "substantially aligned" includes the first stage first alignment weld and the first stage second alignment weld each contacting each other, but not being precisely centered in a direction perpendicular to the first stage second surface. "centered" herein generally means that the centers of the first stage first alignment weld and the first stage second alignment weld are aligned in a direction perpendicular to the first stage second surface. It should be noted that "substantial alignment" of the first stage first alignment weld with the first stage second alignment weld means that there is at least contact between the first stage first alignment weld and the first stage second alignment weld to such an extent that self-alignment is enabled by the principle of minimum surface energy of the first stage alignment weld in an at least partially molten state during welding as described below, and thus "substantial alignment" includes a state of not being precisely centered but at least physically contacted, but may not exclude a state of being precisely centered.

It should be appreciated that when the first stage device is placed on the carrier plate in step S320, the first stage second surface of the first stage device faces the carrier plate (i.e., the surface on which the first stage first alignment weld is formed), and the first stage first surface of the first stage device faces away from the carrier plate.

As an exemplary embodiment, as shown in fig. 4B, first level semiconductor devices 410, 410' are placed on carrier 420 such that first level alignment solder bumps 414 are in contact with corresponding first level alignment pads 424. At this time, the first level alignment solder bump 414 is misaligned with the first level alignment pad 424, i.e., the vertical centerline L1 of the first level alignment solder bump 414 and the vertical centerline L2 of the first level alignment pad 424 do not coincide.

S330: and forming a plurality of first-stage alignment pads by welding the plurality of first-stage first alignment welds and the plurality of first-stage second alignment welds such that the at least one first-stage device is precisely aligned and fixed to the carrier plate.

It should be noted that "precise alignment" means a state in which a deviation between an actual position of the first stage device on the carrier plate and a target position is within a tolerance range in the art. It should be appreciated that the precise alignment is achieved using the principle of minimum surface energy exhibited by a weld joint formed by welding a first stage first alignment weld and a first stage second alignment weld in an at least partially molten state during the welding process. Specifically, when the first-stage first-alignment solder joint and the first-stage second-alignment solder joint are in contact with each other but are not precisely aligned in a direction perpendicular to the first-stage second surface of the first-stage device or the carrier plate, one of the first-stage first-alignment solder joint and the first-stage second-alignment solder joint, which is the first-stage alignment bump, is at least partially melted and wets the other one of the first-stage alignment solder pad or the other first-stage alignment solder bump, or both the first-stage first-alignment solder joint and the first-stage second-alignment solder joint are at least partially melted, thereby forming a first-stage alignment solder joint in an at least partially melted state, which, on the basis of the principle of minimum surface energy, tends to deform and move to bring the first-stage first-alignment solder joint and the first-stage second-alignment solder joint in an at least partially melted state close to an aligned state, thereby driving the first-stage device lighter relative to the carrier plate to be precisely aligned to a target position on the carrier plate.

It will be appreciated that after the first stage first alignment bond and the first stage second alignment bond are bonded, the first stage second surface of the first stage device and the carrier plate are spaced apart to form a space therebetween due to the height of the first stage alignment bond itself (in a direction perpendicular to the first stage second surface of the first stage device or the carrier plate) formed thereby.

In some embodiments, the first level alignment solder bumps are made of solder and the soldering may be by a variety of molten solder soldering means known in the art including, but not limited to, reflow soldering, laser soldering, high frequency soldering, infrared soldering, and the like. As an example, soldering may be performed using a flux or a cream solder.

As an exemplary embodiment, first level alignment solder bumps 414 and first level alignment pads 424 are soldered to form first level alignment solder bumps 416, as shown in fig. 4C. During the soldering process, the first level alignment solder bump 414 in a molten state wets the first level alignment pad 424 and self-aligns with the first level alignment pad 424 based on its own minimum surface energy principle (i.e., the vertical centerline L1 of the first level alignment solder bump 414 coincides with the vertical centerline L2 of the first level alignment pad 424), so that the first level semiconductor devices 410, 410' are brought into precise alignment on the carrier 420. After the soldering is completed, the passive surfaces 413 of the first stage semiconductor devices 410, 410' are spaced apart from the carrier 420 to form a space.

In some embodiments, after S330, S331 is further included: and turning over the first-stage device and the carrier plate as a whole, so that the first surface of the first-stage device faces downwards, and cooling after at least partial melting of the first-stage alignment welding spots to solidify the first-stage alignment welding spots. It should be appreciated that the first stage alignment pads, which are at least partially melted again at this time, are moderately elongated due to the weight of the first stage devices, thereby further improving self-alignment accuracy. It should be noted that, due to the surface energy of the first stage alignment pad in at least a partially molten state, the first stage device will not fall off the carrier plate due to its own weight. As an alternative embodiment, in S310, an adhesive flux is pre-coated on the plurality of first stage first alignment welds and/or the first stage second alignment welds, and S330 includes S330': before the welding, the first-stage device and the carrier plate are turned over as a whole, so that the first-stage first surface of the first-stage device faces downwards. It should be appreciated that at this point, after flipping, the first stage alignment pads, which are at least partially melted during the soldering process, are moderately elongated due to the weight of the first stage devices, thereby further improving the self-alignment accuracy. It should be noted that, because the adhesive flux adheres the first-stage device to the carrier plate, the first-stage device will not fall off from the carrier plate due to its own weight after being turned over. It should be understood that, before S340 described below, the first stage device and the carrier plate may also be flipped again as a whole as needed.

In some embodiments, when the first stage device is a plurality, S330 includes S330": and flattening the first-stage first surfaces of the plurality of first-stage devices by using a flattening plate (flattening plate) when the first-stage devices are precisely aligned with the carrier plate and the first-stage alignment welding spots are still in an at least partially molten state, so that the first-stage first surfaces of the plurality of first-stage devices are basically positioned in the same plane parallel to the carrier plate. As an example, S330 "includes: placing the platen over a first level first surface of the plurality of first level devices; pressing the platen toward the carrier plate such that the first-stage first surfaces of the plurality of first-stage devices lie substantially in a same plane parallel to the carrier plate; cooling while maintaining the pressing to enable the first-stage alignment welding spots to be basically solidified; and removing the platen. As an alternative embodiment, when the first stage devices are plural, S332 is further included after S330: and after the first-stage alignment welding spots are at least partially melted again, flattening the first-stage first surfaces of the first-stage devices by using a flattening plate, so that the first-stage first surfaces of the first-stage devices are basically positioned in the same plane parallel to the carrier plate. As an example, the S332 includes: at least partially melting the first stage alignment pads again; placing the platen over a first level first surface of the plurality of first level devices; pressing the platen toward the carrier plate such that the first-stage first surfaces of the plurality of first-stage devices lie substantially in a same plane parallel to the carrier plate; cooling while maintaining the pressing to enable the first-stage alignment welding spots to be basically solidified; and removing the platen. It will be appreciated that the surface energy of the molten solder joint can be prevented from re-allowing the first stage device to resume its original height prior to flattening because the platen is not removed until the first stage alignment solder joint has substantially solidified by maintaining the press.

As an exemplary embodiment, as shown in fig. 4D, after the first stage alignment pads 416 are again brought into an at least partially molten state by heating, a platen P is placed on the active surface 411 of the first stage semiconductor devices 410, 410 'and pressed (i.e., toward the carrier 420) to perform a flattening process such that the active surfaces of the first stage semiconductor devices 410, 410' are in the same plane parallel to the carrier 420. Subsequently, the temperature is lowered while maintaining the pressing to solidify the first level alignment pad 416, and then the platen P is removed.

Thereby, the first-stage first surfaces of all first-stage devices can be made precisely flush and at the same height. It will be appreciated that it is necessary to apply a suitable pressure on the platen such that the first stage alignment pads in an at least partially molten state are suitably deformed and the resulting vertical (relative to the first stage first surface or carrier plate of the first stage device) displacement of the platen is suitable to prevent damage to the first stage device. As an example, a solder trap (solder trap) is formed in advance around the first stage second alignment solder of the carrier plate, whereby uncontrolled random flow of excess molten solder can be prevented during pressing.

In some embodiments, the flattening process using a flattening plate is combined with the post-flip welding process or the remelting process. As an example, S330 "is performed after S330 'is performed in S330, or S332 is performed after S330 including S330' is performed, or S331 is performed after S330 including S330" is performed, or S332 is performed when S331 is performed.

S340: injection molding is performed through the opening to form a plastic package covering the at least one first-stage device between the carrier plate and the clamping plate pre-attached to the first-stage first surface.

It should be appreciated that by the injection molding, not only the side surfaces of the first stage devices are covered, but also the space between the first stage second surface of the first stage devices and the carrier plate is filled with the covering. It will be appreciated that the first level first surface is substantially planar and therefore the clamping plate is substantially in close proximity to the first level first surface, and thus the first level first surface of the first level device, including the first level interconnect pads, is not encapsulated by the injection molding.

It should be appreciated that the injection molding is performed through the openings formed on the carrier plate and/or the clamping plate according to S310.

In some embodiments, S330 includes S330' ": attaching the clamping plate to the first stage first surface of the at least one first stage device. As an example, S330' "is performed before S330" is performed in S330. In other embodiments, S333 is further included between S330 and S340: attaching the clamping plate to the first stage first surface of the at least one first stage device. As an example, S333 is performed before S332. As another example, S333 is performed after S332. As yet another example, S333 is performed after S330 including S330 ". In still other embodiments, the platen is retained as the clamping plate after the flattening process in S330 "or S332. Therefore, by multiplexing the pressing plate into the clamping plate, materials required by the process can be reduced and the whole process flow can be simplified. As an example, S330 includes: and when the first stage devices are precisely aligned with the carrier plate and the first stage alignment welding spots are still in an at least partially molten state, flattening the first stage first surfaces of the first stage devices by using the clamping plates as flattening plates, so that the first stage first surfaces of the first stage devices are basically positioned in the same plane parallel with the carrier plate until the first stage alignment welding spots are basically solidified. As another example, between S330 and S340 further includes: and after the first-stage alignment welding spots are at least partially melted again, flattening the first-stage first surfaces of the first-stage devices by using the clamping plates as flattening plates, so that the first-stage first surfaces of the first-stage devices are basically positioned in the same plane parallel to the carrier plate until the first-stage alignment welding spots are basically solidified.

In some embodiments, the clamping plate is made of glass, ceramic, metal, organic polymer material, or silicon wafer, or a combination of two or more of the foregoing materials.

In some embodiments, the molding compound is used for molding of a resinous material (e.g., epoxy).

As an exemplary embodiment, after attaching the clamping plate 430 to the active surface 411 of the first stage semiconductor device 410, 410', as shown in fig. 4E, injection molding is performed through the opening 428 of the carrier 420, as shown in fig. 4F, thereby forming a plastic package 440 between the carrier 420 and the clamping plate 430, which encapsulates the first stage semiconductor device 410, 410'.

S350: the clamping plate is removed to expose the first stage first surface.

In some embodiments, the splint is removed by stripping, etching, ablating, grinding, and the like, as is known in the art.

As an exemplary embodiment, as shown in fig. 4G, the plastic package 440 exposes the active surface 411 of the first level semiconductor device 410, 410', i.e., exposes the first level interconnect pad 412, by removing the clamping plate 430.

S360: and sequentially forming an interconnection layer and a plurality of transfer terminals respectively corresponding to the plurality of second-stage interconnection terminals on one side of the plastic package body exposing the first surface of the first stage, so that at least one part of the plurality of first-stage interconnection pads is respectively electrically connected to the plurality of transfer terminals through the interconnection layer, and a plurality of second-stage second alignment welding parts respectively corresponding to the plurality of second-stage first alignment welding parts are also formed on the interconnection layer, thereby forming a first-stage assembly.

In some embodiments, the interconnect layer includes a rewiring layer (RDL) to thereby realize a conductive path of the first level interconnect pad and the transit terminal. It should be appreciated that the interconnect layer also includes an insulating layer for electrically insulating between the conductive paths, and the specific number and materials of the insulating layers may be appropriately selected according to specific process conditions or needs, which are not particularly limited in this application.

In some embodiments, any one of the second level first alignment bond and the second level second alignment bond is a second level alignment bond bump and the other is a second level alignment pad corresponding to the second level alignment bond bump. In other embodiments, the second level first alignment solder joint and the second level second alignment solder joint are both second level alignment solder bumps and may have the same melting point or different melting points. As an example, the second level second alignment solder bump may employ a bump manufacturing process (e.g., electroplating, ball-plating, stencil printing, evaporation/sputtering, etc.) known in the art as the second level second alignment solder bump. As an example, the second level alignment pad may employ a deposition (e.g., metal layer) -photolithographic-etching process as the second level second alignment pad. It should be appreciated that the second stage first alignment weld and the second stage second alignment weld may take any other configuration or form as long as they are capable of being welded to one another for alignment purposes.

In some embodiments, the second stage second alignment welds correspond to the second stage first alignment welds in terms of volume, size, geometry, composition, distribution, location, and number, etc., such that the second stage devices can be precisely aligned to respective target locations on the first stage assembly by welding to each other.

It should be appreciated that the specific volume, size, geometry, composition, distribution, location, and number of the second level second alignment welds may be appropriately selected according to specific process conditions or actual requirements (e.g., the size or shape of the first level devices and the second level devices, the placement pitch of the first level devices and the second level devices, package size or shape, etc.), and the application is not particularly limited thereto. For example, the second level second alignment welds on the first level assembly may all be formed of substantially the same volume, size, geometry, or composition in order to reduce subsequent process complexity and improve packaging efficiency. For another example, for a plurality of second level devices that differ in function, size, or shape, the second level second alignment welds may be formed in different volumes, sizes, geometries, or compositions so that different solder joint heights may be formed after subsequent welds to achieve a particular function or meet a particular requirement.

In some embodiments, the second level interconnect terminal is a second level interconnect bump and the landing terminal is a landing bump or landing pad. In other embodiments, the second level interconnect terminal is a second level interconnect pad and the landing terminal is a landing bump. As an example, bump fabrication processes known in the art (e.g., electroplating, ball-plating, stencil printing, evaporation/sputtering, etc.) may be used to fabricate the landing pads, which may be deposited (e.g., metal layer) -photolithographic-etching processes known in the art, as not particularly limited in this application.

In some embodiments, the transit terminals correspond to the second level interconnect terminals in terms of volume, size, geometry, composition, distribution, location, and number, etc., such that the transit terminals can be precisely centered with the second level interconnect terminals for stacked interconnection between the second level device and the first level assembly, as described below, when the second level device is precisely aligned to a respective target location on the first level assembly.

It should be appreciated that the sum of the heights of the second-stage interconnect terminal and the transit terminal is sufficiently smaller than the sum of the heights of the second-stage first alignment solder joint and the second-stage second alignment solder joint in a direction perpendicular to the second-stage first surface of the second-stage device (or the interconnect layer of the first-stage component) such that the second-stage interconnect terminal and the transit terminal are also spaced apart from each other after the second-stage first alignment solder joint and the second-stage second alignment solder joint are subsequently formed so as not to affect the subsequent soldering of the second-stage first alignment solder joint and the second-stage second alignment solder joint, and to prevent the second-stage interconnect terminal and the transit terminal from being damaged against each other upon the subsequent soldering of the second-stage first alignment solder joint and the second-stage second alignment solder joint.

As an exemplary embodiment, as shown in fig. 4H, a re-routing layer (RDL) trace 458 is first formed from bottom to top on a side of the plastic package body 440 exposing the active surface 411 of the first level semiconductor devices 410, 410' (including the first level interconnect pads 412), and then landing pads 452 respectively corresponding to the second level interconnect bumps 462 of the second level semiconductor devices 460 are formed to form conductive paths of the first level interconnect pads 412 to the corresponding landing pads 452. In this process, particularly when RDL traces 458 and/or landing pads 452 are formed, dielectric layer 455 is also formed to provide electrical isolation between the conductive paths. In addition, a plurality of second level alignment pads 454 corresponding to the plurality of second level alignment solder bumps 464, respectively, are also formed on the dielectric layer 455. Thereby, the first stage semiconductor device 450 is formed.

In some embodiments, external interconnect terminals are also formed on the interconnect layer such that a portion of the plurality of first level interconnect pads are electrically connected to the external interconnect terminals through the interconnect layer. As an example, the conductive path between them is realized by the aforesaid RDL. It should be appreciated that, in this case, among the plurality of first-level interconnect pads, the first-level interconnect pad electrically connected to the transit terminal and the first-level interconnect pad electrically connected to the external interconnect terminal may be independent of each other or may be at least partially overlapped (i.e., electrically connected to both the transit terminal and the external interconnect terminal). It is understood that the external interconnect terminals are used to interconnect the final package (i.e., the integrated package of the first level device and the second level device) with another level device (e.g., a semiconductor device, an interconnect board, or a PCB board). Therefore, it is applicable to a case where the second-stage device has no through electrode (such as TSV, TGV, PTH or via), but is not excluded from a case where the second-stage device is provided with a through electrode. For example, the external interconnect terminals may provide interconnection with another level device along with the aforementioned additional interconnect terminals formed on the second surface of the second level device (hereinafter referred to as "first external connection terminals" and "second external connection terminals", respectively, for ease of distinction), it being understood that the first external connection terminals need to be sufficiently high (e.g., the solder balls are large in size when the first external connection terminal is in the form of solder balls) so that the first external connection terminals and the second external connection terminals lie substantially in the same parallel plane (i.e., relative to the first level assembly) after the second level device is aligned and secured to the first level assembly, as described below, in order to effect interconnection with the another level device. As an example, the external interconnect terminal distribution is formed to be sufficiently spaced apart from the second level second alignment solder so as not to be covered by a perpendicular projection of the plurality of second level devices onto the interconnect layer after the plurality of second level devices are precisely aligned to the first level assembly so as not to affect stacking of subsequent second level devices onto the interconnect layer.

As an exemplary embodiment, as shown in fig. 4H', external interconnect terminals 456 are further formed on the basis of fig. 4H so as to be sufficiently distant from second level alignment pads 454, and a conductive path is formed with a portion of first level interconnect pads 412 through RDL traces.

S370: the at least one second stage device is placed on the first stage assembly such that the plurality of second stage first alignment welds are substantially aligned with the plurality of second stage second alignment welds.

The "basic alignment" herein may optionally refer to the aforementioned description of the "basic alignment" between the first-stage first alignment weld and the first-stage second alignment weld in S320, and thus will not be described herein.

It should be appreciated that when the second stage device is placed on the first stage assembly in step S370, the second stage first surface of the second stage device faces the first stage assembly (i.e., the surface on which the second stage second alignment weld is formed).

As an exemplary embodiment, as shown in fig. 4I, a second level semiconductor device 460 is placed on the first level semiconductor package 450 such that the second level alignment solder bumps 464 are in contact with the corresponding second level alignment pads 454. At this point, the second level alignment solder bumps 464 are not centered with the second level alignment pads 454.

S380: forming a plurality of second-stage alignment pads by soldering the plurality of second-stage first alignment pads and the plurality of second-stage second alignment pads such that the at least one second-stage device is precisely aligned to the first-stage assembly, and bonding the plurality of second-stage interconnect terminals and the plurality of transit terminals, respectively, while pressing the at least one second-stage device and the first-stage assembly toward each other in a state in which the plurality of second-stage alignment pads are at least partially melted, to form a plurality of interconnect joints.

The "forming the plurality of second-stage first alignment welds and the plurality of second-stage second alignment welds by welding so that the at least one second-stage device is precisely aligned to the first-stage assembly" herein may optionally refer to the foregoing description about S330, and thus will not be repeated herein.

It should be appreciated that after the second level first alignment bond is bonded to the second level second alignment bond, the second level first surface of the second level device (including the second level interconnect terminals) and the first level assembly are spaced apart to form a space therebetween due to the height of the second level alignment bond itself (in a direction perpendicular to the second level first surface of the second level device) formed thereby.

In some embodiments, the second level alignment solder bumps are made of solder and the soldering may be by a variety of molten solder soldering means known in the art including, but not limited to, reflow soldering, laser soldering, high frequency soldering, infrared soldering, and the like. As an example, soldering may be performed using a flux or a cream solder.

In some embodiments, in S380, while the at least one second stage device is in precise alignment with the first stage assembly and the plurality of second stage alignment pads are still in an at least partially molten state, the plurality of second stage interconnect terminals and the interposer terminal are respectively engaged while pressing the at least one second stage device and the first stage assembly toward each other. In other embodiments, after the at least one second stage device is precisely aligned and secured to the first stage assembly, the second stage alignment pads are again at least partially melted and the plurality of second stage interconnect terminals and the interposer terminal are respectively engaged while pressing the at least one second stage device and the first stage assembly toward each other in S380.

In some embodiments, the second level interconnect bump and/or the transfer bump is made of solder, and the plurality of second level interconnect terminals and the transfer terminal are soldered to form an interconnect pad in S380. In some embodiments, the second level interconnect bump and/or the transfer bump does not include solder, and the plurality of second level interconnect terminals and the transfer terminal are Thermally Compression Bonded (TCB) in S380.

As an exemplary embodiment, as shown in fig. 4J, second level alignment solder bumps 464 and second level alignment pads 454 are soldered to form second level alignment solder bumps 466. During the soldering process, the second level alignment solder bumps 464 in a molten state infiltrate the second level alignment pads 454 and self-align with the second level alignment pads 454 based on their own minimum surface energy principle, so that the second level semiconductor device 460 is brought into precise alignment on the first level semiconductor device 450. After the soldering is completed, the active surface of the second stage semiconductor device 460 is spaced apart from the first stage semiconductor assembly 450 to form a space. Then, as shown in fig. 4K, the second-stage semiconductor device 460 and the first-stage semiconductor assembly 450 are pressed toward each other while heating is performed. At this point, the second level alignment pad 466 again at least partially melts and is further flattened, and the second level interconnect bump 462 (also in an at least partially melted state) is brought into contact with the landing pad 452 and a second level interconnect pad 468 is formed.

In some embodiments, further comprising: the second stage alignment pads in an at least partially molten state after the integral flipping further improve the self-alignment accuracy by utilizing the weight of the second stage device. As an example, reference may be selectively made to S331 or S330' previously described.

S390: releasing the pressing.

In some embodiments, the pressing is released after the second level alignment pads and/or the interconnection joints are at least partially solidified to secure the at least one second level device to the first level assembly. It should be appreciated that the time required for the second level alignment pads and/or the interconnection joints to at least partially solidify to secure the at least one second level device to the first level assembly is predictable theoretically and empirically or is measurable through previous experimentation, and that the compression may be optionally released after the time has elapsed.

In some embodiments, when the carrier does not have an interconnection structure or a product function, the packaging method further includes: and removing the carrier plate. As an example, the carrier plate is removed in any one step or between any two steps of S340 to S390.

In some embodiments, the carrier plate is removed by a process known in the art of lift-off, etching, ablating, grinding, and the like. As an example, when a lift-off process is used, the solder between the carrier and the first stage device (i.e., the first stage alignment solder joint) may be desoldered to facilitate the lift-off of the carrier from the plastic package.

In some embodiments, some or all of the first stage alignment pads are also removed when or after the carrier plate is removed. By way of example, some or all of the first level alignment pads may be removed by a process known in the art such as reflow, etching, ablating, or grinding. In some embodiments, some or all of the first level alignment pads are reserved as part of the final semiconductor assembly (i.e., the final package) for electrical connections (e.g., power and ground), heat dissipation, mechanical structure, etc.

In some embodiments, after removing the carrier plate, further comprising: and thinning (such as grinding, etching or ablating) the surface of the plastic package body from which the carrier plate is removed. As an example, the thinned portion is thinned to remove a portion of the plastic package (including a portion of the remaining first level alignment pad) on the first level second surface side of the first level device, or thinned to the first level second surface of the first level device, or thinned portion includes a portion of the first level second surface side of the first level device. It should be appreciated that the first level alignment pads remaining after the carrier plate is removed are also removed by this thinning process. Thereby, the thickness of the final semiconductor assembly can be further reduced.

As an exemplary embodiment, as shown in fig. 4L, the heat is removed until after the second level alignment pad 466 and the second level interconnect pad 468 are substantially solidified, the press is removed. Carrier 420 (and the first level alignment pads) is then removed by de-soldering first level alignment pads 416, thereby forming semiconductor assembly 400.

It should be appreciated that due to the height of the second level alignment pads and/or the interconnect joints themselves, a space is created between the second level devices and the first level components. In some embodiments, further comprising: and underfilling a space formed between the second stage device and the first stage assembly.

In some embodiments, the passive devices are packaged with the at least first stage devices into a first stage assembly in substantially the same manner as the embodiments described above.

In some embodiments, after S390, further comprising: cutting is performed.

It should be understood that the dicing process may be performed to make individual semiconductor assemblies according to package specifications, or not.

Based on similar inventive concepts, the present application also provides a packaging method according to another embodiment, which is mainly different from the aforementioned packaging method according to the embodiment shown in fig. 3 in that: the first level interconnect pads of the first level devices are not fanned out (i.e., no interconnect layers are formed), but rather the interconnections between the first level interconnect pads of the first level devices and the second level interconnect terminals of the second level devices (interconnect bumps only, or a combination of interconnect bumps and second level first alignment solder joints) are made directly. Accordingly, in order to avoid unnecessarily obscuring the inventive concept, a description of portions that are substantially identical or have not been substantially changed from the embodiment shown in fig. 3 will be omitted in the following description of the packaging method according to this embodiment, and the foregoing corresponding description for the embodiment shown in fig. 3 will be referred to.

Fig. 5 shows a flow chart of a packaging method according to another embodiment of the present application. As shown in fig. 5, the packaging method includes the steps of:

s410: providing at least one first level device, at least one second level device, a carrier plate and a clamping plate, wherein the first level device is formed with a plurality of first level interconnection pads on a first level first surface and a plurality of first level first alignment welds on a first level second surface opposite the first level first surface; the at least one second-level device is provided with a plurality of second-level interconnection bumps and a plurality of second-level first alignment welding parts on a second-level first surface, wherein the second-level interconnection bumps respectively correspond to at least one part of the first-level interconnection pads; a plurality of first-stage second alignment welding parts corresponding to the plurality of first-stage first alignment welding parts respectively are formed on the carrier plate; and at least one of the carrier plate and the clamping plate is penetrated with an opening for injection molding.

It should be appreciated that in order to directly interconnect at least a portion of the plurality of first level interconnect pads of the at least one first level device with the plurality of second level interconnect bumps of the at least one second level device, at least a portion of the plurality of first level interconnect pads need to correspond in volume, size, geometry, composition, distribution, location, and number to each other with the plurality of second level interconnect bumps so that at least a portion of the plurality of first level interconnect pads can be precisely centered with the plurality of second level interconnect bumps when the at least one second level device is precisely aligned to a respective target location on the first level component for stacking interconnect between the at least one second level device and the first level component as described below.

In some embodiments, the plurality of second level interconnect bumps correspond to the plurality of first level interconnect pads, respectively. In an alternative embodiment, the plurality of second level interconnect bumps and the plurality of second level first alignment welds together function as a plurality of second level interconnect terminals on the second level first surface of the at least one second level device and respectively correspond to the plurality of first level interconnect pads.

As an exemplary embodiment, as shown in fig. 6A, two first stage semiconductor devices 510, 510', a second stage semiconductor device 560, a carrier plate 520, and a chucking plate 530 are provided. The two first level semiconductor devices 510, 510' are not identical, e.g., are different in size and/or function. It will be appreciated that although only the first stage semiconductor device 510 is shown with reference numerals for relevant portions thereof in fig. 6A for ease of illustration and will be described below in connection therewith, the description applies equally to corresponding similar portions of the first stage semiconductor device 510'. Each first level semiconductor device 510, 510' is formed with a plurality of first level interconnect pads 512 distributed on the active surface 511 and a plurality of first level alignment solder bumps 514 formed on the passive surface 513. The second level semiconductor device 560 is formed with a plurality of second level interconnection bumps 562 and a plurality of second level alignment solder bumps 564 distributed on the active surface 561 as interconnection terminals respectively corresponding to the first level interconnection pads 512, and the second level semiconductor device 560 is further provided with TSVs 565 electrically connected to the second level alignment solder bumps 564 and part of the second level interconnection bumps 562, respectively. A plurality of first level alignment pads 524 are formed on one surface of the carrier 520 in the same arrangement (or relative positional relationship) as the first level alignment solder bumps 514 on the respective first level semiconductor devices 510, 510'. Openings 538 for injection molding are formed therethrough in regions between the target locations of the clamping plate 530 corresponding to the first stage semiconductor devices 510, 510'. Alternatively, passive devices may be provided in a similar structure in addition to the first-stage semiconductor device and the second-stage semiconductor device. For example, reference numeral 510' as shown in fig. 6A may be replaced with a passive device.

S420 to S440: substantially the same as S320 to S340, respectively, described above.

S450: the clamping plate is removed to expose the first stage first surface, thereby forming a first stage assembly.

As an exemplary embodiment, as shown in fig. 6B, the plastic package 540 exposes the active surfaces 511 of the first level semiconductor devices 510, 510', i.e., exposes the first level interconnect pads 512, by removing the clamping plate 530, thereby forming the first level semiconductor assembly 550.

S460: the at least one second stage device is placed on the first stage assembly such that the plurality of second stage first alignment welds are substantially aligned with the plurality of second stage second alignment welds on the first stage assembly, wherein the plurality of second stage second alignment welds are preformed on a side of the first stage assembly that exposes the first stage first surface and correspond to the plurality of second stage first alignment welds, respectively.

In some embodiments, when the plurality of second level interconnect bumps correspond to the plurality of first level interconnect pads, respectively, between S450 and S460 further comprises: the plurality of second stage second alignment welds are formed on a side of the first stage assembly that exposes the first stage first surface. As an alternative embodiment, when the plurality of second level interconnection bumps correspond to the plurality of first level interconnection pads, respectively, and the second level first alignment solder joints have a form of an alignment solder bump, the first level device is further formed with the plurality of second level second alignment solder joints having a form of an alignment solder pad on the first level first surface in S410.

In some embodiments, when the plurality of second level interconnection bumps and the plurality of second level first alignment welds together serve as a plurality of second level interconnection terminals on the second level first surface of the at least one second level device, respectively corresponding to the plurality of first level interconnection pads, and the plurality of second level first alignment welds have a morphology of alignment welds, a portion of the plurality of first level interconnection pads, respectively corresponding to the plurality of second level first alignment welds, is taken as the plurality of second level second alignment welds in S460. As an alternative embodiment, when the plurality of second level interconnect bumps and the plurality of second level first alignment solder joints together serve as a plurality of second level interconnect terminals on the second level first surface of the at least one second level device, respectively corresponding to the plurality of first level interconnect pads, between S450 and S460, further include: and forming a plurality of second-stage second alignment solder joints having a form of alignment solder bumps on a portion of the plurality of first-stage interconnection pads respectively corresponding to the plurality of second-stage first alignment solder joints.

It should be appreciated that the sum of the heights of the first level interconnect pad and the second level interconnect bump is substantially less than the sum of the heights of the second level first alignment bond pad and the second level second alignment bond pad in a direction perpendicular to the second level first surface of the second level device (or the side surface of the first level assembly that exposes the first level first surface), such that the first level interconnect pad and the second level interconnect bump are also spaced apart from each other after the second level first alignment bond pad and the second level second alignment bond pad are subsequently formed.

As an exemplary embodiment, as shown in fig. 6C, a second level semiconductor device 560 is placed on the first level semiconductor assembly 550 such that the second level alignment solder bumps 564 are in contact with the corresponding first level interconnect pads 512. At this point, the second level alignment solder bumps 564 are not centered with the corresponding first level interconnect pads 512.

S470: forming a plurality of second level alignment pads by soldering the plurality of second level first alignment pads and the plurality of second level second alignment pads such that the at least one second level device is precisely aligned to the first level component, and bonding the plurality of second level interconnect bumps with corresponding first level interconnect pads, respectively, while pressing the at least one second level device and the first level component toward each other in a state in which the plurality of second level alignment pads are at least partially melted, to form a plurality of interconnect joints.

In some embodiments, in S470, while the at least one second level device is in precise alignment with the first level assembly and the plurality of second level alignment pads are still in an at least partially molten state, the plurality of second level interconnect bumps and corresponding first level interconnect pads are respectively engaged while the at least one second level device and the first level assembly are pressed toward each other. In other embodiments, after the at least one second level device is precisely aligned and secured to the first level assembly, the second level alignment pads are again at least partially melted and the plurality of second level interconnect bumps and corresponding first level interconnect pads are respectively bonded while the at least one second level device and the first level assembly are pressed toward each other in S470.

In some embodiments, the second level interconnect bumps are made of solder, and the plurality of second level interconnect bumps and corresponding first level interconnect pads are soldered, respectively, to form interconnect pads in S470. In some embodiments, the second level interconnect bumps do not contain solder, and the plurality of second level interconnect bumps and corresponding first level interconnect pads are thermocompression bonded in S470.

As an exemplary embodiment, as shown in fig. 6D, second level alignment solder bumps 564 and corresponding first level interconnect pads 512 are soldered to form second level alignment solder bumps 566. During the soldering process, the second level alignment solder bumps 564 in a molten state infiltrate the corresponding first level interconnect pads 512 and self-align with the corresponding first level interconnect pads 512 based on their own minimum surface energy principle, so as to bring the second level semiconductor device 560 into precise alignment on the first level semiconductor assembly 550. After the soldering is completed, the active surface of the second level semiconductor device 560 is spaced apart from the first level semiconductor assembly 550 to form a space. Then, as shown in fig. 6E, the second-stage semiconductor device 560 and the first-stage semiconductor assembly 550 are pressed toward each other while heating is performed. At this point, second level alignment pad 566 is again at least partially melted and further flattened, and second level interconnect bump 562 (also in an at least partially melted state) is brought into contact with first level interconnect pad 512 and second level interconnect pad 568 is formed.

S480: substantially the same as S390 described above.

It will be apparent to those skilled in the art that various changes and modifications can be made to the embodiments of the present application without departing from the spirit and scope of the application. Thus, if such changes and modifications of the present application fall within the scope of the claims and their equivalents, the disclosure of the present application is intended to cover such changes and modifications as well.

Claims

1. A semiconductor packaging method, comprising:

s350: removing the clamping plate to expose the first stage first surface;

s360: sequentially forming an interconnection layer and a plurality of transfer terminals respectively corresponding to the plurality of second-stage interconnection terminals on one side of the plastic package body exposing the first-stage first surface, so that at least one part of the plurality of first-stage interconnection pads is respectively electrically connected to the plurality of transfer terminals through the interconnection layer, and a plurality of second-stage alignment welding parts respectively corresponding to the plurality of second-stage first-stage alignment welding parts are also formed on the interconnection layer, thereby forming a first-stage assembly;

S390: releasing the pressing.

2. The semiconductor packaging method of claim 1, wherein at least one of the at least one first level device and the at least one second level device comprises at least one of a semiconductor device and an interconnect board, the interconnect board being an interposer or a substrate.

3. The semiconductor packaging method of claim 1, wherein at least one of the at least one first level device and the at least one second level device is further provided with at least one through electrode.

4. The semiconductor packaging method according to claim 1, wherein any one of the plurality of first-stage first alignment solder portions and the plurality of first-stage second alignment solder portions has a form of an alignment solder bump and the other has a form of an alignment pad corresponding to the alignment solder bump, or the plurality of first-stage first alignment solder portions and the plurality of first-stage second alignment solder portions each have a form of an alignment solder bump; and any one of the plurality of second-stage first alignment welds and the plurality of second-stage second alignment welds has a form of an alignment solder bump and the other has a form of an alignment pad corresponding to the alignment solder bump, or the plurality of second-stage first alignment welds and the plurality of second-stage second alignment welds each have a form of an alignment solder bump.

5. The semiconductor packaging method according to claim 1, wherein any one of the plurality of second-stage interconnect terminals and the plurality of transit terminals has a form of an interconnect bump and the other has a form of an interconnect pad, or the plurality of second-stage interconnect terminals and the plurality of transit terminals each have a form of an interconnect bump.

6. The semiconductor packaging method according to claim 1, wherein a sum of heights of the second-stage interconnection terminal and the transit terminal is smaller than a sum of heights of the second-stage first alignment solder and the second-stage second alignment solder in a direction perpendicular to the second-stage first surface of the at least one second-stage device, such that the second-stage interconnection terminal and the transit terminal are spaced apart from each other before the pressing in S380.

7. The semiconductor packaging method according to claim 1, wherein a plurality of external interconnect terminals are further formed on the interconnect layer in the S360 such that a part of the plurality of first-stage interconnect pads is electrically connected to the plurality of external interconnect terminals through the interconnect layer.

8. The semiconductor packaging method of claim 7, wherein the plurality of external interconnect terminals are spaced apart from the second level second alignment solder such that after the plurality of second level devices are precisely aligned to the first level assembly in S380, they are not covered by a vertical projection of the plurality of second level devices onto the interconnect layer.

9. The semiconductor packaging method of claim 1, wherein in the S380, the plurality of second level interconnect terminals and the plurality of transit terminals are respectively engaged while pressing the at least one second level device and the first level assembly toward each other while the at least one second level device and the first level assembly are brought into precise alignment with the first level assembly and while the plurality of second level alignment pads are still in an at least partially molten state.

10. The semiconductor packaging method of claim 1, wherein in the S380, after the at least one second level device is precisely aligned and fixed to the first level assembly, the second level alignment pads are again at least partially melted, and the plurality of second level interconnect terminals and the plurality of interposer terminals are respectively bonded while the at least one second level device and the first level assembly are pressed toward each other.

11. The semiconductor packaging method of claim 5, wherein the interconnect bump is made of solder and the bonding the plurality of second level interconnect terminals and the plurality of transit terminals, respectively, in S380 to form a plurality of interconnect joints comprises: the plurality of second level interconnect terminals and the plurality of transit terminals are soldered to form interconnect pads.

12. The semiconductor packaging method of claim 5, wherein the interconnect bump contains no solder and the bonding the plurality of second level interconnect terminals and the plurality of transit terminals, respectively, in S380 to form a plurality of interconnect joints comprises: and performing thermocompression bonding on the plurality of second-stage interconnection terminals and the transfer terminal.

13. The semiconductor packaging method of claim 1, wherein the pressing is released after the plurality of second level alignment pads and/or the plurality of interconnect joints are at least partially solidified to secure the at least one second level device to the first level assembly.

14. A semiconductor packaging method, comprising:

s480: releasing the pressing.

15. The semiconductor packaging method according to claim 14, wherein any one of the plurality of first-stage first alignment solder joints and the plurality of first-stage second alignment solder joints has a form of an alignment solder bump and the other has a form of an alignment pad corresponding to the alignment solder bump, or the plurality of first-stage first alignment solder joints and the plurality of first-stage second alignment solder joints each have a form of an alignment solder bump; and any one of the plurality of second-stage first alignment welds and the plurality of second-stage second alignment welds has a form of an alignment solder bump and the other has a form of an alignment pad corresponding to the alignment solder bump, or the plurality of second-stage first alignment welds and the plurality of second-stage second alignment welds each have a form of an alignment solder bump.

16. The semiconductor packaging method of claim 14, wherein the plurality of second level interconnect bumps correspond to the plurality of first level interconnect pads, respectively.

17. The semiconductor packaging method of claim 14, wherein the plurality of second level interconnect bumps and the plurality of second level first alignment welds together serve as a plurality of second level interconnect terminals on the second level first surface of the at least one second level device and respectively correspond to the plurality of first level interconnect pads.

18. The semiconductor packaging method of claim 16, wherein between the S450 and the S460 further comprises: the plurality of second stage second alignment welds are formed on a side of the first stage assembly that exposes the first stage first surface.

19. The semiconductor packaging method of claim 16, wherein the second level first alignment solder has a form of an alignment solder bump, and the first level device is further formed with the plurality of second level second alignment solder having a form of an alignment pad on the first level first surface in the S410.

20. The semiconductor packaging method according to claim 17, wherein the second-stage first alignment solder has a form of an alignment solder bump, and a portion of the plurality of first-stage interconnect pads corresponding to the plurality of second-stage first alignment solder portions, respectively, is taken as the plurality of second-stage second alignment solder portions in the S460.

21. The semiconductor packaging method of claim 17, wherein between the S450 and the S460 further comprises: and forming a plurality of second-stage second alignment solder joints having a form of alignment solder bumps on a portion of the plurality of first-stage interconnection pads respectively corresponding to the plurality of second-stage first alignment solder joints.

22. The semiconductor packaging method of claim 14, wherein at least one of the at least one first level device and the at least one second level device comprises at least one of a semiconductor device and an interconnect board, the interconnect board being an interposer or a substrate.

23. The semiconductor packaging method of claim 14, wherein at least one of the at least one first level device and the at least one second level device is further provided with at least one through electrode.

24. The semiconductor packaging method of claim 14, wherein a sum of heights of the first level interconnect pad and the second level interconnect bump is smaller than a sum of heights of the second level first alignment bond and the second level second alignment bond in a direction perpendicular to the second level first surface of the at least one second level device such that the first level interconnect pad and the second level interconnect bump are spaced apart from each other before the pressing in S470.

25. The semiconductor packaging method of claim 14, wherein in the S470, the plurality of second level interconnect bumps and corresponding first level interconnect pads are respectively bonded while pressing the at least one second level device and the first level component toward each other while the at least one second level device is in precise alignment with the first level component and the plurality of second level alignment pads are still in an at least partially molten state.

26. The semiconductor packaging method of claim 14, wherein in the S470, after the at least one second level device is precisely aligned and fixed to the first level assembly, the second level alignment pad is again at least partially melted, and the plurality of second level interconnect bumps and corresponding first level interconnect pads are respectively bonded while the at least one second level device and the first level assembly are pressed toward each other.

27. The semiconductor packaging method of claim 14, wherein the second level interconnect bumps are made of solder and the bonding the plurality of second level interconnect bumps and corresponding first level interconnect pads, respectively, in S470 to form a plurality of interconnect joints comprises: and respectively welding the plurality of second-stage interconnection bumps and the corresponding first-stage interconnection pads to form interconnection welding spots.

28. The semiconductor packaging method of claim 14, wherein the second level interconnect bumps do not contain solder and the bonding the plurality of second level interconnect bumps and corresponding first level interconnect pads, respectively, in S470 to form a plurality of interconnect joints comprises: and performing hot-press binding on the second-stage interconnection bumps and the corresponding first-stage interconnection pads.

29. The semiconductor packaging method of claim 14, wherein the pressing is released after the plurality of second level alignment pads and/or the plurality of interconnect joints are at least partially solidified to secure the at least one second level device to the first level assembly.

30. A semiconductor component packaged by the semiconductor packaging method according to any one of claims 1 to 29.

31. An electronic device comprising the semiconductor assembly of claim 30.