TW202232611A - Semiconductor packaging method, semiconductor assembly and electronic equipment comprising semiconductor assembly - Google Patents

Abstract

The invention discloses a semiconductor packaging method, a semiconductor assembly and electronic equipment comprising the semiconductor assembly. The semiconductor packaging method comprises the following steps: enabling a first-stage device to be automatically and accurately aligned and fixed to a target position on a carrier plate by utilizing the self-alignment capability of a first-stage alignment welding spot between the first-stage device and the carrier plate; the carrier plate is used for supporting one side of the first-stage device, the clamping plate is used for abutting against the other side of the first-stage device, and meanwhile injection molding is carried out through the through opening of the carrier plate or the clamping plate to achieve the plastic packaging technology; a second-stage device is automatically and accurately aligned and fixed to a target position on the first-stage assembly by utilizing the self-alignment capability of a second-stage alignment welding spot between the first-stage assembly and the second-stage device, so that the speed of picking and placing the first-stage device and the second-stage device is remarkably improved; and the process efficiency is improved; and the process cost is reduced.

Description

Semiconductor packaging method, semiconductor element, and electronic equipment including the same

The embodiments of the present application relate to the technical field of semiconductor manufacturing, and in particular, to a semiconductor packaging method, a semiconductor element, and an electronic device including the semiconductor element.

Semiconductor packages and systems have been pursuing dense, small, light, and thin designs while striving to achieve high integration and versatility in functionality. At present, various packaging technologies have been proposed to meet the above technical requirements, such as Fan-out wafer level packaging, chiplet, heterogeneous integration, 2.5D/3D (2.5D/3D) ) package. These packaging technologies have their own distinct advantages and characteristics, but all present some technical challenges. Taking the existing fan-out package as an example, it faces many technical problems, such as warpage, die shift, surface flatness (toporgraphy), and non-coplanarity between the die and the plastic package (chip). -to-mold non-planarity), package reliability (Reliability), etc. Despite continuous efforts in the industry to improve these technical problems by improving equipment, materials, and process links, there are still no economical and effective solutions to some technical problems, especially for warpage, wafer drift and surface coplanarity between different wafers Program.

In addition, in various high-end semiconductor packaging and system manufacturing processes, there are also some common technologies, which often involve high-precision placement and fixing of semiconductor devices. This process step is usually carried out by high-precision pick and place (pick and place or die bonder) equipment, but its placement speed is limited, which makes the production speed very slow, and the equipment cost is expensive, which has become a major bottleneck for technology development and popularization.

The present application aims to solve several of the above-mentioned core technical problems.

The present application aims to propose a new breakthrough semiconductor packaging method, a semiconductor element, and an electronic device including the semiconductor element, so as to at least solve the above-mentioned and other technical problems existing in the prior art.

An aspect of the present application provides a semiconductor packaging method, including:

S310: Provide at least one first-level device, at least one second-level device, a carrier board, and a clamping board, wherein the first-level device has a plurality of first-level interconnect pads formed on the first-level first surface and is A plurality of first-level first-level alignment welds are formed on a first-level second surface opposite to the first-level first surface; the at least one second-level device is formed on the second-level first surface a plurality of second-level interconnection terminals and a plurality of second-level first-level alignment welding parts; a plurality of first-level first-level alignment welding parts corresponding to the first-level first-level welding parts are formed on the carrier board respectively a second alignment welding part; and an opening for injection molding is formed through at least one of the carrier plate and the clamping plate;

S320: Place the at least one first-level device on the carrier board, so that the plurality of first-level first-level alignment soldering parts are substantially aligned with the plurality of first-level second-level alignment soldering parts ;

S330: Form a plurality of first-level alignment solder joints by welding the plurality of first-level first-level alignment welding portions and the plurality of first-level second-level alignment soldering portions, so that the at least one The first stage device is precisely aligned and secured to the carrier;

S340: performing injection molding through the opening to form a plastic package covering the at least one first-level device between the carrier board and the splint pre-attached on the first-level first surface;

S350: Remove the splint to expose the first-level first surface;

S360: Sequentially form an interconnection layer and a plurality of transfer terminals corresponding to the plurality of second-level interconnect terminals on the side of the plastic package exposed to the first-level first surface, so that the plurality of At least a part of the first-level interconnect pads are respectively electrically connected to the plurality of transfer terminals through the interconnection layer, and first pairs with the plurality of second-level first pairs are also formed on the interconnection layer. a plurality of second-level second-level alignment-welding parts corresponding to the quasi-welding parts respectively, thereby forming a first-level element;

S370: Place the at least one second-level device on the first-level component, so that the plurality of second-level first-aligned solders are substantially the same as the plurality of second-level second-aligned solders alignment;

S380: Form a plurality of second-level alignment solder joints by welding the plurality of second-level first-level alignment welding portions and the plurality of second-level second-level alignment solder portions, so that the at least one A second-level device is precisely aligned to the first-level component, and the at least one second-level device and the first-level device are fused together in a state where the plurality of second-level alignment pads are at least partially melted. respectively engaging the plurality of second-level interconnect terminals and the plurality of transition terminals while pressing the stage elements toward each other to form a plurality of interconnect junctions; and

S390: Release the pressing.

Another aspect of the present application provides a semiconductor packaging method, comprising:

S410: Provide at least one first-level device, at least one second-level device, a carrier board, and a clamping board, wherein the first-level device has a plurality of first-level interconnect pads formed on the first-level first surface and is A plurality of first-level first-level alignment welds are formed on a first-level second surface opposite to the first-level first surface; the at least one second-level device is formed on the second-level first surface a plurality of second level interconnect bumps and a plurality of second level first alignment pads, wherein the plurality of second level interconnect bumps and at least a portion of the plurality of first level interconnect pads corresponding respectively; a plurality of first-level second-level alignment welding portions corresponding to the first-level first-level first-level alignment welding portions are formed on the carrier plate; At least one is formed with an opening for injection molding therethrough;

S420: Place the at least one first-level device on the carrier board, so that the plurality of first-level first-level alignment soldering parts are substantially aligned with the plurality of first-level second-level alignment soldering parts ;

S430: Form a plurality of first-level alignment solder joints by welding the plurality of first-level first-level alignment welding parts and the plurality of first-level second-level alignment welding parts, so that the at least one The first stage device is precisely aligned and secured to the carrier;

S440: performing injection molding through the opening to form a plastic package covering the at least one first-level device between the carrier board and the splint pre-attached on the first-level first surface;

S450: removing the splint to expose the first-level first surface, thereby forming a first-level element;

S460 : Place the at least one second-level device on the first-level component, so that the plurality of second-level first-aligned welding parts and the plurality of second-level first-level components on the first-level component Two alignment welds are substantially aligned, wherein the plurality of second level second alignment welds are pre-formed on a side of the first level element that exposes the first level first surface and are aligned with the first level The plurality of second-level first alignment welding parts correspond respectively;

S470: Form a plurality of second-level alignment solder joints by welding the plurality of second-level first-level alignment welding portions and the plurality of second-level second-level alignment solder portions, so that the at least one A second-level device is precisely aligned to the first-level component, and the at least one second-level device and the first-level device are fused together in a state where the plurality of second-level alignment pads are at least partially melted. separately bonding the plurality of second-level interconnect bumps and corresponding first-level interconnect pads while pressing the level elements toward each other to form a plurality of interconnect bonding points; and

S480: Release the pressing.

Yet another aspect of the present application provides a semiconductor element packaged by the above-mentioned semiconductor packaging method.

Still another aspect of the present application provides an electronic device including the above-mentioned semiconductor element.

It should be understood that the above description is only an overview of the present application, so that the technical solutions of the present application can be understood more clearly, so that it can be implemented according to the contents of the description. In order to make the above and other objects, features and advantages of the present application more clearly understood, specific embodiments of the present application are described in detail below.

The present application contains at least one embodiment in the following description with reference to the accompanying drawings, wherein like numerals refer to the same or similar components throughout the drawings. While the following description is primarily based on specific embodiments, those of ordinary skill in the art will understand that the following description is intended to cover the present application as defined by the appended claims and their equivalents and as supported by the following description and accompanying drawings Alternatives, modifications, and equivalent technical means or solutions within the inventive concept and scope. In the following description, some specific details, such as specific configurations, compositions, and processes, are given in order to provide a thorough understanding of the present application. In other instances, specific details of well-known processes and fabrication techniques have not been described in order to avoid unnecessarily obscuring the present application. Furthermore, the various embodiments shown in the figures are schematic illustrations and not necessarily to scale.

Semiconductor components (also known as semiconductor packages) are the core components of modern electronic equipment or products. Semiconductor components can be roughly divided into: discrete semiconductor components, that is, single-chip components, such as single digital logic processors, diodes, triodes; multi-chip components, such as image sensors (CIS) and image processing unit (ASIC) modules, central processing unit (CPU) and dynamic memory device (DRAM) stacking; and system-level components such as RF front-end modules (FEMs) in mobile phones, mobile phones and Display module in smart watch. Usually, system-level components include a wide range of devices, in addition to semiconductor devices, there are passive components (resistors, capacitors, inductors) and other devices and even components.

The semiconductor components herein can include active and passive devices, including but not limited to bipolar transistors, field effect transistors, integrated circuits and other active devices and chip resistors, capacitors, inductors, integrated passive components ( IPD), micro-electromechanical systems (MEMS) and other passive devices. Various electrical connections are made between various active and passive devices to form circuits that enable semiconductor elements to perform high-speed computations and other useful functions.

Currently, semiconductor fabrication typically consists of two complex manufacturing processes, front-end wafer fabrication and back-end packaging fabrication, each of which may involve hundreds of steps. Front-end wafer fabrication involves forming multiple dies on the surface of a wafer. Each wafer is typically identical and internally contains circuitry formed by electrically connecting active and/or passive cells. Back-end packaging manufacturing involves separating individual dies from finished wafers and packaging them into semiconductor components to provide electrical connections, structural support, and environmental isolation, while facilitating subsequent assembly of electronic products.

An important goal of semiconductor manufacturing is to produce smaller semiconductor devices, packages and components. Smaller products generally have higher integration, lower power consumption, higher performance and smaller area/volume, which is very important for the market performance of the final product. On the one hand, smaller integrated circuits can be fabricated by improving the front-end wafer process, thereby shrinking the die, increasing the density and improving the performance. On the other hand, the back-end packaging process can further reduce the size, increase the density and improve the performance of semiconductor components by improving the packaging design, process and packaging materials.

At present, in the back-end packaging process, a relatively novel and efficient packaging method is fan-out packaging. Fan-out packages typically use a molding compound to encapsulate a single or multiple qualified dies from a diced wafer and route interconnect traces from the die's connection pads to external via a redistribution layer (RDL). Solder ball packaging technology for higher I/O density and flexible integration. Fan-out packaging can be mainly divided into chip-first packaging and chip-last packaging. The chip-first type package can be further divided into an active surface-down (face-down) type and an active surface-up (face-up) type.

The mainstream process for chip-first/face-down type packaging can include the following major steps: pick up a chip from a diced wafer and place it on a carrier with an adhesive film with its active surface facing the adhesive film; use a molding compound Mold the side where the die is mounted; remove the carrier (along with the adhesive film) to expose the active surface of the die; form the interconnect layers (including the RDL layer and the under bump metal (UBM) on the active surface of the die )); forming solder balls on the interconnect layer, wherein the wafer's interconnect pads or interconnect bumps are electrically connected to the solder balls through the interconnect layer; and dicing to form individual semiconductor elements.

The chip-first/face-up type packaging process can be roughly the same as the chip-first/face-down type packaging process, the main difference is that the active surface of the die is picked and placed on the adhesive film carrier. back-to-back adhesive film; thinning of the molding compound on the active surface side of the wafer after molding to expose interconnect bumps on the active surface of the wafer; and the carrier can be removed after the interconnect layer and solder balls are formed.

Among the technical problems currently faced by fan-out packaging, there is still a lack of efficient and economical methods for high-precision placement and position fixation of chips. Usually, the higher the wafer placement accuracy, the higher the equipment cost and the lower the production efficiency, and the accuracy of the wafer loading equipment is difficult to break through the 0.5 micron limit. In addition, after the chip is placed on the film, the film is glued to fix the position, but the adhesive film is deformable. During the molding process, the flow of the molding compound will push the chip, resulting in the chip on the film. displacement and rotation. The higher temperatures used in the molding process exacerbate this problem. Another source of wafer displacement and rotation is internal stress within the mold. Specifically, in the existing chip-first/face-up type packaging process, the plastic packaging process includes three stages of heating injection molding, partial curing of the plastic sealing compound at high temperature, and cooling. Usually followed by a thermostatically heated molding compound to fully cure. There are differences in the thermal expansion coefficients of wafers, molding compounds, adhesive films, carrier boards, etc. Therefore, during the molding process, the mismatch of thermal expansion coefficients of various materials and the curing shrinkage of the molding compound lead to uneven internal stress of the molding, which further causes wafer drift and and/or rotation (as shown in the wafer arrangement in the lower right of Figure 1) and warpage of the mold body (the form in which the wafer and carrier are overmolded with mold compound). Wafer drift and/or rotation can cause subsequent redistribution (RDL) traces and under-bump metal (UBM) location mismatch or misalignment (as shown in the top right of Figure 2 after wafer drift and rotation occurs). shown), which may result in a significant drop in yield. The warpage of the plastic package will cause difficulties to the subsequent packaging process (including the formation of RDL and UBM), and even the subsequent process cannot be continued in severe cases.

In addition, in the back end packaging process, depending on the specific packaging specifications, it may be necessary to further realize the substrate in the Z-axis direction based on the two-dimensional integration of the X-Y plane (eg, the plane parallel to the active or passive surface of the wafer) Interconnect integration (eg in system-in-package), interposer board (eg in 2.5D packaging) or another layer of die (eg in 3D packaging). At this time, similar to the aforementioned fan-out package, there is at least a lack of efficient and economical methods for high-precision placement and position fixation of the upper-layer device on the lower-layer device. In addition, as for the interconnection between upper and lower layer devices in 3D packaging (eg, TSMC's InFO (integrated fan-out), CoWoS (chip-on-wafer on substrate), SoIC (system-on-chip)), as the current mainstream A key technology is hybrid bonding. However, there are also many technical difficulties in hybrid bonding. In addition to common problems such as high cost and low production efficiency, there are also many other problems. For example, chemical mechanical polishing (CMP) is difficult to meet the strict requirements for pad concave The difference in pad density in different areas affects the depth of recess, the pad (metallic copper) is easily oxidized at high temperature, and the die is prone to contamination in hybrid bonding of die-to-wafer.

The purpose of this application is to propose a new and breakthrough packaging method that can at least solve the above-mentioned technical problems.

The packaging method according to the embodiment of the present application utilizes the self-alignment capability of the first-level alignment joints between the first-level device and the carrier when the solder is at least partially melted to make the first-level device automatically accurate Align the target position on the carrier board and fix the position of the first-level device after the solder solidifies, wherein the first-level second surface of the first-level device (ie, the opposite surface of the first-level first surface) and the carrier One side of the board is respectively pre-formed with a first-level first-level alignment welding portion and a corresponding first-level second-level alignment welding portion (for example, one of which is a first-level alignment welding bump and the other is a first-level alignment pads; or both first-level alignment solder bumps). The packaging method causes the first-level first-level alignment after placing the first-level device on the carrier board at the target location so that the first-level first-level alignment bond and the first-level second alignment bond contact each other One (or both) of the solder joints and the first-level second-level alignment solder joints are melted to form the first-level alignment solder joints if the first-level device is not precisely aligned to the target location on the carrier (ie, the first-level first-level alignment weld and the first-level second-alignment weld are misaligned), then the at least partially molten state (liquid or partially liquid) first-level alignment weld is based on the minimum surface energy The principle automatically introduces the first-level device precisely to the target location for surface energy minimization, and the first-level alignment pads hold the first-level device firmly in the target location after curing. The first-level first-aligned welds and the first-level second-aligned welds (in terms of volume, geometry, composition, location, distribution and quantity, etc.) are optimally designed to achieve the most accurate and efficient , Efficient and reliable self-alignment capability. Since the first-level device is fixed on the carrier board by welding instead of film bonding, it not only improves the warpage problem, but also prevents the possible drift and rotation of the first-level device during the plastic sealing process through a firm welding method. The self-alignment capability of the first-level alignment solder joints allows a certain degree of placement deviation when picking and placing first-level devices, which can significantly reduce the placement accuracy of first-level devices (especially for pick and place machines). place or die bonder)), and can significantly increase the speed of the first-level device pick and place operation, thereby improving process efficiency and reducing process costs.

Secondly, while the packaging method according to the embodiment of the present application supports the first-level second surface side of the first-level device with the carrier board and uses the clamping plate to press against the first-level first surface of the first-level device, the carrier board or The through-openings of the splint are injection molded to achieve the molding process, so there is no need to drill the molding to expose the interconnect pads after the molding process, compared to existing chip-first/face-up type packaging processes, or only The surface of the mold body needs to be slightly cleaned (eg, plasma cleaning) after the molding process to keep the interconnect pad surface clean, which not only improves the efficiency of the molding process, but also avoids thinning (eg, grinding) or Accidental damage to the first-level first surface of the first-level device caused by processes such as drilling, thereby improving yield.

In addition, according to the packaging method of the embodiment of the present application, the second-level device (interconnect board (eg, a substrate or an interposer) or a semiconductor device is performed on the first-level element including the first-level device. ) Z-axis interconnection integration also utilizes the self-alignment capability of the second-level alignment solder joints between them when the solder is at least partially melted to automatically and accurately align the second-level devices on the first-level components. The target position of the second-level device is fixed after the solder is solidified, and the second-level first pair of the second-level device is pre-formed on the second-level first surface of the second-level device and the corresponding surface of the first-level element. A quasi-bond and a corresponding second-level second-level alignment bond (eg, one is a second-level alignment solder bump and the other is a second-level alignment pad; or both are second-level level alignment solder bumps). Similarly, due to the self-alignment capabilities of the second-level alignment pads, a degree of placement deviation can be tolerated when picking and stacking second-level devices on first-level components, which can significantly reduce the impact on second-level components. Device placement accuracy (especially for pick and place or die bonder) requirements, and can significantly increase the speed of second-level device pick and place operations, thereby further improving process efficiency and reducing process costs. In addition, by replacing the hybrid bonding method, the aforementioned technical difficulties in hybrid bonding can be avoided, thereby realizing simple and efficient 3D packaging.

The term "semiconductor device" as used herein may refer to a wafer (also interchangeably referred to as a die, die, die, integrated circuit) produced in a fab, that is, diced and A wafer that has not yet been packaged after testing, which typically has only interconnect pads for external connections. As desired, the semiconductor device may also be a pre-processed (at least partially packaged) wafer, eg with interconnect bumps formed on interconnect pads, or the semiconductor device may also have additional structures, eg stacked Wafers or packaged wafers or semiconductor components.

The term "active surface" as used herein generally refers to the side surface of a semiconductor device that has a circuit function, having interconnection pads (or interconnection bumps formed on interconnection pads) thereon, and is also interchangeable is called the frontal or functional side. The active surface of the semiconductor device and the other side surface (interchangeably referred to as the passive surface or the back surface) that does not function as a circuit face each other.

The term "interconnect terminal" as used herein generally refers to an interconnect pad or an interconnect bump on an active surface of a semiconductor device.

The term "alignment weld" as used herein generally refers to a structure that can be welded to a corresponding other alignment weld for alignment by welding methods known in the art.

FIG. 3 shows a schematic flowchart of a packaging method according to an embodiment of the present application. As shown in Figure 3, the packaging method includes the following steps:

S310: Provide at least one first-level device, at least one second-level device, a carrier board, and a clamping board, wherein the first-level device has a plurality of first-level interconnect pads formed on the first-level first surface and is A plurality of first-level first alignment welding parts are formed on a first-level second surface opposite to the first-level first surface, and the at least one second-level device is formed with a plurality of first-level first surfaces. a plurality of second-level interconnection terminals and a plurality of second-level first-level alignment soldering portions, and a plurality of first-level first-level alignment soldering portions corresponding to the plurality of first-level first-level alignment soldering portions are formed on the carrier. For the second alignment welding portion, an opening for injection molding is formed through at least one of the carrier plate and the clamping plate.

In some embodiments, the first stage device is plural. As an example, the plurality of first-level devices may at least partially differ from each other in function, size, or shape, or may be identical to each other. In some embodiments, the second stage device is plural. As an example, the plurality of second-level devices may at least partially differ from each other in function, size, or shape, or may be identical to each other. It should be understood that the size or shape of the carrier board, the first-level device and the second-level device, the first-level device and the second-level device may vary according to specific process conditions or actual requirements (eg, the placement pitch, package size or shape, manufacturing process specification, or functional design of the final semiconductor element, etc.) appropriately select the type and specific quantity of the first-level device and the second-level device, and this application does not Specially limited.

In some embodiments, the carrier is a glass carrier, a ceramic carrier, a metal carrier, an organic polymer material carrier, or a silicon wafer or a combination of two or more of the aforementioned materials. Optionally, the carrier board has an interconnect structure or product function. As an example, an interconnection board is employed as the carrier board, the interconnection board being a substrate (such as a package substrate) or an interposer. For example, the interposer provides horizontal and/or vertical interconnects. As an example, the first-level second alignment soldering portion serves as an interconnection terminal of the interconnection board.

In some embodiments, the first-level device is a first-level semiconductor device. When the first-level device is a first-level semiconductor device, the plurality of first-level interconnect pads are formed on an active surface of the first-level semiconductor device and a plurality of first-level interconnect pads are formed on an inactive surface The plurality of first-level first alignment welds are described. In other embodiments, the first level device is an interconnect board. As an example, the interconnect board is a substrate (such as a package substrate) or an interposer. For example, the interposer provides horizontal and/or vertical interconnects.

In some embodiments, either of the first level first alignment weld and the first level second alignment weld is a first level alignment weld bump, and the other is a The first-level alignment pads are aligned with the first-level alignment pads corresponding to the solder bumps. In other embodiments, the first-level first alignment welding portion and the first-level second alignment welding portion are both first-level alignment welding bumps and their melting points may be the same or different. . As an example, the first-level alignment solder bumps may be pre-fabricated on the first stage using a bump fabrication process known in the art (eg, electroplating, ball-mounting, template printing, evaporation/sputtering, etc.). level device and/or on the carrier board. As an example, the first-level alignment pads may be prefabricated on the first-level device or carrier using a deposition (eg, metal layer)-lithography-etch process. It should be understood that the first-level first alignment welding portion and the first-level second alignment welding portion can also adopt any other structure or form as long as they can be welded to each other for alignment purpose.

In some embodiments, the first-level first aligned welds and the first-level second aligned welds correspond to each other in volume, size, geometry, composition, distribution, location, and number, etc., such that The first level devices can be precisely aligned to the respective target positions on the carrier board by soldering to each other.

It should be understood that the selected device can be appropriately selected according to specific process conditions or actual requirements (for example, the size or shape of the carrier board and the first-level device, the placement distance of the first-level device, the package size or shape, etc.). The specific volume, size, geometric shape, composition, distribution, location and quantity of the first-level first alignment welding portion and/or the first-level second alignment welding portion are not particularly limited in this application. For example, for a plurality of first-level devices, the first-level first-level alignment welds may be formed with substantially the same volume, size, geometry, or composition, regardless of whether they are identical in function, size, or shape to each other, and the carrier board The first-level and second-aligned welding portions on the above can be formed into substantially the same volume, size, geometry or composition, so as to reduce the complexity of the subsequent process and improve the packaging efficiency. For another example, for a plurality of first-level devices with different functions, sizes or shapes, the first-level first-level alignment welding parts and the first-level second-level alignment welding parts may be formed into different volumes, sizes, Geometry or composition so that different solder joint heights can be formed after subsequent soldering to achieve a specific function or to meet a specific requirement. In some embodiments, for a plurality of first-level devices, the first-level first-level alignment bonds and/or the first-level second-level alignment bonds are arranged such that subsequent soldering forms a first-level pair of The first-level first surfaces of the plurality of first-level devices can be located in the same plane parallel to the carrier after the solder joints are prepared. For another example, each of the first-level devices may be formed with at least three first-level first-level alignment welding portions that are substantially regularly distributed, so that the first-level second surfaces of the first-level devices can pass through The welding of the first-level first alignment weld and the first-level second alignment weld is held firmly and stably in a plane substantially parallel to the carrier plate. For another example, on each of the first-level devices, the first-level first-level alignment soldering portion may be formed in a region near the edge on the first-level second surface, so as not to affect subsequent processes and products application.

Optionally, the first-level device is further provided with at least one through electrode for vertical interconnection. For example, for the first-level semiconductor device, the through electrodes are through silicon vias (TSVs). For another example, for the interposer, the through electrodes are TSVs or through glass vias (TGVs). For another example, for the substrate, the through electrode is a plated through hole (PTH) or a via hole (via). It can be understood that, at this time, the first-level device may further be formed with additional interconnection terminals on the first-level second surface opposite to the first-level first surface (for example, the first-level first surface Alignment welding portion can also be used as at least a part thereof), and one end of the at least one through electrode is respectively electrically connected to at least a part of the plurality of first-level interconnection pads and the other end of the at least one through electrode is respectively are respectively electrically connected to the further interconnection terminals.

In some embodiments, the second-level device is a second-level semiconductor device. When the second-level device is a second-level semiconductor device, the plurality of second-level interconnect terminals and the plurality of second-level first-level interconnect terminals are formed on an active surface of the second-level semiconductor device Align the weld. In other embodiments, the second level device is an interconnect board. As an example, the interconnect board is a substrate (such as a package substrate) or an interposer. For example, the interposer provides horizontal and/or vertical interconnects.

As an illustrative embodiment, at least one of the at least one first-level device and the at least one second-level device includes at least one semiconductor device.

In some embodiments, the second-level first alignment solder portion is a second-level alignment solder bump or a second-level alignment pad. As an example, the second-level alignment solder bumps may be pre-fabricated on the second-level using a bump fabrication process known in the art (eg, electroplating, ball-mounting, template printing, evaporation/sputtering, etc.). level device. As an example, the second-level alignment pads may be prefabricated on the second-level device using a deposition (eg, metal layer)-lithography-etch process.

It should be understood that, according to specific process conditions or actual requirements (for example, the size or shape of the first-level device and the second-level device, the placement distance of the first-level device and the second-level device, the packaging The specific volume, size, geometric shape, composition, distribution, location and number of the second-stage first alignment welding portion are appropriately selected, and the present application does not make any special limitation on this. For example, for multiple second-level devices, the second-level first alignment welds may be formed to be substantially the same volume, size, geometry, or composition regardless of whether the function, size, or shape are identical to each other, so as to reduce subsequent Process complexity and improve packaging efficiency. As another example, for multiple second-level devices that differ in function, size, or shape, the second-level first-aligned welds may be formed with different volumes, sizes, geometries, or compositions so that they may be formed after subsequent welding Different solder joint heights to achieve specific functions or meet specific requirements. For another example, each of the second-level devices may be formed with at least three second-level first-level alignment welding portions that are substantially regularly distributed, so that the second-level first surfaces of the second-level devices can pass through The second level of alignment solder joints formed by the later described soldering are held firmly and stably in a plane substantially parallel to the carrier board. For another example, on each of the second-level devices, the second-level first-aligned solder portions may be distributed on edges sufficiently far away from the second-level interconnect terminals so as not to affect subsequent processes and Applications.

In some embodiments, the second level interconnect terminals are second level interconnect bumps. As an example, the second-level interconnect bumps may be pre-fabricated on the second-level using a bump fabrication process known in the art (eg, electroplating, ball mounting, template printing, evaporation/sputtering, etc.). on the interconnect pads of the device. For example, the second level interconnect bumps may be in the form of conductive pillars. In an alternative embodiment, the second level interconnect terminals are second level interconnect pads. Optionally, the second level device is further provided with at least one through electrode for vertical interconnection. For example, for the second level semiconductor device, the through electrodes are through silicon vias (TSVs). For another example, for the interposer, the through electrodes are TSVs or through glass vias (TGVs). For another example, for the substrate, the through electrode is a plated through hole (PTH) or a via hole (via). It can be understood that, at this time, the second-level device may further be formed with another interconnection terminal on the second-level second surface opposite to the second-level first surface, and one end of the at least one through electrode are respectively electrically connected with at least a part of the plurality of second-level interconnection terminals and the other ends of the at least one through electrode are respectively electrically connected with the other interconnection terminals.

In some embodiments, the opening is formed on the carrier plate such that the opening is spaced apart from the first level second alignment weld. As an example, the opening is provided outside an area defined by the target location of the at least one first-level device on the carrier. For example, where there are multiple first-level devices, the openings are provided in regions between target locations of the multiple first-level devices. In some embodiments, the opening is formed on the splint such that the opening is in contact with the first level first surface of the at least one first level device when the splint is attached The first stage first surfaces are spaced apart. In some embodiments, the opening is formed in both the carrier plate and the splint. It should be understood that the size, geometry, number or distribution of the openings can be appropriately selected according to the process conditions or actual requirements (for example, plastic sealing materials) related to subsequent plastic sealing, and as long as the injection molding can be performed effectively to achieve the purpose of plastic sealing, the present application will This is not particularly limited.

As an exemplary embodiment, as shown in Figure 4A, two first-level semiconductor devices 410, 410' The two first-level semiconductor devices 410, 410' are not identical, eg, in size and/or function. It can be understood that although only the first-level semiconductor device 410 is shown with reference numerals of relevant parts thereof in FIG. 4A for the purpose of convenience of explanation and the following description is combined with it, the description is also applicable to the first-level semiconductor device 410 ' corresponding analogous part. Each first-level semiconductor device 410 , 410 ′ is formed with a plurality of first-level interconnection pads 412 distributed on the active surface 411 , and a plurality of first-level alignment solder bumps 414 are formed on the passive surface 413 . The second-level semiconductor device 460 is formed with a plurality of second-level interconnect bumps 462 and a plurality of second-level first-aligned solder bumps 464 distributed on the active surface 461 . A plurality of corresponding first-levels are formed on a surface of the carrier board 420 in the same arrangement (or relative positional relationship) as the first-level alignment solder bumps 414 on the first-level semiconductor devices 410 and 410 ′. Align pads 424 . Openings 428 for injection molding are formed therethrough in regions between the target positions corresponding to the first-stage semiconductor devices 410 and 410' on the carrier board 420 . Alternatively, in addition to the first-level semiconductor device and the second-level semiconductor device, passive devices may also be provided in a similar structure. For example, reference numeral 410' as shown in FIG. 4A may be replaced with passive devices.

S320: Place the at least one first-level device on the carrier board, so that the plurality of first-level first-level alignment soldering parts are substantially aligned with the plurality of first-level second-level alignment soldering parts .

In some embodiments, the "substantially aligned" includes the first level first alignment weld and the first level second alignment weld, respectively, in contact with each other, but not perpendicular to the first level Accurate alignment in the direction of the second surface of the stage. "Centered" herein generally means that the centers of the first level first alignment weld and the first level second alignment weld are aligned in a direction perpendicular to the first level second surface. It should be noted that the "substantial alignment" between the first-level first-level alignment welding portion and the first-level second-aligning welding portion indicates that there are at least the first-level first-level alignment welding portion and all the first-level alignment welding portions. The contact between the first-level and second-level alignment welds is such that self-alignment is possible as described below by means of the minimum surface energy principle of the first-level alignment welds in an at least partially molten state during the welding process. Therefore, "substantially aligned" includes the state of not being precisely aligned but at least in physical contact, but may also not exclude the state of being precisely aligned.

It should be understood that when the first-level device is placed on the carrier board in step S320, the first-level second surface of the first-level device faces the carrier board (ie, the surface on which the first-level first alignment solder portion is formed) , the first-level first surface of the first-level device faces away from the carrier.

As an exemplary embodiment, as shown in FIG. 4B , the first-level semiconductor devices 410 , 410 ′ are placed on the carrier board 420 such that the first-level alignment solder bumps 414 are aligned with the corresponding first-level alignment pads 424 contact. At this time, the first-level alignment solder bumps 414 are not aligned with the first-level alignment pads 424 , that is, the vertical centerlines L1 of the first-level alignment solder bumps 414 and the first-level alignment pads 424 The vertical centerlines L2 do not coincide.

S330: Form a plurality of first-level alignment solder joints by welding the plurality of first-level first-level alignment welding portions and the plurality of first-level second-level alignment soldering portions, so that the at least one The first stage devices are precisely aligned and secured to the carrier.

It should be noted that "accurate alignment" refers to a state in which the deviation between the actual position of the first-level device on the carrier board and the target position is within the tolerance range in the art. It should be understood that the precise alignment refers to the minimum surface of the solder joint formed by welding the first-level first-level alignment weld portion and the first-level second-level alignment weld portion in the at least partially molten state during the welding process. principle can be realized. Specifically, when the first-level first-level alignment bond and the first-level second-level alignment bond contact each other but are not precisely centered in the direction perpendicular to the first-level second surface or carrier board of the first-level device During the welding process, one of the first-level first-level alignment welding part and the first-level second-level alignment welding part, which is the first-level alignment welding bump, is at least partially melted and wetted as the first-level alignment welding bump. The other side of the first-level alignment pad or another first-level alignment solder bump, or the first-level first-level alignment bond and the first-level second-level alignment bond both serve as a first-level pair The quasi-solder bumps are at least partially melted, thereby forming first-level alignment solder joints in an at least partially molten state, where the first-level alignment solder joints in an at least partially molten state tend to be based on the principle of minimum surface energy. During deformation and movement, the first-level first alignment welding part and the first-level second alignment welding part are close to the centering state, so as to drive the first-level device that is lighter relative to the carrier board for precise alignment to the target position on the carrier board.

It should be understood that, after welding the first-level first-level alignment welding portion and the first-level second-level alignment welding portion, due to the height of the first-level alignment welding point itself formed by the welding the direction of the first-level second surface of the first-level device or the carrier), the first-level second surface of the first-level device and the carrier are spaced apart to form a certain space therebetween. space.

In some embodiments, the first-level alignment solder bumps are made of solder, and the soldering can be performed by various molten solder soldering methods known in the art, including but not limited to reflow soldering, laser soldering, high Frequency welding, infrared welding, etc. As an example, soldering may be performed using flux or solder paste.

As an exemplary embodiment, as shown in FIG. 4C , first-level alignment solder bumps 414 and first-level alignment pads 424 are soldered to form first-level alignment pads 416 . During the soldering process, the first-level alignment solder bumps 414 in a molten state wet the first-level alignment pads 424 and self-align with the first-level alignment pads 424 based on their own minimum surface energy principle (ie, the vertical centerlines L1 of the first-level alignment solder bumps 414 and the vertical centerlines L2 of the first-level alignment pads 424 are coincident), so that the first-level semiconductor devices 410, 410' are driven on the carrier board. Precise alignment on the 420. After soldering is completed, the passive surfaces 413 of the first-level semiconductor devices 410, 410' are separated from the carrier 420 to form a space.

In some embodiments, after S330, it further includes S331: inverting the first-level device and the carrier board as a whole, so that the first-level first surface of the first-level device faces downwards, The first-level alignment solder joint is at least partially melted again, and then the temperature is lowered to solidify the first-level alignment solder joint. It should be understood that the first-level alignment pads, which are at least partially melted again at this time, are moderately elongated due to the weight of the first-level device, thereby further improving the self-alignment accuracy. It should be noted that, due to the surface energy of the first-level alignment solder joints in an at least partially molten state, the first-level device will not fall off the carrier board due to its own weight. As an alternative embodiment, in S310, viscous flux is pre-applied on the plurality of first-level first alignment welding parts and/or the first-level second alignment welding parts, and S330 includes S330' : Before performing the soldering, the first-level device and the carrier board are turned over as a whole, so that the first-level first surface of the first-level device faces downwards. It should be understood that, after turning over at this time, the first-level alignment solder joint at least partially melted during the soldering process is moderately elongated due to the weight of the first-level device, thereby further improving the self-alignment accuracy. It should be noted that, since the first-level device and the carrier board are adhered by the adhesive flux, the first-level device will not fall off from the carrier board due to its own weight after being turned over. It should be understood that, before S340 described below, the first-level device and the carrier board as a whole can also be turned over again as needed.

In some embodiments, when there are multiple first-level devices, S330 includes S330 ″: precise alignment is formed between the first-level devices and the carrier and the first-level alignment pads While still in an at least partially molten state, the first-level first surfaces of the plurality of first-level devices are flattened by a leveling plate, so that the first-level first surfaces of the plurality of first-level devices are flattened. The primary first surface lies substantially in the same plane parallel to the carrier. As an example, S330 ″ includes: placing the platen over the first-level first surfaces of the plurality of first-level devices; and pressing the platen toward the carrier, so that the plurality of first-level devices the first level first surface of the device lies substantially in the same plane parallel to the carrier board; while maintaining pressure, cooling is performed to substantially solidify the first level alignment pads; and removing the Flatten. As an alternative embodiment, when there are multiple first-level devices, S332 is further included after S330: after the first-level alignment solder joints are at least partially melted again, use a pressing plate to align the multiple first-level devices. The first-level first surfaces of the first-level devices are flattened, so that the first-level first surfaces of the plurality of first-level devices are substantially located in the same plane parallel to the carrier board. As an example, the S332 includes: melting the first-level alignment pads at least partially again; placing the platen over the first-level first surfaces of the plurality of first-level devices; facing the carrier pressing the platen so that the first-level first surfaces of the plurality of first-level devices are substantially located in the same plane parallel to the carrier plate; while maintaining the pressing, the temperature is lowered to make the The first stage alignment welds are substantially solidified; and the flattened plate is removed. It will be appreciated that since the pressing is maintained until the first stage alignment pads are substantially solidified and the flattening plate is not removed, the surface energy of the molten solder joints can be prevented from restoring the first stage device to its original height before flattening.

As an exemplary embodiment, as shown in FIG. 4D, after the first-level alignment pads 416 are again in an at least partially molten state by heating, a pressure is placed on the active surface 411 of the first-level semiconductor devices 410, 410' The flat plate P is pressed (ie, toward the carrier plate 420 ) to perform the flattening process, so that the active surfaces of the first-stage semiconductor devices 410 , 410 ′ are in the same plane parallel to the carrier plate 420 . Subsequently, the temperature is lowered while maintaining pressing to solidify the first-level alignment pads 416, and then the platen P is removed.

Thereby, the first-level first surfaces of all the first-level devices can be made to be exactly flush and at the same height. It will be appreciated that appropriate pressure needs to be applied to the flattening plate to properly deform the first-stage alignment pads in an at least partially molten state and the resulting vertical (relative to the first-stage, first-stage, first-stage device) A surface or carrier) is properly displaced to prevent damage to the first-level device. As an example, a solder trap is pre-formed on the periphery of the first-level second alignment welding portion of the carrier board, thereby preventing an uncontrolled random flow of excess molten solder during the pressing process.

In some embodiments, the above-mentioned flattening process using a flattening plate is combined with the above-mentioned inversion welding process or re-melting process. As an example, S330'' is executed after S330' is executed in S330, or S332 is executed after S330 including S330' is executed, or S331 is executed after S330 including S330'' is executed, or S332 is executed when S331 is executed.

S340: Perform injection molding through the opening to form a plastic package covering the at least one first-level device between the carrier plate and the clamping plate pre-attached on the first-level first surface.

It should be understood that, through the injection molding, not only the sides of the first-level device are clad, but also the space between the first-level second surface of the first-level device and the carrier plate is filled with cladding. It can be understood that the first surface of the first stage is substantially flat, so the splint is basically in close contact with the first surface of the first stage. Therefore, through the injection molding, the first stage device includes the first stage The first surface of the first level including the interconnect pads will not be clad.

It should be understood that the injection molding is performed through the openings formed in the carrier plate and/or the clamping plate according to S310.

In some embodiments, S330 includes S330''': attaching the splint on the first-level first surface of the at least one first-level device. As an example, S330''' is performed before S330'' is performed in S330. In other embodiments, S333 is further included between S330 and S340: attaching the splint on the first-level first surface of the at least one first-level device. As an example, S333 is performed before S332. As another example, S333 is performed after S332. As yet another example, S333 is performed after S330 including S330''. In still other embodiments, the flattened plate is retained as the splint after the flattening process in S330" or S332. Thus, by reusing the flattening plate as a plywood, the materials required for the process can be reduced and the entire process flow can be simplified. As an example, S330 includes: when the plurality of first-level devices are precisely aligned with the carrier board but the plurality of first-level alignment solder joints are still at least partially melted, using the clamping plate as a The flattening plate flattens the first-level first surfaces of the plurality of first-level devices, so that the first-level first surfaces of the plurality of first-level devices are substantially located with the carrier plate parallel in the same plane until the first-level alignment solder joints are substantially solidified. As another example, between S330 and S340, the method further includes: after the first-level alignment solder joints are at least partially melted again, using the clamping plate as a pressing plate to align the first-level devices of the plurality of first-level devices. The first-level first surface is flattened, so that the first-level first surfaces of the plurality of first-level devices are substantially located in the same plane parallel to the carrier board, until the first-level alignment welding is performed The point is basically solidified.

In some embodiments, the splint is made of glass, ceramic, metal, organic polymer material or silicon wafer or a combination of two or more of the above materials.

In some embodiments, molding is performed with a molding compound of a resinous material (eg, epoxy).

As an exemplary embodiment, as shown in FIG. 4E , after attaching the splint 430 on the active surface 412 of the first-stage semiconductor devices 410 and 410 ′, as shown in FIG. 4F , injection molding is performed through the opening 428 of the carrier board 420 , Thus, a plastic package 440 covering the first-level semiconductor devices 410 and 410 ′ is formed between the carrier board 420 and the clamping board 430 .

S350: Remove the splint to expose the first-level first surface.

In some embodiments, the splint is removed by lift-off, etching, ablation, grinding, etc. processes known in the art.

As an exemplary embodiment, as shown in FIG. 4G , by removing the splint 430 , the overmolded body 440 exposes the active surface 411 of the first-level semiconductor device 410 , 410 ′, ie, exposes the first-level interconnect pad 412 .

S360: Sequentially form an interconnection layer and a plurality of transfer terminals corresponding to the plurality of second-level interconnect terminals on the side of the plastic package that is exposed to the first-level first surface, so that the At least a part of the plurality of first-level interconnection pads are respectively electrically connected to the plurality of via terminals through the interconnection layer, and the interconnection layer is also formed with the plurality of second-level first-level interconnection pads. A plurality of second-level second-level alignment welding portions corresponding to an alignment welding portion respectively, thereby forming a first-level element.

In some embodiments, the interconnect layer includes a redistribution layer (RDL), thereby enabling conductive paths between the first level interconnect pads and the via terminals. It should be understood that the interconnection layer also includes an insulating layer for realizing electrical insulation between the conductive paths, and the specific quantity and material of the insulating layer can be appropriately selected according to specific process conditions or needs, which is not particularly limited in this application. .

In some embodiments, either of the second level first alignment weld and the second level second alignment weld is a second level alignment weld bump, and the other is a The second-level alignment pads corresponding to the second-level solder bumps are aligned. In other embodiments, the second-level first alignment welding portion and the second-level second alignment welding portion are both second-level alignment welding bumps, and their melting points may be the same or different. . As an example, as the second-level second alignment soldering part, the second-level alignment soldering bumps may adopt a bump fabrication process known in the art (eg, electroplating method, ball mounting method, template printing method) , evaporation/sputtering, etc.). As an example, as the second-level second alignment bonding portion, the second-level alignment pad may employ a deposition (eg, metal layer)-lithography-etching process. It should be understood that the second-level first alignment welding portion and the second-level second alignment welding portion can also adopt any other structure or form as long as they can be welded to each other for alignment purpose.

In some embodiments, the second-level second aligned welds correspond to each other in volume, size, geometry, composition, distribution, location, and number, etc., such that the second-level first aligned welds The second level devices can be precisely aligned to respective target positions on the first level components by soldering to each other.

It should be understood that, according to specific process conditions or actual requirements (for example, the size or shape of the first-level device and the second-level device, the placement distance of the first-level device and the second-level device, the packaging The specific volume, size, geometric shape, composition, distribution, location and number of the second-stage second alignment welding portion are appropriately selected, and the present application does not make any special limitation on this. For example, the second-level second-level alignment welds on the first-level components can all be formed with substantially the same volume, size, geometry, or composition in order to reduce subsequent process complexity and improve packaging efficiency. As another example, for multiple second-level devices that differ in function, size, or shape, the second-level second-level alignment welds may be formed with different volumes, dimensions, geometries, or compositions so that they may be formed after subsequent soldering Different solder joint heights to achieve specific functions or meet specific requirements.

In some embodiments, the second level interconnect terminals are second level interconnect bumps and the via terminals are via bumps or via pads. In other embodiments, the second level interconnect terminals are second level interconnect pads and the via terminals are via bumps. As an example, the fabrication of the via bumps may adopt a bump fabrication process known in the art (eg, electroplating method, ball mounting method, template printing method, evaporation/sputtering method, etc.), and the fabrication of the transfer pads may be performed using The deposition (eg, metal layer)-lithography-etching process known in the art is not particularly limited in this application.

In some embodiments, the transit terminals and the second-level interconnect terminals correspond to each other in terms of volume, size, geometry, composition, distribution, location, and number, such that the second-level device is in When the first-level components are precisely aligned to the corresponding target positions, the transfer terminals and the second-level interconnect terminals can be accurately centered for the second-level device and the second-level device to be described later. Stacked interconnects between primary components.

It should be understood that in a direction perpendicular to the second-level first surface of the second-level device (or the interconnection layer of the first-level element), the second-level interconnect terminals and the transfer terminals The sum of the heights of the second-level first alignment welding portion and the second-level second alignment welding portion is sufficiently smaller than the sum of the heights of the second-level first alignment welding portion and the second-level second alignment welding portion, so that the second-level interconnection terminal and the transfer terminal are The second-level first alignment welding portion and the second-level second alignment welding portion are also spaced apart from each other after the second-level alignment welding point is subsequently formed, so as not to affect the second-level first alignment welding Subsequent soldering of the second-level interconnection terminals and the transfer terminals to the second-level first-aligned welds and the second-level Subsequent welding of the stage second alignment welds is damaged when pressed against each other.

As an exemplary embodiment, as shown in FIG. 4H , the side of the plastic package 440 that exposes the active surfaces 411 (including the first-level interconnect pads 412 ) of the first-level semiconductor devices 410 , 410 ′ is bottom-up Redistribution layer (RDL) traces 458 are formed first, followed by via pads 452 respectively corresponding to second-level interconnect bumps 462 of second-level semiconductor device 460 to form first-level interconnect pads 412 to The conductive paths of the corresponding via pads 452 . During this process, especially when the RDL traces 458 and/or via pads 452 are formed, a dielectric layer 455 is also formed to provide electrical isolation between the conductive paths. In addition, a plurality of second-level alignment pads 454 corresponding to the plurality of second-level alignment solder bumps 464 are also formed on the dielectric layer 455 . Thus, the first-stage semiconductor element 450 is formed.

In some embodiments, external interconnect terminals are further formed on the interconnect layer such that a portion of the plurality of first level interconnect pads are electrically connected to the external interconnect terminals through the interconnect layer . As an example, the conductive path between them is achieved by the aforementioned RDL. It should be understood that, among the plurality of first-level interconnection pads, the first-level interconnection pads electrically connected to the transfer terminals and the first-level interconnection pads electrically connected to the external interconnection terminals The connection pads may be independent of each other, or may at least partially overlap (ie, be electrically connected to both the transfer terminal and the external interconnection terminal). It can be understood that the external interconnection terminals are used to interconnect the final package (ie, the integrated package of the first-level device and the second-level device) with another level device (eg, a semiconductor device, an interconnection board, or a PCB board). even. Therefore, it can be applied to the scenario where the second-level device does not have through electrodes (such as TSV, TGV, PTH or via), but does not exclude the scenario where the second-level device has through electrodes. For example, the external interconnection terminal may be together with the aforementioned additional interconnection terminal formed on the second surface of the second-level device (for convenience of distinction, hereinafter referred to as "first external connection terminal" and "second external connection terminal", respectively "connection terminal") provides interconnection with another level of device, it should be understood that the first external connection terminal needs to be high enough at this time (for example, when the first external connection terminal terminal is in the form of a solder ball, the size of the solder ball is larger), so that As will be described later, after the second-level device is aligned and fixed to the first-level element, the first external connection terminal and the second external connection terminal are substantially in the same parallel plane (ie, relative to the first-level element), so as to realize the connection with the other-level device. interconnection. As an example, external interconnect terminals are formed to be spaced sufficiently apart from the second-level second-level alignment welds so that after the plurality of second-level devices are precisely aligned to the first-level elements, they are not The vertical projection of the plurality of second-level devices on the interconnect layer is covered, so as not to affect the stacking of subsequent second-level devices on the interconnect layer.

As an exemplary embodiment, as shown in FIG. 4H ′, on the basis of FIG. 4H , an external interconnection terminal 456 is further formed so as to be sufficiently far away from the second-level alignment pad 454 , and is formed with a portion of the first Conductive paths for level interconnect pads 412 .

S370: Place the at least one second-level device on the first-level component, so that the plurality of second-level first-aligned solders are substantially the same as the plurality of second-level second-aligned solders alignment.

The “substantial alignment” here can optionally refer to the aforementioned “substantial alignment” between the first-level first alignment welding portion and the first-level second alignment welding portion in S320. description, and therefore will not be repeated here.

It should be understood that when the second-level device is placed on the first-level component in step S370, the second-level first surface of the second-level device faces the first-level component (ie, the second-level second alignment solder is formed with the second-level component). surface of the part).

As an exemplary embodiment, as shown in FIG. 4I , second-level devices 460 are placed on first-level semiconductor elements 450 such that second-level alignment solder bumps 464 are aligned with corresponding second-level alignment pads 454 touch. At this point, the second-level alignment solder bumps 464 are misaligned with the second-level alignment pads 454 .

S380: Form a plurality of second-level alignment solder joints by welding the plurality of second-level first-level alignment welding portions and the plurality of second-level second-level alignment solder portions, so that the at least one A second-level device is precisely aligned to the first-level component, and the at least one second-level device and the first-level device are fused together in a state where the plurality of second-level alignment pads are at least partially melted. The plurality of second-stage interconnect terminals and the plurality of transfer terminals are respectively engaged while the stage elements are pressed toward each other to form a plurality of interconnection joints.

Herein, "a plurality of second-level alignment solder joints are formed by welding the plurality of second-level first-level alignment solder portions and the plurality of second-level second-level alignment solder portions so that the "The precise alignment of at least one second-level device to the first-level element" can selectively refer to the foregoing description about S330, and thus will not be repeated here.

It should be understood that after welding the second-level first-level alignment welding portion and the second-level second-level alignment welding portion, due to the height of the second-level alignment welding point itself (at the perpendicular to the in the direction of the second-level first surface of the second-level device), the second-level first surface of the second-level device (including the second-level interconnect terminals) and the first-level element are spaced apart to be in the There is a certain space between them.

In some embodiments, the second-level alignment solder bumps are made of solder, and the soldering can be performed using various molten solder soldering methods known in the art, including but not limited to reflow soldering, laser soldering, high Frequency welding, infrared welding, etc. As an example, soldering may be performed using flux or solder paste.

In some embodiments, in S380, when the at least one second-level device is in precise alignment with the first-level component and the plurality of second-level alignment pads are still in an at least partially molten state , engaging the plurality of second-level interconnect terminals and the transfer terminals, respectively, while pressing the at least one second-level device and the first-level element toward each other. In other embodiments, in S380, after the at least one second-level device is precisely aligned and secured to the first-level component, the second-level alignment pads are again at least partially melted, and The plurality of second-level interconnect terminals and the transfer terminals are respectively engaged while pressing the at least one second-level device and the first-level element toward each other.

In some embodiments, the second-level interconnect bumps and/or the transfer bumps are made of solder, and the plurality of second-level interconnect terminals and the transfer terminals are connected in S380 Solder to form interconnect pads. In some embodiments, the second-level interconnect bumps and/or the via bumps do not include solder, and the plurality of second-level interconnect terminals and the via terminals are performed in S380. Thermal Compression Bonding (TCB).

As an exemplary embodiment, as shown in FIG. 4J , second-level alignment solder bumps 464 and second-level alignment pads 454 are soldered to form second-level alignment pads 466 . During the soldering process, the molten second-level alignment solder bumps 464 wet the second-level alignment pads 454 and self-align with the second-level alignment pads 454 based on their own minimum surface energy principle alignment, so that the second-level device 460 is driven to achieve precise alignment on the first-level semiconductor element 450 . After soldering is completed, the active surface of the second-level device 460 is separated from the first-level semiconductor element 450 to form a space. Then, as shown in FIG. 4K, the second stage device 460 and the first stage semiconductor element 450 are pressed toward each other while heating. At this point, the second-level alignment pads 466 are again at least partially melted and further squashed, and the second-level interconnect bumps 462 (also in an at least partially melted state) then come into contact with the transfer pads 452 and Second level interconnect pads 468 are formed.

In some embodiments, the method further includes: using the weight of the second-level device to further improve the self-alignment accuracy of the second-level alignment solder joint in a state where the whole is turned over and at least partially melted. As an example, the aforementioned S331 or S330' can be selectively referred to.

S390: Release the pressing.

In some embodiments, after the second-level alignment pads and/or the interconnect junctions have at least partially solidified to secure the at least one second-level device to the first-level component, releasing all the press as described above. It should be understood that the time required for the second level alignment pads and/or the interconnect junction to at least partially solidify to secure the at least one second level device to the first level element is based on theory and Predictable from experience or measurable by prior experimentation, and optional release of compressions after this time has elapsed.

In some embodiments, when the carrier board has no interconnect structure or product function, the packaging method further comprises: removing the carrier board. As an example, in any one of steps S340 to S390 or between any two steps, the carrier plate is removed.

In some embodiments, the carrier is removed by stripping, etching, ablation, grinding, or the like, processes known in the art. As an example, when the lift-off process is used, the soldering between the carrier board and the first-level device (ie, the first-level alignment solder joints) may be desoldered, so as to facilitate the removal of the plastic seal from the plastic package. Peel off the carrier.

In some embodiments, some or all of the first level alignment pads are also removed upon removal of the carrier board or after removal of the carrier board. As an example, some or all of the first-level alignment pads may be removed by processes known in the art, such as desoldering, etching, ablation, or grinding. In some embodiments, some or all of the first-level alignment pads are retained as part of the final semiconductor component (ie, final package) for electrical connections (eg, power and ground), heat dissipation, mechanical structures, and the like.

In some embodiments, after removing the carrier plate, the method further includes: thinning (eg, grinding, etching or ablating, etc.) on the surface of the plastic package from which the carrier plate has been removed. As an example, thinning to remove a portion of the first-level second surface side of the mold body of the first-level device (including a portion of the remaining first-level alignment pads), or thinning to the first level The first-level second surface of the first-level device, or the thinned portion includes a portion of the first-level second surface side of the first-level device. It should be understood that the thinning process also removes the first-level alignment solder joints remaining after the carrier plate is removed. Thereby, the thickness of the final semiconductor element can be further reduced.

As an exemplary embodiment, as shown in FIG. 4L, the heating is released until the second level alignment pads 466 and the second level interconnect pads 468 are substantially solidified, and then the pressing is released. Then, the carrier 420 (and the first-level alignment pads) are removed by desoldering the first-level alignment pads 416 , thereby forming the semiconductor element 400 .

It will be appreciated that due to the height of the second level alignment pads and/or the interconnect junctions themselves, some space is formed between the second level device and the first level element. In some embodiments, the method further includes: underfilling the space formed between the second-level device and the first-level element.

In some embodiments, passive devices are packaged together with the at least first-level devices into first-level components in substantially the same manner as in the above-described embodiments.

In some embodiments, after S390, the method further includes: performing cutting.

It should be understood that the dicing process may be performed to produce individual semiconductor elements, or not performed, depending on the package specifications.

Based on similar inventive concepts, the present application also provides a packaging method according to another embodiment. Compared with the aforementioned packaging method according to the embodiment shown in FIG. 3 , the main difference is: The interconnection pads do not fan out (that is, do not form an interconnection layer), but directly connect the first-level interconnection pads of the first-level devices and the second-level interconnection terminals of the second-level devices (only interconnect bumps). dots, or a combination of interconnect bumps and second-level first-aligned solder joints). Therefore, in order to avoid unnecessarily confusing the inventive concept, in the following description of the packaging method according to this embodiment, descriptions about parts that are basically the same or have no substantial changes compared with the embodiment shown in FIG. 3 will be omitted, In this regard, reference is made to the corresponding descriptions given above for the embodiment shown in FIG. 3 .

FIG. 5 shows a flowchart of a packaging method according to another embodiment of the present application. As shown in Figure 5, the packaging method includes the following steps:

S410: Provide at least one first-level device, at least one second-level device, a carrier board, and a clamping board, wherein the first-level device has a plurality of first-level interconnect pads formed on the first-level first surface and is A plurality of first-level first-level alignment welds are formed on a first-level second surface opposite to the first-level first surface; the at least one second-level device is formed on the second-level first surface a plurality of second level interconnect bumps and a plurality of second level first alignment pads, wherein the plurality of second level interconnect bumps and at least a portion of the plurality of first level interconnect pads corresponding respectively; a plurality of first-level second-level alignment welding portions corresponding to the first-level first-level first-level alignment welding portions are formed on the carrier plate; At least one of them has an opening for injection molding formed therethrough.

It should be understood that in order to directly perform at least a portion of the plurality of first-level interconnect pads of the at least one first-level device with the plurality of second-level interconnect bumps of the at least one second-level device interconnection between points, at least a portion of the plurality of first-level interconnection pads needing to be interconnected with the plurality of second-level interconnection pads in terms of volume, size, geometry, composition, distribution, location and number, etc. The bumps correspond to each other to enable at least a portion of the plurality of first-level interconnect pads when the at least one second-level device is precisely aligned to a corresponding target location on the first-level element Accurately centered with the plurality of second-level interconnect bumps for stack interconnection between the at least one second-level device and the first-level element described later.

In some embodiments, the plurality of second-level interconnect bumps correspond to the plurality of first-level interconnect pads, respectively. In an alternative embodiment, the plurality of second-level interconnect bumps and the plurality of second-level first-aligned bond pads together serve as the second-level first of the at least one second-level device A plurality of second-level interconnection terminals on the surface respectively correspond to the plurality of first-level interconnection pads.

As an exemplary embodiment, as shown in Figure 6A, two first-level semiconductor devices 510, 510' The two first-level semiconductor devices 510, 510' are not identical, eg, in size and/or function. It can be understood that although only the first-level semiconductor device 510 is shown with reference numerals of relevant parts thereof in FIG. 6A for the purpose of convenience of explanation and the following description is combined with it, the description is also applicable to the first-level semiconductor device 510 ' corresponding analogous part. Each first-level semiconductor device 510 , 510 ′ is formed with a plurality of first-level interconnection pads 512 distributed on the active surface 511 , and a plurality of first-level alignment solder bumps 514 are formed on the passive surface 513 . The second-level semiconductor device 560 is formed with a plurality of second-level interconnection bumps 562 and a plurality of second-level first-aligned solder bumps 564 distributed on the active surface 561 to serve as connection with the first-level interconnection pads 512 Corresponding interconnect terminals, and the second-level semiconductor device 560 is further provided with TSVs 565 electrically connected to the second-level first-aligned solder bumps 564 and part of the second-level interconnect bumps 562, respectively. A plurality of corresponding first-levels are formed on a surface of the carrier board 520 in the same arrangement (or relative positional relationship) as the first-level alignment solder bumps 514 on the first-level semiconductor devices 510 and 510 ′. Align pads 524 . Openings 538 for injection molding are formed through the clamping plate 530 in regions between the target positions corresponding to the first-stage semiconductor devices 510 and 510'. Alternatively, in addition to the first-level semiconductor device and the second-level semiconductor device, passive devices may also be provided in a similar structure. For example, the reference numeral 510' as shown in FIG. 6A may be replaced with passive devices.

S420 to S440: are basically the same as the aforementioned S320 to S340, respectively.

S450: Remove the splint to expose the first-level first surface, thereby forming a first-level element.

As an exemplary embodiment, as shown in FIG. 6B , by removing the clamping plate 530 , the overmolding body 540 exposes the active surface 511 of the first-level semiconductor devices 510 , 510 ′, ie, exposes the first-level interconnect pads 512 , thereby exposing the first-level interconnect pads 512 . A first-level semiconductor element 550 is formed.

S460 : Place the at least one second-level device on the first-level component, so that the plurality of second-level first-aligned welding parts and the plurality of second-level first-level components on the first-level component Two alignment welds are substantially aligned, wherein the plurality of second level second alignment welds are pre-formed on a side of the first level element that exposes the first level first surface and are aligned with the first level The plurality of second-level first alignment welding parts correspond respectively.

In some embodiments, when the plurality of second-level interconnection bumps correspond to the plurality of first-level interconnection pads respectively, between S450 and S460 further includes: in the first-level element The plurality of second-level second alignment welds are formed on the side of the exposed first-level first surface. As an alternative embodiment, the plurality of second-level interconnection bumps correspond to the plurality of first-level interconnection pads, respectively, and the second-level first-level alignment soldering portion has alignment solder bumps. In the S410, the first-level device is further formed with the plurality of second-level second alignment soldering portions having the shape of alignment pads on the first-level first surface.

In some embodiments, when the plurality of second-level interconnect bumps and the plurality of second-level first-aligned pads are taken together as the second-level first of the at least one second-level device When the plurality of second-level interconnect terminals on the surface corresponding to the plurality of first-level interconnect pads, respectively, and the plurality of second-level first-level alignment soldering portions have the form of alignment solder bumps , in S460, a part of the plurality of first-level interconnection pads corresponding to the plurality of second-level first-alignment welding portions respectively is used as the plurality of second-level second-level alignment welding portions. As an alternative embodiment, when the plurality of second-level interconnect bumps and the plurality of second-level first-aligned pads together act as the second-level first of the at least one second-level device When there are a plurality of second-level interconnection terminals on the surface corresponding to the plurality of first-level interconnection pads respectively, between S450 and S460 further comprising: among the plurality of first-level interconnection pads The plurality of second-level second-level alignment-welding portions in the form of alignment-welding bumps are respectively formed on a portion corresponding to each of the plurality of second-level first-level alignment-welding portions.

It should be understood that in a direction perpendicular to the second-level first surface of the second-level device (or the surface of the first-level element exposed to the side of the exposed first-level first surface), the The sum of the heights of the first-level interconnect pads and the second-level interconnect bumps is substantially smaller than the sum of the heights of the second-level first-level alignment pads and the second-level second-level alignment pads , so that the first-level interconnect pads and the second-level interconnect bumps form a second-level subsequent to the second-level first-level alignment bonding portion and the second-level second-level alignment bonding portion Also spaced apart from each other after aligning the solder joints.

As an exemplary embodiment, as shown in FIG. 6C , a second-level device 560 is placed on the first-level semiconductor element 550 such that the second-level alignment solder bumps 564 are aligned with the corresponding first-level interconnect pads 512 touch. At this point, the second-level alignment solder bumps 564 are misaligned with the corresponding first-level interconnect pads 512 .

S470: Form a plurality of second-level alignment solder joints by welding the plurality of second-level first-level alignment welding portions and the plurality of second-level second-level alignment solder portions, so that the at least one A second-level device is precisely aligned to the first-level component, and the at least one second-level device and the first-level device are fused together in a state where the plurality of second-level alignment pads are at least partially melted. The plurality of second-level interconnect bumps are respectively bonded to the corresponding first-level interconnect pads while the level elements are pressed toward each other to form a plurality of interconnect bonding points.

In some embodiments, in S470, when the at least one second-level device is in precise alignment with the first-level component and the plurality of second-level alignment pads are still in an at least partially molten state , respectively bonding the plurality of second-level interconnect bumps and corresponding first-level interconnect pads while pressing the at least one second-level device and the first-level element toward each other. In other embodiments, in S470, after the at least one second-level device is precisely aligned and secured to the first-level component, the second-level alignment pads are again at least partially melted, and The plurality of second-level interconnect bumps and corresponding first-level interconnect pads are respectively bonded while pressing the at least one second-level device and the first-level element toward each other.

In some embodiments, the second-level interconnect bumps are made of solder, and in S470 the plurality of second-level interconnect bumps and corresponding first-level interconnect pads are respectively soldered to form interconnect solder joints. In some embodiments, the second-level interconnect bumps do not include solder, and in S470 thermocompression bonding is performed on the plurality of second-level interconnect bumps and the corresponding first-level interconnect pads .

As an exemplary embodiment, as shown in FIG. 6D , second-level alignment solder bumps 564 and corresponding first-level interconnect pads 512 are soldered to form second-level alignment pads 566 . During the soldering process, the second-level alignment solder bumps 564 in the molten state will wet the corresponding first-level interconnect pads 512 and interact with the corresponding first-level interconnect pads based on the principle of its own minimum surface energy. 512 performs self-alignment so that the second-level device 560 is driven to achieve precise alignment on the first-level semiconductor element 550 . After soldering is completed, the active surface of the second-level device 560 is separated from the first-level semiconductor element 550 to form a space. Then, as shown in FIG. 6E, the second-level device 560 and the first-level semiconductor element 550 are pressed toward each other while heating. At this point, the second-level alignment pads 566 are again at least partially melted and further squashed, and the second-level interconnect bumps 562 (also in an at least partially melted state) are then joined with the first-level interconnect pads 512 Contacts are made and second level interconnect pads 568 are formed.

S480: It is basically the same as the aforementioned S390.

Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the present application. In this way, if these changes and modifications of the present application fall within the scope of the claims of the present application and their equivalent technical solutions, the description content of the present application is also intended to include these changes and modifications.

410, 410': first-level semiconductor devices 411: Active Surface 412: first level interconnect pad 413: Passive Surface 414: First level alignment solder bumps 416: First-level alignment solder joints 420: carrier board 424: First-level alignment pads 428: Opening 430: splint 450: First-Class Semiconductor Components 452: transfer pad 454: Second-level alignment pads 455: Dielectric Layer 456: External interconnect terminal 458: RDL trace 460: Second Stage Semiconductor Devices 461: Active Surface 462: Second level interconnect bump 464: Second level first alignment solder bumps 466: Second-level alignment solder joints 468: Second level interconnect solder joints 510, 510': first-level semiconductor devices 511: Active Surface 512: First level interconnect pads 513: Passive Surface 514: First level alignment solder bumps 520: carrier board 524: First-level alignment pads 530: Splint 538: Opening 540: plastic body 550: First-Class Semiconductor Components 560: Second Stage Semiconductor Devices 561: Active Surface 562: Second level interconnect bump 564: Second-level first-aligned solder bumps 565:TSV 566: Second-level alignment solder joints 568: Second level interconnect solder joints

[ FIG. 1 ] A schematic diagram illustrating the phenomenon of wafer drift and wafer rotation caused by inaccurate placement or extrusion by mold flow in a chip-first fan-out type packaging process according to the related art . [Fig. 2] A schematic diagram showing the state of mismatch (or misalignment) of the under bump metal (UBM) and redistribution layer (RDL) trace positions formed after wafer drift and rotation as shown in Fig. 1 occurs. [ Fig. 3 ] A flowchart showing a packaging method according to an embodiment of the present application. 4A to 4L] show cross-sectional views for schematically explaining a packaging method according to an exemplary embodiment of the present application. [ FIG. 5 ] A flowchart illustrating a packaging method according to another embodiment of the present application. [ FIGS. 6A to 6E ] show cross-sectional views for schematically explaining a packaging method according to an exemplary embodiment of the present application.

S310: Provide at least one first-level device, at least one second-level device, a carrier board, and a clamping board, wherein the first-level device is formed with a plurality of first-level interconnect pads on the first-level first surface and is A plurality of first-level first alignment welding parts are formed on a first-level second surface opposite to the first-level first surface, and the at least one second-level device is formed with a plurality of first-level first surfaces. a plurality of second-level interconnection terminals and a plurality of second-level first-level alignment soldering portions, and a plurality of first-level first-level alignment soldering portions corresponding to the plurality of first-level first-level alignment soldering portions are formed on the carrier. The second alignment welding part, at least one of the carrier plate and the clamping plate is formed with an opening for injection molding therethrough

S320: Place the at least one first-level device on the carrier board, so that the plurality of first-level first-level alignment soldering parts and the plurality of first-level second-level alignment soldering parts are substantially aligned

S330: Form a plurality of first-level alignment solder joints by welding the plurality of first-level first-level alignment welding portions and the plurality of first-level second-level alignment soldering portions, so that the at least one The first stage devices are precisely aligned and secured to the carrier board

S340: Perform injection molding through the opening to form a plastic package covering the at least one first-level device between the carrier board and the splint pre-attached on the first-level first surface

S350: Remove the splint to expose the first-level first surface

S360: Sequentially forming an interconnection layer and a plurality of transfer terminals corresponding to the plurality of second-level interconnect terminals respectively on the side of the plastic package that exposes the first-level first surface, so that the At least a part of the plurality of first-level interconnection pads are respectively electrically connected to the plurality of via terminals through the interconnection layer, and the interconnection layer is also formed with the plurality of second-level first-level interconnection pads. A plurality of second-level second-level alignment welding portions corresponding to one alignment welding portion respectively, thereby forming a first-level element

S370: Placing the at least one second-level device on the first-level component, so that the plurality of second-level first-aligned solder portions are substantially the same as the plurality of second-level second-level alignment solder portions alignment

S380: Form a plurality of second-level alignment solder joints by welding the plurality of second-level first-level alignment welding portions and the plurality of second-level second-level alignment solder portions, so that the at least one A second-level device is precisely aligned to the first-level component, and the at least one second-level device and the first-level device are fused together in a state where the plurality of second-level alignment pads are at least partially melted. respectively engaging the plurality of second-level interconnect terminals and the plurality of transition terminals while pressing the stage elements toward each other to form a plurality of interconnect junctions

S390: Release the pressing

Claims (31)

A semiconductor packaging method, comprising: S310: Provide at least one first-level device, at least one second-level device, a carrier board, and a clamping board, wherein the first-level device is formed with a plurality of first-level devices on a first-level first surface level interconnect pads and a plurality of first level first alignment pads are formed on a first level second surface opposite to the first level first surface; the at least one second level device is on a second level A plurality of second-level interconnect terminals and a plurality of second-level first-aligned welding parts are formed on the first surface of the first-level; the carrier is formed with a plurality of first-level first-aligned welding parts respectively a plurality of corresponding first-level second alignment welding parts; and an opening for injection molding is formed through at least one of the carrier plate and the clamping plate; S320: Place the at least one first-level device on the carrier board, so that the plurality of first-level first-level alignment soldering parts are substantially aligned with the plurality of first-level second-level alignment soldering parts ; S330: Form a plurality of first-level alignment solder joints by welding the plurality of first-level first-level alignment welding portions and the plurality of first-level second-level alignment soldering portions, so that the at least one The first stage device is precisely aligned and secured to the carrier; S340: performing injection molding through the opening to form a plastic package covering the at least one first-level device between the carrier board and the splint pre-attached on the first-level first surface; S350: Remove the splint to expose the first-level first surface; S360: Sequentially form an interconnection layer and a plurality of transfer terminals corresponding to the plurality of second-level interconnect terminals on the side of the plastic package that is exposed to the first-level first surface, so that the At least a part of the plurality of first-level interconnection pads are respectively electrically connected to the plurality of via terminals through the interconnection layer, and the interconnection layer is also formed with the plurality of second-level first-level interconnection pads. A plurality of second-level second-level alignment welding portions corresponding to an alignment welding portion respectively, thereby forming a first-level element; S370: Place the at least one second-level device on the first-level component, so that the plurality of second-level first-aligned solders are substantially the same as the plurality of second-level second-aligned solders alignment; S380: Form a plurality of second-level alignment solder joints by welding the plurality of second-level first-level alignment welding portions and the plurality of second-level second-level alignment solder portions, so that the at least one A second-level device is precisely aligned to the first-level component, and the at least one second-level device and the first-level device are fused together in a state where the plurality of second-level alignment pads are at least partially melted. respectively engaging the plurality of second-level interconnect terminals and the plurality of transition terminals while pressing the stage elements toward each other to form a plurality of interconnect junctions; and S390: Release the pressing. The semiconductor packaging method of claim 1, wherein at least one of the at least one first-level device and the at least one second-level device includes at least one of a semiconductor device and an interconnect board, the The interconnect board is an interposer board or substrate. The semiconductor packaging method of claim 1, wherein at least one of the at least one first-level device and the at least one second-level device is further provided with at least one through electrode. The semiconductor packaging method of claim 1, wherein any one of the plurality of first-level first alignment solders and the plurality of first-level second alignment solders has an alignment solder bump point morphology and the other has the morphology of alignment pads corresponding to the alignment solder bumps, or the plurality of first-level first alignment bonds and the plurality of first-level second pairs each of the quasi-welds has a morphology of an align-bond bump; and any one of the plurality of second-level first-alignment welds and the plurality of second-level second-alignment welds has an alignment weld the form of bumps and the other has the form of alignment pads corresponding to the alignment solder bumps, or the plurality of second-level first alignment pads and the plurality of second-level second All of the alignment welding portions have the form of alignment welding bumps. The semiconductor packaging method of claim 1, wherein any one of the plurality of second-level interconnect terminals and the plurality of via terminals has an interconnect bump form and the other has an interconnect pad In the form of a pad, or the plurality of second-level interconnect terminals and the plurality of via terminals each have the form of interconnect bumps. The semiconductor packaging method of claim 1, wherein, in a direction perpendicular to the second-level first surface of the at least one second-level device, the second-level interconnect terminals and the vias The sum of the heights of the terminals is smaller than the sum of the heights of the second-level first alignment welding part and the second-level second alignment welding part, so that the second-level interconnection terminal and the transfer terminal are in the spaced apart from each other before the pressing in the S380. The semiconductor packaging method according to claim 1, wherein in the S360, a plurality of external interconnection terminals are further formed on the interconnection layer, so that a part of the plurality of first-level interconnection pads pass through The interconnect layer is electrically connected to the plurality of external interconnect terminals. The semiconductor packaging method of claim 7, wherein the plurality of external interconnect terminals are spaced apart from the second-level second-level alignment soldering portion, such that the plurality of second-level devices in the S380 After being precisely aligned to the first level element, it is not covered by the vertical projection of the plurality of second level devices on the interconnect layer. The semiconductor packaging method according to claim 1, wherein, in the S380, precise alignment is formed between the at least one second-level device and the first-level element, and the plurality of second-level alignment welds are formed. Pressing the at least one second-level device and the first-level element toward each other while the dots are still in an at least partially molten state, pressing the plurality of second-level interconnect terminals and the plurality of interposers The terminals are respectively engaged. The semiconductor packaging method of claim 1, wherein, in the S380, after the at least one second-level device is precisely aligned and fixed to the first-level element, the second-level alignment is made The solder joints are again at least partially melted and the plurality of second-level interconnect terminals and the plurality of transfer terminals are respectively pressed while the at least one second-level device and the first-level element are pressed toward each other engage. The semiconductor packaging method according to claim 5, wherein the interconnection bumps are made of solder, and in the S380, the plurality of second-level interconnection terminals and the plurality of transfer terminals are respectively joined The forming of the plurality of interconnect junctions includes soldering the plurality of second level interconnect terminals and the plurality of transfer terminals to form interconnect lands. The semiconductor packaging method of claim 5, wherein the interconnect bumps do not contain solder and the step of S380 is to bond the plurality of second-level interconnect terminals and the plurality of transfer terminals respectively to Forming the plurality of interconnect junctions includes thermocompression bonding the plurality of second level interconnect terminals and the transfer terminals. The semiconductor packaging method of claim 1, wherein the plurality of second-level alignment pads and/or the plurality of interconnect junctions are at least partially solidified to secure the at least one second-level device After reaching the first-level element, the pressing is released. A semiconductor packaging method, comprising: S410: Provide at least one first-level device, at least one second-level device, a carrier board, and a clamping board, wherein the first-level device has a plurality of first-level interconnect pads formed on the first-level first surface and is A plurality of first-level first-level alignment welds are formed on a first-level second surface opposite to the first-level first surface; the at least one second-level device is formed on the second-level first surface a plurality of second level interconnect bumps and a plurality of second level first alignment pads, wherein the plurality of second level interconnect bumps and at least a portion of the plurality of first level interconnect pads corresponding respectively; a plurality of first-level second-level alignment welding portions corresponding to the first-level first-level first-level alignment welding portions are formed on the carrier plate; At least one is formed with an opening for injection molding therethrough; S420: Place the at least one first-level device on the carrier board, so that the plurality of first-level first-level alignment soldering parts are substantially aligned with the plurality of first-level second-level alignment soldering parts ; S430: Form a plurality of first-level alignment solder joints by welding the plurality of first-level first-level alignment welding parts and the plurality of first-level second-level alignment welding parts, so that the at least one The first stage device is precisely aligned and secured to the carrier; S440: performing injection molding through the opening to form a plastic package covering the at least one first-level device between the carrier board and the splint pre-attached on the first-level first surface; S450: removing the splint to expose the first-level first surface, thereby forming a first-level element; S460 : Place the at least one second-level device on the first-level component, so that the plurality of second-level first-aligned welding parts and the plurality of second-level first-level components on the first-level component Two alignment welds are substantially aligned, wherein the plurality of second level second alignment welds are pre-formed on a side of the first level element that exposes the first level first surface and are aligned with the first level The plurality of second-level first alignment welding parts correspond respectively; S470: Form a plurality of second-level alignment solder joints by welding the plurality of second-level first-level alignment welding portions and the plurality of second-level second-level alignment solder portions, so that the at least one A second-level device is precisely aligned to the first-level component, and the at least one second-level device and the first-level device are fused together in a state where the plurality of second-level alignment pads are at least partially melted. separately bonding the plurality of second-level interconnect bumps and corresponding first-level interconnect pads while pressing the level elements toward each other to form a plurality of interconnect bonding points; and S480: Release the pressing. The semiconductor packaging method of claim 14, wherein any one of the plurality of first-level first alignment solders and the plurality of first-level second alignment solders has an alignment solder bump point morphology and the other has the morphology of alignment pads corresponding to the alignment solder bumps, or the plurality of first-level first alignment bonds and the plurality of first-level second pairs each of the quasi-welds has a morphology of an align-bond bump; and any one of the plurality of second-level first-alignment welds and the plurality of second-level second-alignment welds has an alignment weld the form of bumps and the other has the form of alignment pads corresponding to the alignment solder bumps, or the plurality of second-level first alignment pads and the plurality of second-level second All of the alignment welding portions have the form of alignment welding bumps. The semiconductor packaging method of claim 14, wherein the plurality of second-level interconnection bumps correspond to the plurality of first-level interconnection pads, respectively. The semiconductor packaging method of claim 14, wherein the plurality of second-level interconnect bumps and the plurality of second-level first-aligned solders together serve as all of the at least one second-level device. A plurality of second-level interconnection terminals on the second-level first surface are respectively corresponding to the plurality of first-level interconnection pads. The semiconductor packaging method of claim 16, wherein between the S450 and the S460, further comprising: forming the plurality of first-level elements on a side of the first-level element that exposes the first-level first surface A second level of second alignment welds. The semiconductor packaging method of claim 16, wherein the second-level first-level alignment soldering portion has a shape of an alignment soldering bump, and in the S410, the first-level device is in the first level The plurality of second-level second alignment pads in the form of alignment pads are further formed on the first surface of the level. The semiconductor packaging method of claim 17, wherein the second-level first-level alignment soldering portion has the form of an alignment soldering bump, and the plurality of first-level interconnections are soldered in the S460 A portion of the disk corresponding to the plurality of second-level first alignment welding portions respectively serves as the plurality of second-level second alignment welding portions. The semiconductor packaging method according to claim 17, wherein between the S450 and the S460, further comprising: connecting the plurality of first-level interconnect pads with the plurality of second-level first pairs The plurality of second-level second alignment welding portions having the form of alignment welding bumps are respectively formed on corresponding portions of the pseudo welding portions. The semiconductor packaging method of claim 14, wherein at least one of the at least one first-level device and the at least one second-level device includes at least one of a semiconductor device and an interconnection board, the interconnection The connecting board is an adapter board or a base plate. The semiconductor packaging method of claim 14, wherein at least one of the at least one first-level device and the at least one second-level device is further provided with at least one through electrode. The semiconductor packaging method of claim 14, wherein, in a direction perpendicular to the second-level first surface of the at least one second-level device, the first-level interconnect pads and the first-level The sum of the heights of the second-level interconnection bumps is less than the sum of the heights of the second-level first alignment soldering portion and the second-level second alignment soldering portion, so that the first-level interconnection pads and The second level interconnect bumps are spaced apart from each other prior to the pressing in the S470. The semiconductor packaging method of claim 14, wherein, in the S470, precise alignment is formed between the at least one second-level device and the first-level element and the plurality of second-level alignment welds are formed while the dots are still in an at least partially molten state, interconnecting the plurality of second level bumps and the corresponding first level while pressing the at least one second level device and the first level element toward each other The interconnection pads are respectively bonded. The semiconductor packaging method of claim 14, wherein, in the S470, after the at least one second-level device is precisely aligned and fixed to the first-level element, the second-level alignment is performed The solder joints are again at least partially melted and the plurality of second-level interconnect bumps and corresponding first-level interconnects are pressed while the at least one second-level device and the first-level element are pressed toward each other The pads are individually bonded. The semiconductor packaging method of claim 14, wherein the second-level interconnect bumps are made of solder and in S470 the plurality of second-level interconnect bumps and the corresponding first-level interconnect bumps are connected Respectively bonding the interconnection pads to form the plurality of interconnection bonding points includes: respectively bonding the plurality of second-level interconnection bumps and the corresponding first-level interconnection pads to form the interconnection bonding points. The semiconductor packaging method of claim 14, wherein the second-level interconnection bumps do not contain solder and the step of S470 interconnects the plurality of second-level interconnection bumps with the corresponding first-level interconnections The bonding of the connection pads respectively to form the plurality of interconnection bonding points includes: performing thermocompression bonding on the plurality of second-level interconnection bumps and the corresponding first-level interconnection pads. The semiconductor packaging method of claim 14, wherein the plurality of second-level alignment pads and/or the plurality of interconnect junctions are at least partially solidified to secure the at least one second-level device After reaching the first-level element, the pressing is released. A semiconductor element packaged by the semiconductor packaging method according to any one of claims 1 to 29. An electronic device comprising the semiconductor element as claimed in claim 30.

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