CN111430322A - System-level fan-out packaging structure and packaging method - Google Patents

System-level fan-out packaging structure and packaging method Download PDF

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Publication number
CN111430322A
CN111430322A CN202010148148.5A CN202010148148A CN111430322A CN 111430322 A CN111430322 A CN 111430322A CN 202010148148 A CN202010148148 A CN 202010148148A CN 111430322 A CN111430322 A CN 111430322A
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layer
chip
discrete device
dielectric layer
fan
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崔成强
杨冠南
徐广东
张昱
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Guangdong University of Technology
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Guangdong University of Technology
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
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    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
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Abstract

The invention relates to a system-level fan-out packaging structure, which comprises a chip, a discrete device, a fixed layer, a plastic packaging layer, a rewiring layer, a dielectric layer and a solder ball, wherein the chip and the discrete device are provided with bumps; the chip and the discrete device are both connected with the rewiring layer through respective salient points; the dielectric layer comprises a first dielectric layer and a second dielectric layer, the first dielectric layer is arranged on the rewiring layer and is positioned at one side close to the chip and the discrete device, and the second dielectric layer is arranged on the rewiring layer and is positioned at one side far away from the first dielectric layer; the solder balls are connected with the rewiring layer and are positioned on one side far away from the first dielectric layer. The system-level fan-out type packaging structure reduces the drift of the chip and the discrete device generated in the injection molding and curing processes, facilitates the positioning and implementation of the subsequent re-wiring process, and improves the yield of the system-level packaging.

Description

System-level fan-out packaging structure and packaging method
Technical Field
The invention relates to the technical field of packaging structures, in particular to a system-level fan-out type packaging structure and a packaging method.
Background
With the trend of high performance and integration of electronic products, chips are developed in the directions of higher density, higher speed, lower cost and the like, and the size reduction following moore's law can not meet the requirements of high performance, low power consumption, small size and low cost independently any more. The System in Package (System in Package) can provide more and stronger System functions, has good compatibility of various processes, strong flexibility and adaptability, low cost and easy block test, has shorter interconnecting leads among bare chips in the Package, can effectively reduce the time delay and crosstalk of interconnecting lines of the System, reduces capacitive reactance, enables devices to work at higher frequency, improves the transmission bandwidth and data rate of a System bus, and simultaneously reduces the power consumption of the System due to closer chip spacing, and the like, and becomes an important development trend.
In the process of multi-size chip plastic packaging, due to the difference of thermal expansion coefficients (coefficient of thermal expansion) of a carrier plate (mold plate), a plastic carrier tape (mold tape) and a molding compound (mold compound), a chip shift (die shift) is caused due to the influence of the difference of thermodynamic deformation. In addition, since the plastic package material in a molten state needs to be injected by external force pressurization, the chip may be affected by fluid force and drift during the filling process of the plastic package material. The existing method reduces the chip drift by adjusting different material parameters such as thermal expansion Coefficients (CTEs) of a carrier plate and an injection molding material and adjusting process parameters such as injection molding time, pressure, curing temperature and curing time of a plastic packaging material, but the effect has certain limitation; in addition, by changing the matching relationship between the bottom surface of the chip and the plane of the carrier tape, a rougher contact surface is arranged or a concave-convex matching surface is designed to fix the position of the chip, so that the chip drift is reduced.
Disclosure of Invention
In order to solve the problem that chips and discrete devices can drift in the process of plastic packaging of chips with multiple sizes, the invention provides a system-level fan-out type packaging structure and a packaging method, which reduce the drift of the chips and the discrete devices generated in the injection molding and curing processes, facilitate the positioning and implementation of the subsequent rewiring process and improve the yield of system-level packaging.
In order to solve the technical problems, the invention provides the following two technical schemes:
the first technical scheme is as follows:
a system-level fan-out packaging structure comprises a chip, a discrete device, a fixed layer, a plastic packaging layer, a rewiring layer, a dielectric layer and solder balls, wherein the chip and the discrete device are provided with salient points; the salient points of the chip and the discrete device are arranged on the same side, and the chip and the discrete device are connected with the rewiring layer through the respective salient points; the dielectric layer comprises a first dielectric layer and a second dielectric layer, the first dielectric layer is arranged on the rewiring layer and is positioned at one side close to the chip and the discrete device, and the second dielectric layer is arranged on the rewiring layer and is positioned at one side far away from the first dielectric layer; the solder balls are connected with the rewiring layer and are positioned on one side far away from the first dielectric layer; the plastic packaging layer is wrapped on the chip and the discrete device; the fixing layers are respectively arranged between the chip and the plastic packaging layer and between the discrete device and the plastic packaging layer.
In the invention, the fixing layer is adopted to realize the fixation of the chip and the discrete device in the plastic packaging process, thereby solving the drifting problem of the chip with a tiny size in the injection molding process and being also suitable for solving the drifting problem of the system-level packaging of the chips and the discrete devices with different sizes, functions and shapes.
Furthermore, the fixed layer is made of solid crystal glue, the solid crystal glue has high fluidity before solidification and has better wettability with the chip, the discrete device and the lower temporary bonding layer, gaps among the chip, the discrete device and the lower temporary bonding layer can be completely filled, and the solid crystal glue has high bonding strength after solidification and is enough to prevent the chip from drifting.
A system-level fan-out packaging method based on the system-level fan-out packaging structure comprises the following steps:
s1: coating a layer of die attach adhesive on the local position of the carrier plate pasted with the temporary bonding adhesive, namely the placement positions of the subsequent chip and the discrete device;
s2: mounting the chip and the discrete device at corresponding positions on the die attach adhesive in a direction that the bumps face downwards, and heating and fixing;
s3: carrying out integral plastic package;
s4: removing the temporary bonding adhesive and the carrier plate, and exposing the salient points of the chip and the discrete device in a mechanical grinding mode;
s5: and covering the first dielectric layer, and exposing the salient points of the chip through patterned etching.
S6: performing seed layer deposition and pattern electroplating to form a rewiring layer communicated with the salient points of the chip, and then etching to remove the seed layer;
s7: and covering the second dielectric layer, and performing patterned etching, ball mounting and cutting to obtain the required packaging body.
Further, in step S2, when the heights of the selected chip and the discrete device are consistent, the chip is mounted in a bump-up manner.
The second technical scheme is as follows:
a system-level fan-out packaging structure comprises a chip, a discrete device, a fixed layer, a plastic packaging layer, a rewiring layer, a dielectric layer and solder balls, wherein the chip and the discrete device are provided with salient points; the salient points of the chip and the discrete device are arranged on the same side, and the chip and the discrete device are connected with the rewiring layer through the respective salient points; the dielectric layer comprises a first dielectric layer and a second dielectric layer, the first dielectric layer is arranged on the rewiring layer and is positioned at one side close to the chip and the discrete device, and the second dielectric layer is arranged on the rewiring layer and is positioned at one side far away from the first dielectric layer; the solder balls are connected with the rewiring layer and are positioned on one side far away from the first dielectric layer; the plastic packaging layer is wrapped on the chip and the discrete device; the fixing layers are respectively arranged between the chip and the plastic packaging layer and between the discrete device and the plastic packaging layer.
In the invention, the fixing layer is adopted to realize the fixation of the chip and the discrete device in the plastic packaging process, thereby solving the drifting problem of the chip with a tiny size in the injection molding process and being also suitable for solving the drifting problem of the system-level packaging of the chips and the discrete devices with different sizes, functions and shapes.
Furthermore, the fixing layer is a positioning solder ball, so that the fixing is more convenient and faster, and the strength after welding is high enough to prevent the chip from drifting.
A system-level fan-out packaging method based on the system-level fan-out packaging structure comprises the following steps:
s1: depositing a metal seed layer at the local position of the carrier plate pasted with the temporary bonding glue, namely the placement position of a subsequent chip and a discrete device, and carrying out pattern electroplating to form a metal layer;
s2: fixing the salient points to corresponding positions of the metal layer through positioning solder balls by a solder ball-reflow soldering process in a direction that the salient points are downward;
s3: carrying out integral plastic package;
s4: removing the temporary bonding adhesive and the carrier plate, removing the metal layer in a mechanical grinding mode, and exposing the positioning welding balls connected with the chip and the salient points of the discrete device; or further grinding, removing the positioning welding balls and exposing the salient points of the chip and the discrete device;
s5: covering the first dielectric layer, and exposing the positioning welding balls through patterning etching;
s6: performing seed layer deposition and pattern electroplating to form a rewiring layer communicated with the positioning solder balls and the chip bumps, and then etching to remove the seed layer;
s7: and covering the second dielectric layer, and performing patterned etching, ball mounting and cutting to obtain the required packaging body.
Compared with the prior art, the invention has the following beneficial effects:
according to the invention, the chip and the discrete device are connected with the positioning solder balls or the crystal fixing glue is locally coated on the temporary bonding glue to position the chip and the discrete device, so that the drifting of the chip and the discrete device generated in the injection molding and curing process is reduced, the positioning and implementation of the subsequent rewiring process are facilitated, and the yield of system-level packaging is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a two-dimensional schematic diagram of a chip and a die attach adhesive of a system-in-fan package structure according to a first embodiment of the invention;
fig. 2 is a three-dimensional schematic diagram of a chip and a die attach adhesive of a system-in-fan package structure according to a first embodiment of the invention;
fig. 3 is a schematic structural diagram of a flip-chip structure of a system-in-fan package structure according to a first embodiment of the invention;
fig. 4 is a schematic diagram illustrating a packaging process of a flip-chip structure of a system-in-fan package structure according to a first embodiment of the invention;
fig. 5 is a schematic structural diagram of a front-side-up structure of a system-in-package structure according to a first embodiment of the invention;
fig. 6 is a schematic diagram illustrating a packaging process of a face-up structure of a system-in-fan package structure according to a first embodiment of the invention;
fig. 7 is a two-dimensional schematic diagram of a chip and solder balls in a system-in-fan package structure according to a second embodiment of the invention;
fig. 8 is a three-dimensional schematic diagram of a chip and solder balls in a system-in-fan package according to a second embodiment of the invention;
fig. 9 is a schematic structural diagram of a flip-chip structure of a system-in-fan package structure according to a second embodiment of the invention;
fig. 10 is a schematic diagram of a packaging process of a flip-chip structure of the system-in-fan package structure according to a second embodiment of the invention.
In the figure: 1. a carrier plate; 2. a temporary bonding glue; 3. die bonding glue; 4. salient points; 5. a chip; 6. a discrete device; 7. a plastic packaging layer; 8. a first dielectric layer; 9. a wiring layer is arranged; 10. a second dielectric layer; 11. soldering tin balls; 12. a seed layer; 13. a metal layer; 14. the solder balls are positioned.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention comprises the following steps:
the first embodiment is as follows:
as shown in fig. 1-6, a system-in-a-fan package structure includes a chip 5 and a discrete device 6 each having a bump 4, a fixing layer, a molding layer 7, a redistribution layer 9, a dielectric layer, and a solder ball 11; the bumps 4 of the chip 5 and the discrete device 6 are arranged on the same side, and the chip 5 and the discrete device 6 are connected with the rewiring layer 9 through the respective bumps 4; the dielectric layers comprise a first dielectric layer 8 and a second dielectric layer 10, the first dielectric layer 8 is arranged on the rewiring layer 9 and positioned at one side close to the chip 5 and the discrete device 6, and the second dielectric layer 10 is arranged on the rewiring layer 9 and positioned at one side far away from the first dielectric layer 8; the solder balls 11 are connected with the rewiring layer 9 and are positioned on one side far away from the first dielectric layer 8; the plastic packaging layer 7 is wrapped on the chip 5 and the discrete device 6; the fixing layers are respectively arranged between the chip 5 and the molding layer 7 and between the discrete device 6 and the molding layer 7.
In the invention, the fixing layer is adopted to realize the fixation of the chip 5 and the discrete device 6 in the plastic packaging process, thereby solving the drifting problem of the chip 5 with small size in the injection molding process and also being suitable for solving the drifting problem of the system-level packaging of the chip 5 and the discrete device 6 with different sizes, functions and shapes.
As shown in fig. 1 to 6, the fixing layer is the die attach adhesive 3, the die attach adhesive 3 has high fluidity before curing and has better wettability with the chip 5, the discrete device 6 and the lower temporary bonding layer, so that gaps among the chip 5, the discrete device 6 and the lower temporary bonding layer can be completely filled, and the die attach adhesive 3 has high bonding strength after curing, which is enough to prevent the chip 5 from drifting.
As shown in fig. 4, a system-level fan-out packaging method based on the system-level fan-out packaging structure includes the following steps:
s1: coating a layer of die attach adhesive 3 on the local position of the carrier plate 1 pasted with the temporary bonding adhesive 2, namely the placement positions of the subsequent chip 5 and the discrete device 6;
s2: installing the chip 5 and the discrete device 6 on the corresponding position on the die attach adhesive 3 in the downward direction of the salient point 4 and heating and fixing;
s3: carrying out integral plastic package;
s4: removing the temporary bonding glue 2 and the carrier plate 1, and exposing the chip 5 and the salient points 4 of the discrete device 6 in a mechanical grinding mode;
s5: the first dielectric layer 8 is covered and the bumps 4 of the chip 5 are exposed by patterned etching.
S6: carrying out seed layer 12 deposition and pattern electroplating to form a rewiring layer 9 communicated with the salient points 4 of the chip 5, and then etching to remove the seed layer 12;
s7: and covering the second dielectric layer 10, and performing patterned etching, ball mounting and cutting to finally obtain the required packaging body.
As shown in fig. 5 to 6, in step S2, when the heights of the selected chip 5 and the discrete device 6 are uniform, the chip 5 is mounted with the bumps 4 facing upward.
Example two:
as shown in fig. 7-10, a system-in-a-fan-out package structure includes a chip 5 and a discrete device 6 each having a bump 4, a fixing layer, a molding layer 7, a redistribution layer 9, a dielectric layer, and a solder ball 11; the bumps 4 of the chip 5 and the discrete device 6 are arranged on the same side, and the chip 5 and the discrete device 6 are connected with the rewiring layer 9 through the respective bumps 4; the dielectric layers comprise a first dielectric layer 8 and a second dielectric layer 10, the first dielectric layer 8 is arranged on the rewiring layer 9 and positioned at one side close to the chip 5 and the discrete device 6, and the second dielectric layer 10 is arranged on the rewiring layer 9 and positioned at one side far away from the first dielectric layer 8; the solder balls 11 are connected with the rewiring layer 9 and are positioned on one side far away from the first dielectric layer 8; the plastic packaging layer 7 is wrapped on the chip 5 and the discrete device 6; the fixing layers are respectively arranged between the chip 5 and the molding layer 7 and between the discrete device 6 and the molding layer 7.
In the invention, the fixing layer is adopted to realize the fixation of the chip 5 and the discrete device 6 in the plastic packaging process, thereby solving the drifting problem of the chip 5 with small size in the injection molding process and also being suitable for solving the drifting problem of the system-level packaging of the chip 5 and the discrete device 6 with different sizes, functions and shapes.
As shown in fig. 7-10, the fixing layer is a positioning solder ball 14, which is more convenient and faster to fix, and the strength after soldering is high enough to prevent the chip 5 from drifting.
As shown in fig. 10, a system-level fan-out packaging method based on the system-level fan-out packaging structure includes the following steps:
s1: depositing a metal seed layer 12 at the local position of the carrier plate 1 pasted with the temporary bonding glue 2, namely the placement position of the subsequent chip 5 and the discrete device 6, and carrying out pattern electroplating to form a metal layer 13;
s2: fixing the chip 5 and the discrete device 6 on the corresponding position of the metal layer 13 by positioning the solder ball 14 through a solder ball-reflow soldering process in the downward direction of the bump 4;
s3: carrying out integral plastic package;
s4: the temporary bonding glue 2 and the carrier plate 1 are removed, the metal layer 13 is removed in a mechanical grinding mode, and the positioning solder balls 14 connected with the chip 5 and the salient points 4 of the discrete device 6 are exposed; or further grinding, removing the positioning solder balls 14 and exposing the bumps 4 of the chip 5 and the discrete device 6;
s5: covering the first dielectric layer 8 and exposing the positioning solder balls 14 through patterned etching;
s6: carrying out seed layer 12 deposition and pattern electroplating to form a rewiring layer 9 communicated with the positioning solder balls 14 and the salient points 4 of the chip 5, and then etching to remove the seed layer 12;
s7: and covering the second dielectric layer 10, and performing patterned etching, ball mounting and cutting to finally obtain the required packaging body.
Example three:
the embodiment is based on the first embodiment and the second embodiment, and specifically includes: the fixing mode of the chip 5 is flexibly selected according to the size and the direction of the chip 5, and the chip 5 and the discrete device 6 which are large and difficult to drift can be directly arranged on the temporary bonding glue 2 layer; the chip 5 and the discrete device 6 which are small in size and easy to drift can be fixed through the die attach adhesive 3; the chip 5 and the discrete device 6 which are small in size and easy to drift, and the bumps 4 with small quantity and large intervals are fixed through the positioning solder balls 14.
Example four:
the present embodiment is based on the second embodiment, except that the solder balls 14 are replaced by nano-copper paste or other semi-solid solder, and in step S2, the nano-copper paste or other semi-solid solder is first coated on the corresponding positions of the bumps 4 or the metal layers 13 of the chip 5 and the discrete device 6, and then the chip 5 and the discrete device 6 are fixed on the corresponding positions of the metal layers 13 by pressure sintering or pressureless sintering.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by the present specification, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims (6)

1. A system-level fan-out packaging structure is characterized by comprising a chip, a discrete device, a fixed layer, a plastic packaging layer, a rewiring layer, a dielectric layer and a solder ball, wherein the chip and the discrete device are provided with bumps; the salient points of the chip and the discrete device are arranged on the same side, and the chip and the discrete device are connected with the rewiring layer through the respective salient points; the dielectric layer comprises a first dielectric layer and a second dielectric layer, the first dielectric layer is arranged on the rewiring layer and is positioned at one side close to the chip and the discrete device, and the second dielectric layer is arranged on the rewiring layer and is positioned at one side far away from the first dielectric layer; the solder balls are connected with the rewiring layer and are positioned on one side far away from the first dielectric layer; the plastic packaging layer is wrapped on the chip and the discrete device; the fixing layers are respectively arranged between the chip and the plastic packaging layer and between the discrete device and the plastic packaging layer.
2. The system-in fan-out package structure of claim 1, wherein the fixing layer is die attach adhesive.
3. The system-in fan-out package structure of claim 1, wherein the mounting layer is a solder ball.
4. A system-in fan-out packaging method based on the system-in fan-out packaging structure of claim 2, comprising the steps of:
s1: coating a layer of die attach adhesive on the local position of the carrier plate pasted with the temporary bonding adhesive, namely the placement positions of the subsequent chip and the discrete device;
s2: mounting the chip and the discrete device at corresponding positions on the die attach adhesive in a direction that the bumps face downwards, and heating and fixing;
s3: carrying out integral plastic package;
s4: removing the temporary bonding adhesive and the carrier plate, and exposing the salient points of the chip and the discrete device in a mechanical grinding mode;
s5: covering the first dielectric layer, and exposing the salient points of the chip through patterning etching;
s6: performing seed layer deposition and pattern electroplating to form a rewiring layer communicated with the salient points of the chip, and then etching to remove the seed layer;
s7: and covering the second dielectric layer, and performing patterned etching, ball mounting and cutting to obtain the required packaging body.
5. The system-in fan-out packaging method of claim 4, wherein in step S2, when the height of the selected chip and the discrete device are consistent, the chip is mounted in a bump-up manner.
6. A system-in fan-out packaging method based on the system-in fan-out packaging structure of claim 3, comprising the steps of:
s1: depositing a metal seed layer at the local position of the carrier plate pasted with the temporary bonding glue, namely the placement position of a subsequent chip and a discrete device, and carrying out pattern electroplating to form a metal layer;
s2: fixing the salient points to corresponding positions of the metal layer through positioning solder balls by a solder ball-reflow soldering process in a direction that the salient points are downward;
s3: carrying out integral plastic package;
s4: removing the temporary bonding adhesive and the carrier plate, removing the metal layer in a mechanical grinding mode, and exposing the positioning welding balls connected with the chip and the salient points of the discrete device; or further grinding, removing the positioning welding balls and exposing the salient points of the chip and the discrete device;
s5: covering the first dielectric layer, and exposing the positioning welding balls through patterning etching;
s6: performing seed layer deposition and pattern electroplating to form a rewiring layer communicated with the positioning solder balls and the chip bumps, and then etching to remove the seed layer;
s7: and covering the second dielectric layer, and performing patterned etching, ball mounting and cutting to obtain the required packaging body.
CN202010148148.5A 2020-03-05 2020-03-05 System-level fan-out packaging structure and packaging method Pending CN111430322A (en)

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Application publication date: 20200717