CN105720018B - There is the integrated fan-out structure of opening in buffer layer - Google Patents

There is the integrated fan-out structure of opening in buffer layer Download PDF

Info

Publication number
CN105720018B
CN105720018B CN201510523238.7A CN201510523238A CN105720018B CN 105720018 B CN105720018 B CN 105720018B CN 201510523238 A CN201510523238 A CN 201510523238A CN 105720018 B CN105720018 B CN 105720018B
Authority
CN
China
Prior art keywords
moulding compound
buffer layer
opening
semiconductor package
packaging part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201510523238.7A
Other languages
Chinese (zh)
Other versions
CN105720018A (en
Inventor
邱梧森
郑礼辉
蔡柏豪
林俊成
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US14/577,450 external-priority patent/US9455211B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN105720018A publication Critical patent/CN105720018A/en
Application granted granted Critical
Publication of CN105720018B publication Critical patent/CN105720018B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836Wafer tapes, e.g. grinding or dicing support tapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48229Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad protruding from the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/0651Wire or wire-like electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1064Electrical connections provided on a side surface of one or more of the containers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1076Shape of the containers
    • H01L2225/1082Shape of the containers for improving alignment between containers, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/143Digital devices
    • H01L2924/1431Logic devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/143Digital devices
    • H01L2924/1432Central processing unit [CPU]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape

Abstract

The present invention provides a kind of packaging part, including moulding compound, the through-hole across moulding compound, the component pipe core that is molded in moulding compound and on moulding compound and contact the buffer layer of moulding compound.Opening reaches through-hole across buffer layer.Buffer layer has in the parallel plane in the interface between moulding compound and buffer layer and around the ripple of open circumferential.The method that other embodiment realizes another packaging part for being bonded to the packaging part and forms packaging part.

Description

There is the integrated fan-out structure of opening in buffer layer
The application is entitled " the Integrated Fan-Out Structure with that September in 2013 is submitted on the 11st The part continuation application of the U.S. Patent Application No. 14/024,311 of Guiding Trenches in Buffer Layer ", Entire contents are hereby expressly incorporated by reference.
Technical field
This patent disclosure relates generally to semiconductor applications, more particularly, to the encapsulation of semiconductor.
Background technology
With the development of semiconductor technology, semiconductor chip/tube core becomes smaller and smaller.Meanwhile it is more multi-functional need by It is integrated into semiconductor element.Therefore, more and more I/O pads are encapsulated into smaller region by semiconductor element needs, Therefore the density of I/O pads was promoted rapidly with the time.As a result, the encapsulation of semiconductor element becomes more difficult, this can be unfavorable Ground influences the yield of encapsulation.
Traditional encapsulation technology can be divided into two classes.In the first kind, the tube core on wafer is at them by cutting Preceding encapsulation.This encapsulation technology has some advantageous features, the increment of such as bigger and lower cost.Furthermore, it is necessary to Less bottom filler or moulding compound.However, this encapsulation technology also has defect.As previously mentioned, the size of tube core becomes It is smaller and smaller, and corresponding encapsulation only can be that fan-in type encapsulates, wherein and the I/O pads of each tube core are limited to direct position Region in the surface of corresponding tube core.Due to the limited area of tube core, the spacing of the quantity of I/O pads due to I/O pads It limits and is restricted.If the spacing of pad reduces, solder bridge joint can occur.Therefore, requiring size of solder ball fixed Under the conditions of, soldered ball must have specific size, this can limit the quantity that can be encapsulated into the soldered ball in die surfaces again.
In another class wrapper, tube core is cut before they are packed and wafer separate, and only encapsulates " known good Good tube core ".The advantage of this encapsulation technology, which is to be formed, is fanned out to packaging part, it means that I/O pads on tube core can be with It is re-distributed the region bigger than tube core, therefore the quantity for the I/O pads being encapsulated into die surfaces can be increased.
Invention content
According to an aspect of the invention, there is provided a kind of structure, including the first packaging part.First packaging part includes: Moulding compound;Through-hole passes through moulding compound;Component pipe core is molded in moulding compound;And buffer layer, on moulding compound and connect Touch plastics, opening reach through-hole across buffer layer, and buffer layer is in the parallel plane in the interface between moulding compound and buffer layer In and around opening around have ripple.
Preferably, the first packaging part further includes the laminated film being located on buffer layer, and buffer layer is arranged in laminated film and molding Between material, it is open across laminated film.
Preferably, it is arranged in around opening to corrugated periodic.
Preferably, the height of wave crest-trough of ripple is included between 0.2 μm and 20 μm.
Preferably, the wave crest of ripple-wave crest distance is included between 0.2 μm and 20 μm.
Preferably, the average diameter of opening is included between 10 μm and 600 μm.
Preferably, which further includes:Second packaging part, by being bonded to the first encapsulation across the electrical connector of opening Part.
Preferably, the first packaging part further includes the guiding groove extended to from the surface of buffer layer in buffer layer, wherein is drawn Guide groove is not aligned with component pipe core.
Preferably, guiding groove forms annular, and guiding groove is around the central part of buffer layer, simultaneous buffering layer Central part is Chong Die with the entirety of component pipe core.
According to another aspect of the present invention, a kind of structure, including the first packaging part and the second packaging part are provided.First envelope Piece installing, including:Moulding compound, including flat top and planar bottom surface;Component pipe core is molded material transverse sealing;Through-hole passes through mould Plastics;With flat dielectric layer, above the flat top of moulding compound and the flat top of moulding compound is contacted, opening is across flat Smooth dielectric layer reaches through-hole, and ripple is located at flat dielectric layer and around opening.Second packaging part is bonded to the first packaging part, First packaging part is electrically connected to the second packaging part by external electrical connections, and external electrical connections are at least partially disposed on opening In.
Preferably, the first packaging part further includes the laminated film being located on flat dielectric layer, and flat dielectric layer setting is being laminated Between film and moulding compound, it is open across laminated film.
Preferably, it is arranged in corrugated periodic around opening.
Preferably, guiding groove is located at the region phase in flat dielectric layer and in planar dielectric with component pipe core Corresponding region.
Preferably, which further includes:Bottom filler is at least partially disposed on the first packaging part and the second packaging part Between.
According to another aspect of the invention, it provides a method, including forms packaging part.Forming packaging part includes:Shape At the composite structure for including component pipe core, moulding compound and through-hole, moulding compound moulding compound first surface and moulding compound second At least partly transverse sealing component pipe core, through-hole extend to mould in moulding compound and from the first surface of moulding compound between surface The second surface of plastics;Buffer layer is formed on the first surface of moulding compound;And it is formed across buffer layer using laser drill The opening of through-hole is reached, buffer layer, which has, is located at parameatal ripple.
Preferably, forming packaging part further includes:Laminated film is formed on the buffer layer, and forming opening further includes:Use laser Drilling forms the opening across laminated film.
Preferably, laser drill includes:It is used with the incident angle θ of the normal of the exposed surface relative to buffer layer sharp Light, a length of λ of light wave of laser, ripple have according toThe wave crest of definition-wave crest distance, delta.
Preferably, corrugated periodic is arranged in around opening.
Preferably, laser drill is selected from the group being made of 355nm, 532nm, 1064nm, 9.4 μm and combination thereof The wavelength of the middle laser used.
Preferably, it further includes that guiding groove is formed in buffer layer to form packaging part.
Description of the drawings
Embodiment and its advantage in order to better understand, are described below in conjunction with attached drawing, wherein:
Fig. 1 to Figure 12 and Figure 13 A is to be fanned out to through-hole (TIV) packaging part according to the manufacture of some exemplary embodiments is integrated Intermediate stage sectional view;
Figure 13 B to Figure 13 D are the diagrams according to the opening of some exemplary embodiments being formed in TIV packaging parts;
Figure 13 E to Figure 13 J are that have variable size according to being formed in TIV packaging parts for some exemplary embodiments The layout of opening;
Figure 14 A and Figure 14 B respectively illustrate the sectional view and top view of the TIV packaging parts according to some exemplary embodiments Figure.
Figure 15 shows the engagement of TIV packaging parts and top seal;And
Figure 16 is shown in the gap between TIV packaging parts and top seal according to some optional exemplary embodiments Bottom filler distribution.
Specific implementation mode
The manufacture and use of the embodiment of the present disclosure discussed further below.It should be appreciated, however, that embodiment provide many can What is embodied under various specified conditions can application concept.The specific embodiment discussed is schematical rather than limits this Scope of disclosure.
Integrated it is fanned out to (InFO) packaging part and forming method thereof according to what each exemplary embodiment provided including through-hole. It shows to form the intermediate stage of InFO packaging parts.Discuss the variation of embodiment.In each diagram and illustrated embodiment, class As reference label for indicating similar element.
Fig. 1 is to the manufacture encapsulating structure that Figure 12, Figure 13 A, Figure 14 A, Figure 15 and Figure 16 are according to some exemplary embodiments Intermediate stage sectional view.Referring to Fig.1, carrier 20 is set, and adhesive layer 22 is arranged on carrier 20.Carrier 20 can be Blank glass carrier, blank ceramic monolith etc..Adhesive layer 22 can be solidifying by such as ultraviolet light (UV) gel, photothermal conversion (LTHC) The adhesive of glue etc. is formed, although other kinds of adhesive can also be used.
With reference to Fig. 2, buffer layer 24 is formed in 22 top of adhesive layer.Buffer layer 24 is dielectric layer, and it includes polymerization that can be The polymeric layer of object.Polymer for example can be polyimides, polybenzoxazoles (PBO), benzocyclobutene (BCB), aginomoto Enhance film (ABF), solder mask (SR) etc..Buffer layer 24 is the flatness layer for having uniform thickness, wherein thickness T1 can be greater than about 2 μm, and can be between about 2 μm and about 40 μm.The top and bottom of buffer layer 24 are also flat.
Such as by physical vapor gas deposition (PVD) or metal foil laminated, seed layer 26 is formed on buffer layer 24.It is brilliant Kind layer 26 may include copper, copper alloy, aluminium, titanium, titanium alloy or combination thereof.In some embodiments, seed layer 26 includes The titanium layer 26A and layers of copper 26B above titanium layer 26A.In an alternative embodiment, seed layer 26 is layers of copper.
With reference to Fig. 3, photoresist 28 is applied to 26 top of seed layer, is then patterned.As a result, the shape in photoresist 28 At opening 30, some parts of seed layer 26 are exposed by opening.
As shown in figure 4, forming metal parts 32 in photoresist 28 by plating (can be plating or electroless plating).Metal portion Part 32 is plated on the expose portion of seed layer 26.Metal parts 32 includes copper, aluminium, tungsten, nickel, solder or their alloy.Gold The top view diagram shape for belonging to component 32 can be rectangle, square, circle etc..Pass through the thickness for the tube core 34 (Fig. 7) being subsequently placed with Determine the height of metal parts 32, in some embodiments, the height of metal parts 32 is more than the thickness of tube core 34.It is plating After metal parts 32, photoresist 28 is removed, and obtained structure is shown in FIG. 5.After removing photoresist 28, Expose the part that the covering of glue 28 is photo-etched in seed layer 26.
With reference to Fig. 6, etching step is executed to remove the expose portion of seed layer 26, wherein etching can be anisotropy erosion It carves.On the other hand, part Chong Die with metal parts 32 in seed layer 26 keeps not being etched.In entire description, metal portion The remaining lower part of part 32 and seed layer 26 is collectively referred to as InFO through-holes (TIV) 33, is also referred to as through-hole 33.Although seed layer 26 It is illustrated as the layer detached with metal parts 32, but when seed layer 26 is by the material similar or identical with the metal parts 32 of corresponding top Material is when forming, seed layer 26 can merge with metal parts 32 and between them without recognizable interface.In optional implementation Example in, seed layer 26 can between metal parts 32 there are recognizable interfaces.
Fig. 7 is shown is placed on 24 top of buffer layer by component pipe core 34.Component pipe core 34 can be viscous by adhesive layer 36 It is bonded to buffer layer 24.Component pipe core 34 can be logical device tube core, including logic transistor.In some exemplary implementations In example, component pipe core 34 is designed to mobile application, and can be central computation unit (CPU) tube core, power management collection At circuit (PMIC) tube core, transceiver (TRX) tube core etc..Each component pipe core 34 includes the semiconductor lining of contact adhesive layer 36 Bottom 35 (for example, silicon substrate), wherein the back side of semiconductor substrate 35 is contacted with adhesive layer 36.
In some exemplary embodiments, metal column 40 (such as copper post) is formed the top of component pipe core 34, and It is electrically connected to the device of such as transistor (not shown) in component pipe core 34.In some embodiments, dielectric layer 38 is formed in At the top surface of respective devices tube core 34,40 lower part of metal column is located at least in dielectric layer 38.In some embodiments, metal column It 40 top surface can also be with the either flush of metal column 40.Optionally, dielectric layer 38 is not formed, and metal column 40 is protruded right Answer the top of the top dielectric of component pipe core 34.
With reference to Fig. 8, molding material 42 is molded on component pipe core 34 and TIV 33.Molding material 42 fills component pipe core Gap between 34 and TIV 33, and can be contacted with buffer layer 24.In addition, when metal column 40 is prominent metal column, mould Prepared material 42 is filled into the gap between each metal column 40.Molding material 42 may include moulding compound, molded bottom filling Object, epoxy resin or resin.The top surface of molding material 42 is higher than the top of metal column 40 and TIV 33.
Next, grinding steps are executed so that molding material 42 is thinned, until exposing underfill metal column 40 and TIV 33. The structure being shown in FIG. 9.Due to grinding, the top 32A of metal parts 32 is substantially concordant with the top 40A of metal column 40 (coplanar), and it is substantially concordant with the top surface 42A of molding material 42 (coplanar).As grinding as a result, can generate such as golden The metal residue of metal particles, and stay on top surface 32A, 40A and 42A.It therefore, after milling, can be for example by wet Etching executes cleaning so that removal metal residue.
Next, referring to Fig.1 0, redistribution lines (RLD) 44 are formed in 42 top of molding material to be connected to 40 He of metal column TIV 33.RDL 44 can also interconnect metal column 40 and TIV 33.According to various embodiments, the formation of one or more dielectric layers 46 Superstructure shown in Fig. 9, wherein RDL44 are formed in dielectric layer 46.In some embodiments, in RDL 44 and dielectric layer 46 One layer of formation include:Form blanket copper seed layer;Simultaneously patterned mask layer is formed above blanket copper seed layer;Execute plating To form RDL 44;Remove mask layer;And it executes quickly to execute and not covered by RDL 44 with removing in blanket copper seed layer Part.In an alternative embodiment, RDL 44 is formed by the following method:Deposited metal layer;Patterned metal layer;And be situated between Electric material 46 fills the gap between RDL 44.RDL 44 may include metal or metal alloy, including aluminium, copper, tungsten and/or it Alloy.Figure 10 shows two layers of RDL 44, although according to the cabling requirement of corresponding packaging part, can have one layer or more In two layers of RDL.In these embodiments, dielectric layer 46 may include polymer, such as polyimides, benzocyclobutene (BCB), polybenzoxazoles (PBO) etc..Optionally, dielectric layer 46 may include non-organic dielectric material, such as silica, nitridation Silicon, silicon carbide, silicon oxynitride etc..
Figure 11 shows the formation of the electrical connector 48 according to some exemplary embodiments.The formation of electrical connector 48 can be with Including:On the exposed portion of RDL 44 place soldered ball (or bottom projections metal (if formed if, be not shown), then Solder balls.In an alternative embodiment, the formation of electrical connector 48 includes:Plating step is executed to form solder above RDL 44 Region is then refluxed for socket area.Electrical connector 48 can also include metal column or metal column and weld cap, can pass through plating Technique is formed.In entire description, include the RDL 44 and dielectric layer of component pipe core 34, TIV 33, molding material 42, overlying 46 and the composite structure of buffer layer 24 be referred to as TIV packaging parts 50, can be combination wafer.
Next, TIV packaging parts 50 are detached with carrier 20.Also adhesive layer 22 is cleaned from TIV packaging parts 50.In fig. 12 Show obtained structure.As removal adhesive layer 22 as a result, exposing buffer layer 24.TIV packaging parts 50 are further glued It is bonded to cutting belt 52, wherein electrical connector 48 is towards cutting belt 52 and can contact cutting belt 52.In some embodiments, Laminated film 54 is placed on the buffer layer 24 of exposing, wherein laminated film 54 may include SR, ABF, back side coated etc..Can It selects in film, no laminated film 54 is placed on buffer layer 24.
Figure 13 A show the opening of buffer layer 24 and laminated film 54 (if any).Opening 56 and 58 shape of guiding groove At in buffer layer 24 and laminated film 54.According to some embodiments, opening 56 and guiding groove 58 are formed using laser drill, to the greatest extent Pipe can also use photoetching process.Expose TIV 33 by opening 56.Include the implementation of titanium part 26A in seed layer 26 (Fig. 1) In example, etching step is executed to remove titanium part 26A so that expose the copper part 26B of seed layer 26.Otherwise, if seed layer 26 do not include titanium, then skips etching step.
Figure 13 B to Figure 13 D show the pattern and Figure 13 E of the opening 56 when forming opening 56 using laser drill extremely Figure 13 J show the exemplary outlet 56 with variable size.Figure 13 B show the opening 56 in laminated film 54 and buffer layer 24 A part sectional view (for example, in the X-Z plane corresponding to sectional view of Figure 13 A).As the laser for forming opening 56 Drilling 82 as a result, buffer layer 24 can have ripple 80.Laser drill 82 (for example, laser) can be relative to the method for those layers Line 84 (for example, in shown Z-direction) is applied with incidence angle θ on (impinge on) each layer.As shown, ripple 80 is formed In buffer layer 24, and in other embodiments, ripple 80 is additionally formed in laminated film 54 (if present).Such as figure It is shown, side wall of the ripple 80 far from laminated film 54 in buffer layer 24 and to 56 prominent (project) of opening.
Figure 13 C and Figure 13 D show the layout (such as in X-Y plane) of opening 56.Figure 13 D are further shown specifically Diagram 86 in Figure 13 C.Ripple 80 in buffer layer 24 is formed in around opening 56.Ripple 80 can around opening 56 To be in periodic arrangement.Opening 56 can have diameter D, can be to be exposed by opening 56 in seed layer 26 and/or TIV 33 Partial diameter.Diameter D can use instantaneous diameter (can from ripple 80 to opposite ripple 80, from trough to opposed valleys, or Trough is to opposite ripple 80) it indicates.Average diameter DAVEIt can be expressed as the average value of the instantaneous diameter D across opening 56. In some embodiments, the 56 average diameter DAVE of being open can be from about 10 μm to about 600 μm.
Adjacent ripple 80 can be with the distance, delta of wave crest-wave crest.In addition, ripple 80 can be with the height of trough-wave crest H.In some embodiments, the height H of ripple 80 can be from about 0.2 μm to about 20 μm.In some embodiments, distance, delta It can be from about 0.2 μm to about 20 μm.In some embodiments, distance, delta can be expressed asWherein, λ Be the radiant light (for example, laser) used in laser drill wavelength and θ be the radiant light used in laser drill incidence Angle (as shown in Figure 13 B).In some embodiments, can be that (it can have 355nm in the sources UV for the lasing light emitter of laser drill Wavelength), green source (can be with the wavelength of 532nm), Nd:The sources YAG (can be with the wavelength of 1064nm), CO2Source (can have 9.4 μm of wavelength) etc..In the illustrated embodiment of Figure 13 C and Figure 13 D, height H is about 8 μm, and distance, delta is about 10 μm。
Figure 13 E to Figure 13 J are shown with different average diameter DAVEOpening 56 layout (for example, in X-Y plane In).The average diameter D of opening 56 in Figure 13 EAVEIt is 80 μm.The average diameter D of opening 56 in Figure 13 FAVEIt is 120 μm.Figure The average diameter D of opening 56 in 13GAVEIt is 152 μm.The average diameter D of opening 56 in Figure 13 HAVEIt is 190 μm.In Figure 13 I Opening 56 average diameter DAVEIt is 220 μm.The average diameter D of opening 56 in Figure 13 JAVEIt is 250 μm.
Referring back to Figure 13 A, guiding groove 58 is also formed in buffer layer 24 and laminated film 54.In some embodiments, As shown in Figure 14B, guiding groove is formed as annular.Therefore, guiding groove 58 is alternatively termed guide groove grooved ring 58, although also It can be formed and be independent guiding groove band or part-toroidal.As shown in figure 13, in some embodiments, each guiding groove 58 Can surround the buffer layer 24 Chong Die with entire component pipe core 34 central part, wherein guiding groove 58 not with component pipe core 34 alignment.It rephrases the statement, guiding groove 58 does not extend in the region of direct overlying component pipe core 34.The bottom of guiding groove 58 Can be substantially concordant with the top surface 42A of molding material 42, therefore bootup process 58 passes through buffer layer 24 and laminated film 54.Optional In embodiment, guiding groove 58 is not passed through buffer layer 24, and the lower part of buffer layer 24 is retained in the lower section of guiding groove 58. In a further alternative embodiment, guiding groove 58 passes through buffer layer 24 and extends in molding material 42.
Next, TIV packaging parts 50 are cut into multiple TIV packaging parts 60.Figure 14 A and Figure 14 B respectively illustrate one The sectional view and top view of TIV packaging parts 60.In some embodiments, coating soldering paste (not shown) is to protect the TIV of exposing 33.In an alternative embodiment, it is not coated by soldering paste.As shown in Figure 14B, in top view, guide groove grooved ring 58 is around component pipe core 34.Although the inward flange of guide groove grooved ring 58 is illustrated offset from the corresponding edge of component pipe core 34, guide groove grooved ring 58 it is interior Edge can also be aligned with the edge of respective devices tube core 34.In some embodiments, exist in each TIV packaging parts 60 single A guide groove grooved ring 58.In an alternative embodiment, there are two or more guide groove grooved rings 58.The width W1 of guide groove grooved ring 58 60 μm can be greater than about with W2, and can be between about 60 μm and about 250 μm.Depth D1 (the figures of guide groove grooved ring 58 2 μm can 14A) be greater than about, and can be between about 2 μm and about 50 μm.
Figure 15 shows the engagement of top seal 62 and TIV packaging parts 60, wherein engagement can be real by socket area 68 It is existing.In entire description, TIV packaging parts 60 are also referred to as bottom package 60, because they can be used as bottom as shown in figure 15 Packaging part.In some embodiments, top seal 62 includes being bonded to the component pipe core 66 of package substrate 64.Component pipe core 66 May include storage tube core, which can for example deposit for static RAM (SRAM) tube core, dynamic random Access to memory (DRAM) tube core etc..The bottom surface of top seal 62 and the top surface of TIV packaging parts 60 are spaced from each other gap 70, In, top seal 62 and TIV packaging parts 60 can have standoff distance S1, can about 10 μm and about 100 μm it Between, although standoff distance S1 can also have other values.
Referring to Fig.1 6, top seal 62 and TIV packaging parts 60 after engagement are further bonded to another encapsulation part Part 72 (it can be package substrate in some embodiments).In an alternative embodiment, package parts 72 include printed circuit board (PCB).Package parts 72 can have electrical connector 76 (such as metal pad or metal column), and metal on opposite sides Line 78 interconnects electrical connector 76.
In some embodiments, distribution bottom filler 74 is to fill gap 70 (Figure 15).Bottom filler 74 can be with The peripheral portion of seal clearance 70, and the central part 70 ' in gap 70 is not filled by bottom filler 74.In bottom filler In 74 assigning process, bottom filler 74 flows into gap 70 and guiding groove 58 (Figure 15).Between being deeper than due to guiding groove 58 The central part 70 ' of gap 70, thus bottom filler 74 in guiding groove 58 than being flowed in center clearance part 70 ' Soon.Therefore, bottom filler 74 will be first filled with guiding before it can flow into central part 70 ' (Chong Die with component pipe core 34) Groove 58.By terminating underfill process in reasonable time, bottom filler 74 is filled into guiding groove 58 but does not have Have and enters center clearance part 70 '.Therefore, bottom filler 74 can surround but without filling center clearance part 70 '.Cause This, center clearance part 70 ' remains white space, can be the gas gap filled with gas or vacuum space.
In an embodiment of the present invention, the top seal of TIV packaging parts and overlying is spaced from each other by white space, Middle white space can be gas gap or vacuum space.Since the thermal insulation capabilities of white space are better than bottom filler, So white space prevents the heat of the component pipe core in TIV packaging parts from conducting into top seal with better ability Tube core and influence the operation of the tube core in top seal.It should be understood that if not forming guiding groove, bottom is filled out The distance filled in the gap that object is filled between TIV packaging parts and top seal is random, therefore the formation of white space To be non-uniform.By forming guiding groove in buffer layer, the formation of white space is more controllable and more uniform.
According to some embodiments, a kind of bottom package includes moulding compound, above moulding compound and contacts moulding compound Buffer layer and through-hole across moulding compound.Component pipe core is molded in moulding compound.Guiding groove prolongs from the top surface of buffer layer It reaches in buffer layer, wherein guiding groove is not aligned with component pipe core.
According to other embodiment, a kind of packaging part includes bottom package and is bonded to the top encapsulation of bottom package Part.Bottom package includes:Moulding compound has flat top and flat ground;Component pipe core is molded in moulding compound;It is flat Dielectric layer above the flat top of moulding compound and contacts the flat top of moulding compound;Through-hole passes through moulding compound;And the One guide groove grooved ring is located in flat dielectric layer.Top seal separates a gap with bottom package, wherein the first guiding Ditch grooved ring is connected to gap.Bottom filler fills at least part on the periphery and the first guide groove grooved ring in gap, wherein The central part of gap is surround by bottom filler, and central part forms white space.
According to other other embodiment, a kind of method includes:Through-hole is formed above dielectric buffer layer;In dielectric buffers Layer top mask placement device tube core;Molded device tube core and through-hole in moulding compound;And planarization moulding compound is to expose device pipe The through-hole and metal column of core.Redistribution lines are formed as overlying through-hole and metal column and are electrically connected to through-hole and metal column.It is being situated between Opening is formed in electric buffer layer to expose through-hole.Guide groove grooved ring is formed in dielectric buffer layer.
According to other embodiment, a kind of structure includes the first packaging part.First packaging part includes moulding compound, passes through molding The through-hole of material, the component pipe core being molded in moulding compound and on moulding compound and contact the buffer layer of moulding compound.Opening is worn It crosses buffer layer and reaches through-hole.Buffer layer has in the parallel plane in the interface between moulding compound and buffer layer and is looped around Parameatal ripple.
According to other embodiment, a kind of structure includes the first packaging part and is bonded to the second encapsulation of the first packaging part Part.First packaging part includes:Moulding compound, including flat top and planar bottom surface;Component pipe core is laterally molded material sealing; Through-hole passes through moulding compound;And flat dielectric layer, above the flat top of moulding compound and contact the flat top of moulding compound Face.Opening reaches through-hole across flat dielectric layer.Flat dielectric layer middle ring has ripple around opening.External electrical connections are by first Packaging part is electrically coupled to the second packaging part, and external electrical connections are at least partially disposed in opening.
According to still other embodiments, a kind of method includes forming packaging part.It includes forming composite structure to form packaging part.Group It includes component pipe core, moulding compound and through-hole to close structure.Moulding compound seals the first surface and moulding compound of moulding compound at least partly Second surface between component pipe core.Through-hole extends to the of moulding compound in moulding compound and from the first surface of moulding compound Two surfaces.Forming packaging part further includes:Buffer layer is formed on the first surface of moulding compound;And laser drill is used, it passes through Buffer layer forms the opening for reaching through-hole.Buffer layer has ripple around opening.
Although embodiment and its advantage is described in detail, it should be appreciated that without departing substantially from spirit defined in the appended claims In the case of range, various modifications can be carried out, replaces and changes.In addition, the scope of the present invention is not limited to retouch in specification Technique, machine, manufacture and the things stated, device, method and steps combination specific embodiment.Those skilled in the art's energy It is enough readily appreciated that, execution and the essentially identical function of corresponding embodiment described herein or realization can be utilized according to the disclosure The combination of essentially identical result existing or technique, machine, manufacture and the things, device, method and steps developed later. Therefore, appended claims include these techniques, machine, manufacture and things, device, method and steps combination in.This Outside, each claim constitutes independent embodiment, and the combination of each claim and embodiment is included in the present invention In the range of.

Claims (16)

1. a kind of semiconductor package part structure, including:
First packaging part, including:
Moulding compound;
Through-hole passes through the moulding compound;
Component pipe core is molded in the moulding compound;And
Buffer layer on the moulding compound and contacts the moulding compound, and opening reaches the through-hole across the buffer layer, The buffer layer is in the parallel plane in the interface between the moulding compound and the buffer layer and around the opening Surrounding has ripple;
Guiding groove is extended to from the surface of the buffer layer in the buffer layer, the guiding groove not with the device pipe Core is aligned, and the guiding groove forms annular, and the guiding groove surround the central part of the buffer layer, while described The central part of buffer layer is Chong Die with the entirety of the component pipe core.
2. semiconductor package part structure according to claim 1, wherein first packaging part further includes being located at described delay The laminated film on layer is rushed, the buffer layer is arranged between the laminated film and the moulding compound, and the opening is across the layer Press mold.
3. semiconductor package part structure according to claim 1, wherein be arranged in the opening to the corrugated periodic Around.
4. semiconductor package part structure according to claim 1, wherein the height of wave crest-trough of the ripple includes Between 0.2 μm and 20 μm.
5. semiconductor package part structure according to claim 1, wherein the wave crest of the ripple-wave crest distance is included in Between 0.2 μm and 20 μm.
6. semiconductor package part structure according to claim 1, wherein the average diameter of the opening be included in 10 μm and Between 600 μm.
7. semiconductor package part structure according to claim 1, further includes:Second packaging part, by passing through the opening Electrical connector be bonded to first packaging part.
8. a kind of semiconductor package part structure, including:
First packaging part, including:
Moulding compound, including flat top and planar bottom surface;
Component pipe core, by the moulding compound transverse sealing;
Through-hole passes through the moulding compound;With
Flat dielectric layer above the flat top of the moulding compound and contacts the flat top of the moulding compound, opening The through-hole is reached across the flat dielectric layer, ripple is located at the flat dielectric layer and around the opening;
Guiding groove is located at the region in the flat dielectric layer and in the flat dielectric layer with the component pipe core Corresponding region;And
Second packaging part, is bonded to first packaging part, and first packaging part is electrically connected to described by external electrical connections Second packaging part, the external electrical connections are at least partially disposed in the opening.
9. semiconductor package part structure according to claim 8, wherein first packaging part further includes being located at described put down Laminated film on smooth dielectric layer, the flat dielectric layer are arranged between the laminated film and the moulding compound, and the opening is worn Cross the laminated film.
10. semiconductor package part structure according to claim 8, wherein be arranged in the corrugated periodic described open Around mouthful.
11. semiconductor package part structure according to claim 8, further includes:Bottom filler is at least partially disposed on Between first packaging part and second packaging part.
12. a kind of method being used to form semiconductor package part, including:
Packaging part is formed, including:
Formation includes the composite structure of component pipe core, moulding compound and through-hole, first surface of the moulding compound in the moulding compound At least partly component pipe core described in transverse sealing between the second surface of the moulding compound, the through-hole is in the moulding compound And the second surface of the moulding compound is extended to from the first surface of the moulding compound;
Buffer layer is formed on the first surface of the moulding compound;And
The opening that the through-hole is reached across the buffer layer is formed using laser drill, the buffer layer, which has, is located at described open Ripple around mouthful;
Guiding groove is formed in the buffer layer, wherein the guiding groove is located in the buffer layer and around described Region corresponding with the region of the component pipe core in buffer layer.
13. the method according to claim 12 for being used to form semiconductor package part, wherein form the packaging part and also wrap It includes:Laminated film is formed on the buffer layer, forming the opening further includes:It is formed across the laminated film using laser drill The opening.
14. the method according to claim 12 for being used to form semiconductor package part, wherein the laser drill includes: Laser, a length of λ of light wave of the laser, institute are used with the incident angle θ of the normal of the exposed surface relative to the buffer layer State ripple have according toThe wave crest of definition-wave crest distance, delta.
15. the method according to claim 12 for being used to form semiconductor package part, wherein the corrugated periodic arrangement Around the opening.
16. the method according to claim 12 for being used to form semiconductor package part, wherein from by 355nm, 532nm, The wavelength of the laser used in the laser drill is selected in the group that 1064nm, 9.4 μm and combination thereof form.
CN201510523238.7A 2014-12-19 2015-08-24 There is the integrated fan-out structure of opening in buffer layer Active CN105720018B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/577,450 US9455211B2 (en) 2013-09-11 2014-12-19 Integrated fan-out structure with openings in buffer layer
US14/577,450 2014-12-19

Publications (2)

Publication Number Publication Date
CN105720018A CN105720018A (en) 2016-06-29
CN105720018B true CN105720018B (en) 2018-08-07

Family

ID=56097782

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510523238.7A Active CN105720018B (en) 2014-12-19 2015-08-24 There is the integrated fan-out structure of opening in buffer layer

Country Status (4)

Country Link
KR (1) KR101680970B1 (en)
CN (1) CN105720018B (en)
DE (1) DE102015104507B4 (en)
TW (1) TWI587464B (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10290609B2 (en) 2016-10-13 2019-05-14 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method of the same
US9812379B1 (en) * 2016-10-19 2017-11-07 Win Semiconductors Corp. Semiconductor package and manufacturing method
FR3070091B1 (en) 2017-08-08 2020-02-07 3Dis Technologies ELECTRONIC SYSTEM COMPRISING A LOWER REDISTRIBUTION LAYER AND METHOD FOR MANUFACTURING SUCH AN ELECTRONIC SYSTEM
US10510645B2 (en) 2018-04-30 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Planarizing RDLs in RDL-first processes through CMP process
US11133269B2 (en) 2019-10-17 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1763921A (en) * 2004-10-22 2006-04-26 台湾积体电路制造股份有限公司 Copper interconnect structure with modulated topography and method for forming the same
CN101528437A (en) * 2006-10-16 2009-09-09 大成普拉斯株式会社 Composite of metal with resin and process for producing the same
CN101683004A (en) * 2008-03-27 2010-03-24 揖斐电株式会社 Method for manufacturing multilayer printed wiring board

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5255431A (en) * 1992-06-26 1993-10-26 General Electric Company Method of using frozen epoxy for placing pin-mounted components in a circuit module
DE102006010511A1 (en) * 2006-03-07 2007-09-13 Infineon Technologies Ag Vertical semiconductor arrangement e.g. semiconductor chip stack, for printed circuit board substrate, has auxiliary layer that is bounded on area of relevant main side or includes structure provided with recess, channel, wall and trench
US7863090B2 (en) * 2007-06-25 2011-01-04 Epic Technologies, Inc. Packaged electronic modules and fabrication methods thereof implementing a cell phone or other electronic system
US8451620B2 (en) * 2009-11-30 2013-05-28 Micron Technology, Inc. Package including an underfill material in a portion of an area between the package and a substrate or another package
KR101177664B1 (en) 2011-05-11 2012-08-27 삼성전기주식회사 Method for manufacturing printed circuit board
US10049964B2 (en) 2012-03-23 2018-08-14 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units
TWI461122B (en) * 2013-01-07 2014-11-11 Ecocera Optronics Co Ltd Circuit board and method for manufacturing the same
US9048222B2 (en) * 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1763921A (en) * 2004-10-22 2006-04-26 台湾积体电路制造股份有限公司 Copper interconnect structure with modulated topography and method for forming the same
CN101528437A (en) * 2006-10-16 2009-09-09 大成普拉斯株式会社 Composite of metal with resin and process for producing the same
CN101683004A (en) * 2008-03-27 2010-03-24 揖斐电株式会社 Method for manufacturing multilayer printed wiring board

Also Published As

Publication number Publication date
KR20160075299A (en) 2016-06-29
KR101680970B1 (en) 2016-11-29
DE102015104507B4 (en) 2022-06-30
TW201633476A (en) 2016-09-16
CN105720018A (en) 2016-06-29
DE102015104507A1 (en) 2016-06-23
TWI587464B (en) 2017-06-11

Similar Documents

Publication Publication Date Title
US10559525B2 (en) Embedded silicon substrate fan-out type 3D packaging structure
US10354982B2 (en) Integrated fan-out structure with guiding trenches in buffer layer
US9799581B2 (en) Integrated fan-out structure with openings in buffer layer
WO2019161641A1 (en) Chip and packaging method
TWI637473B (en) Package, semiconductor device, and forming method of package
US20180182727A1 (en) Embedded silicon substrate fan-out type packaging structure and manufacturing method therefor
CN105720018B (en) There is the integrated fan-out structure of opening in buffer layer
TWI355034B (en) Wafer level package structure and fabrication meth
CN104600064B (en) Chip structure and method on packaging part
WO2017114323A1 (en) Packaging structure, electronic device and packaging method
US6822324B2 (en) Wafer-level package with a cavity and fabricating method thereof
CN107768351A (en) Semiconductor package part with heat engine electrical chip and forming method thereof
CN105990272A (en) Stripping caused through forming groove elimination saw cutting
CN106847794A (en) Antenna and waveguide in message structure
CN107123605A (en) Semiconductor package part and its technique of doing over again
CN105895596A (en) Reducing Cracking by Adjusting Opening Size in Pop Packages
CN104538318B (en) A kind of Fanout type wafer level chip method for packing
CN106206511A (en) Device, encapsulating structure and forming method thereof
CN103107099B (en) The method of semiconductor packages and encapsulated semiconductor device
CN109786360A (en) Semiconductor package part and method
CN107689351A (en) Encapsulating structure
US20180033775A1 (en) Packages with Die Stack Including Exposed Molding Underfill
CN110391191A (en) Laminated packaging structure
CN109786274A (en) Semiconductor devices and its manufacturing method
CN107342278A (en) Encapsulating structure

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant