CN110600438A - Embedded multi-chip and element SIP fan-out type packaging structure and manufacturing method thereof - Google Patents
Embedded multi-chip and element SIP fan-out type packaging structure and manufacturing method thereof Download PDFInfo
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- CN110600438A CN110600438A CN201910968164.6A CN201910968164A CN110600438A CN 110600438 A CN110600438 A CN 110600438A CN 201910968164 A CN201910968164 A CN 201910968164A CN 110600438 A CN110600438 A CN 110600438A
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- 239000002184 metal Substances 0.000 claims abstract description 51
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- 229920005989 resin Polymers 0.000 claims abstract description 17
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 18
- 229910052802 copper Inorganic materials 0.000 claims description 18
- 239000010949 copper Substances 0.000 claims description 18
- 239000003292 glue Substances 0.000 claims description 18
- 229910000679 solder Inorganic materials 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 13
- 239000003822 epoxy resin Substances 0.000 claims description 12
- 229920000647 polyepoxide Polymers 0.000 claims description 12
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- 238000013329 compounding Methods 0.000 claims description 6
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- 230000008021 deposition Effects 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 230000010354 integration Effects 0.000 abstract description 19
- 230000017525 heat dissipation Effects 0.000 abstract description 9
- 230000000694 effects Effects 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 172
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- 230000005540 biological transmission Effects 0.000 description 6
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- 229920006336 epoxy molding compound Polymers 0.000 description 4
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
- H01L23/295—Organic, e.g. plastic containing a filler
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3737—Organic materials with or without a thermoconductive filler
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention discloses an embedded multi-chip and element SIP fan-out type packaging structure and a manufacturing method thereof, wherein the embedded multi-chip and element SIP fan-out type packaging structure comprises the following components: the plastic packaging layer is provided with a mounting hole along the thickness direction and is provided with a first side surface and a second side surface along the thickness direction; the first chips and the first passive elements are positioned in the mounting holes, and composite layers are filled among the first chips, the first passive elements and the side walls of the mounting holes and comprise filling resin and inorganic particles uniformly distributed in the filling resin; the rewiring layer is positioned on the first side surface of the plastic packaging layer and is electrically connected with the first chip and the first passive element; and the metal bump is welded with the bonding pad area of the redistribution layer. The invention can achieve the effect of resisting the warping and deformation of the packaging structure, simultaneously can improve the heat dissipation efficiency of the chip and the passive element, can increase the integration degree of chip packaging, and can realize the integration of a micro system under smaller volume.
Description
Technical Field
The invention relates to the technical field of advanced electronic packaging, in particular to an embedded multi-chip and element SIP fan-out type packaging structure and a manufacturing method thereof.
Background
Nowadays, the integration of intelligent systems continuously improves the requirements on the functions and performances of electronic component products in unit area, and meanwhile, the sizes of the products are also continuously reduced, so that how to integrate components of different functional modules in a very small space and realize the basic functions of portable products is a key problem to be solved at present. Under the multiple pressure of the extension of moore's law, such as physical limit, huge capital investment, continuous reduction of product size and the like, the fan-out integration advanced packaging technology is adopted to realize high-density integration, multi-element embedded integration, volume miniaturization and lower cost, and the fan-out integration advanced packaging technology becomes an urgent need for the development of semiconductor technology.
Currently, for a fan-out chip package structure, there are two main technical problems:
the difference of Coefficient of Thermal Expansion (CTE) among a packaged chip, a passive element and a plastic package material is large, and the problem of warping is easy to occur during plastic package;
and secondly, the heat dissipation effect of the chip and the passive element is poor, and other heat dissipation structures need to be additionally arranged on the back of the chip to improve the heat dissipation effect, so that the product size of the fan-out chip packaging structure is increased.
Disclosure of Invention
The invention aims to provide an embedded multi-chip and element SIP fan-out type packaging structure and a manufacturing method thereof, which can achieve the effect of resisting the warping and deformation of the packaging structure, can improve the heat dissipation efficiency of a chip and a passive element, can increase the integration degree of chip packaging, and can realize the integration of a micro system under smaller volume.
In order to achieve the purpose, the invention adopts the following technical scheme:
in one aspect, an embedded multi-chip and component SIP fan-out package structure is provided, comprising:
the plastic packaging layer is provided with a mounting hole along the thickness direction and is provided with a first side surface and a second side surface along the thickness direction;
the first chips and the first passive elements are positioned in the mounting holes, the front surfaces of the first chips and the first passive elements face the first side surface, and composite layers are filled among the first chips, the first passive elements and the side walls of the mounting holes and comprise filling resin and inorganic particles uniformly distributed in the filling resin;
the rewiring layer is positioned on the first side face of the plastic packaging layer and is electrically connected with the first chip and the first passive element, and the rewiring layer is provided with a bonding pad area and a non-bonding pad area;
and the metal bump is welded with the bonding pad area of the redistribution layer.
As a preferred scheme of the embedded multi-chip and component SIP fan-out package structure, the filling resin is epoxy resin; the plastic packaging layer is EMC.
As a preferred scheme of the embedded multi-chip and component SIP fan-out type packaging structure, the method further comprises the following steps:
the dielectric layer is positioned on the first side surface of the plastic packaging layer, and a through hole for exposing the electric signal connection part of the first chip and the first passive element is formed in the dielectric layer;
the seed layer covers the dielectric layer and the inner wall of the through hole, the rewiring layer is positioned on the seed layer, and the seed layer and the rewiring layer are provided with graphical holes which enable parts of the dielectric layer to be exposed;
and the electric connecting column is filled in the through hole and is connected with the seed layer and the rewiring layer.
As a preferred scheme of the embedded multi-chip and component SIP fan-out type packaging structure, the packaging structure further comprises a solder mask layer, and the solder mask layer covers the graphical holes and the non-pad area of the rewiring layer.
As a preferred scheme of the embedded multi-chip and element SIP fan-out type packaging structure, the packaging structure further comprises a plurality of second chips or second passive elements which are positioned on one side, away from the plastic packaging layer, of the solder mask layer, the metal bumps comprise first metal bumps and second metal bumps, the size of each second metal bump is smaller than that of each first metal bump, and the second chips or the second passive elements are welded with the second metal bumps.
In another aspect, a method for manufacturing an embedded multi-chip and component SIP fan-out package structure is provided, which includes the following steps:
s10, manufacturing a plastic package layer by adopting a plastic package material, and forming a mounting hole on the plastic package layer;
s20, providing a plurality of first chips and a plurality of first passive elements, placing the first chips and the first passive elements in the mounting holes, and filling gaps among the first chips, the first passive elements and the mounting holes with a composite material formed by compounding filling resin and inorganic particles;
s30, manufacturing a rewiring layer, and leading out electric signals of the first chip and the first passive element to be electrically connected with the rewiring layer;
and S40, providing a metal bump, and welding the metal bump and the pad area of the redistribution layer.
As a preferred scheme of the manufacturing method of the embedded multi-chip and SIP fan-out package structure, step S10 specifically includes the following steps:
s10a, providing a carrier plate and temporary bonding glue, and attaching the temporary bonding glue to one side surface of the carrier plate along the thickness direction of the carrier plate;
s10b, providing a plastic package material, carrying out plastic package on one side surface of the carrier plate, which is pasted with the temporary bonding glue, and forming the plastic package layer after the plastic package material is solidified;
and S10c, forming mounting holes in the plastic packaging layer along the thickness direction of the plastic packaging layer.
As a preferred scheme of the manufacturing method of the embedded multi-chip and SIP fan-out package structure, step S20 specifically includes the following steps:
s20a, providing a plurality of first chips and a plurality of first passive elements, and pasting the front surfaces of the first chips and the first passive elements on the temporary bonding glue in the mounting holes;
s20b, providing a composite material formed by compounding epoxy resin and inorganic particles, filling the composite material into gaps among the first chip, the first passive element and the mounting hole, and forming a composite layer after the composite material is cured;
s20c, detaching the carrier plate and removing the temporary bonding glue.
As a preferred scheme of the manufacturing method of the embedded multi-chip and SIP fan-out package structure, step S30 specifically includes the following steps:
s30a, manufacturing a dielectric layer on the bonding surface of the plastic packaging layer;
s30b, forming a through hole at the position of the dielectric layer corresponding to the electric signal connection position of the first chip and the first passive element, and exposing the electric signal connection position of the first chip and the first passive element;
s30c, sputtering seed layers on the surface of the dielectric layer and the inner wall of the through hole;
s30d, forming an electric connecting column in the through hole through electroplating copper deposition, and forming a copper plating layer connected with the electric connecting column on the surface of the seed layer;
and S30e, carrying out patterning treatment on the copper plating layer and the seed layer, wherein the copper plating layer after the patterning treatment forms the rewiring layer.
As a preferred scheme of the manufacturing method of the embedded multi-chip and SIP fan-out package structure, step S40 specifically includes the following steps:
s40a, coating photosensitive ink on the rewiring layer, forming a solder mask layer after exposure, development and curing, and exposing a pad area of the rewiring layer;
s40b, providing a metal bump, and welding the metal bump to the pad area of the redistribution layer;
preferably, step S40 is followed by step S50: and providing a plurality of second chips or second passive elements, and welding the second chips or the second passive elements with part of the metal bumps.
The invention has the beneficial effects that:
(1) the composite material doped with inorganic particles is added at the mounting hole of the plastic sealing layer, so that the effect of resisting the warping and deformation of the plastic sealing plate is achieved;
(2) the first chip and the first passive element are coated in the composite material, and the doped inorganic particles can improve the heat dissipation efficiency of the first chip and the first passive element;
(3) under the condition of pre-plastic encapsulation, the integration degree of chip encapsulation can be increased, the integration of a microsystem can be realized under a smaller volume, the volume and the transmission distance of a heterogeneous integrated microsystem are further reduced, the encapsulation cost is reduced, and the transmission efficiency is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly described below. It is obvious that the drawings described below are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
Fig. 1 is a cross-sectional view of a board-level carrier according to an embodiment of the invention.
Fig. 2 is a cross-sectional view of an intermediate product obtained by attaching a temporary bonding paste to a carrier according to an embodiment of the present invention.
Fig. 3 is a cross-sectional view of an intermediate product obtained after a molding layer is formed on a carrier according to an embodiment of the invention.
Fig. 4 is a cross-sectional view of a plastic package layer with mounting holes according to an embodiment of the present invention.
Fig. 5 is a cross-sectional view of an intermediate product obtained by attaching the first chip and the first passive component in the mounting hole according to an embodiment of the invention.
Fig. 6 is a cross-sectional view of an intermediate product obtained after a composite layer is filled in a mounting hole according to an embodiment of the present invention.
Fig. 7 is a cross-sectional view of an intermediate product obtained after removing the carrier plate and the temporary bonding paste according to an embodiment of the present invention.
Fig. 8 is a cross-sectional view of an intermediate product after a dielectric layer is formed on a molding layer according to an embodiment of the invention.
Fig. 9 is a cross-sectional view of an intermediate product after a dielectric layer opening process according to an embodiment of the present invention.
Fig. 10 is a cross-sectional view of an intermediate product after a redistribution layer is formed on a dielectric layer according to an embodiment of the invention.
Fig. 11 is a cross-sectional view of an intermediate product after a solder mask is formed on a redistribution layer in accordance with an embodiment of the present invention.
Fig. 12 is a cross-sectional view of an intermediate product after a metal bump is soldered to a pad region of a redistribution layer according to an embodiment of the invention.
Fig. 13 is a cross-sectional view of a product obtained after a second chip or a second passive component is mounted according to an embodiment of the invention.
Fig. 14 is a top view of a board level package structure according to an embodiment of the invention.
Fig. 15 is a top view of a wafer level package structure according to another embodiment of the invention.
In the figure:
1. a carrier plate;
2. a temporary bonding glue;
3. a plastic packaging layer; 31. mounting holes;
41. a first chip; 42. a first passive element; 43. a second chip or a second passive element;
5. compounding layers;
6. a dielectric layer; 61. a through hole;
7. a rewiring layer;
8. a solder resist layer;
9. and a metal bump.
Detailed Description
The technical scheme of the invention is further explained by the specific implementation mode in combination with the attached drawings.
Wherein the showings are for the purpose of illustration only and are shown by way of illustration only and not in actual form, and are not to be construed as limiting the present patent; to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar components; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "inner", "outer", etc. are used for indicating the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not intended to indicate or imply that the device or passive component referred to must have a specific orientation, be constructed in a specific orientation and be operated, and therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and are not to be construed as limiting the present patent, and the specific meaning of the terms described above will be understood by those of ordinary skill in the art according to the specific circumstances.
In the description of the present invention, unless otherwise explicitly specified or limited, the term "connected" or the like, if appearing to indicate a connection relationship between the components, is to be understood broadly, for example, as being fixed or detachable or integral; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through one or more other components or may be in an interactive relationship with one another. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Unless otherwise specified, various raw materials used in the fabrication method of the embedded multi-chip and component SIP fan-out package structure of the present invention are commercially available or prepared according to conventional methods in the art.
As shown in fig. 13, an embodiment of the invention provides an embedded multi-chip and SIP fan-out package structure, including:
the plastic packaging layer 3 is provided with a mounting hole 31 along the thickness direction, and the plastic packaging layer 3 is provided with a first side surface and a second side surface along the thickness direction;
a plurality of first chips 41 and a plurality of first passive elements 42 located in the mounting hole 31, wherein the front surfaces of the first chips 41 and the first passive elements 42 face the first side surface, and a composite layer 5 is filled between the first chips 41, the first passive elements 42 and the side walls of the mounting hole 31, and the composite layer 5 comprises filling resin and inorganic particles uniformly distributed in the filling resin;
a rewiring layer 7 located on the first side of the plastic packaging layer 3 and electrically connected with the first chip 41 and the first passive element 42, wherein the rewiring layer 7 is provided with a pad area and a non-pad area;
and the metal bump 9 is welded with the pad area of the rewiring layer 7.
In this embodiment, the opening position of the mounting hole 31 may be disposed at the center of the plastic package layer 3, or at the edge of the plastic package layer 3, specifically according to the design requirement of the package structure.
As shown in fig. 13, two first chips 41 and a first passive element 42 are integrated in the mounting hole 31, and the two first chips 41 are located on two sides of the first passive element 42; the number and type of the first chip 41 and the first passive element 42 in this embodiment are not limited, and are determined according to the product requirements.
In the prior art, the plastic package structure is easy to warp due to the difference of thermal expansion coefficients among the chip, the passive element and the plastic package layer. In view of this, in the embodiment, the plastic package layer 3 is prepared in a pre-plastic package manner, then the plastic package layer 3 is subjected to a hole opening process, the first chip 41 and the first passive component 42 are mounted at the mounting hole 31, the composite layer 5 doped with inorganic particles is adopted to fix the first chip 41 and the first passive component 42 in the mounting hole 31, and the composite layer 5 doped with inorganic particles is adopted to fix the first chip 41 and the first passive component 42 in the mounting hole 31 of the plastic package layer 3, so that the thermal expansion coefficients among the first chip 41, the first passive component 42 and the plastic package layer 3 can be balanced, and the warpage and deformation phenomena occurring after the chip and the passive component are packaged can be effectively resisted; meanwhile, the composite layer 5 doped with inorganic particles covers the first chip 41 and the first passive element 42, and the inorganic particles in the composite layer 5 have a good heat dissipation effect on the first chip 41 and the first passive element 42; the first chip 41 and the first passive element 42 in this embodiment are mounted inside the plastic package layer 3, and compared with the existing chip mounted on the surface of the plastic package layer 3, the integration degree of chip packaging can be increased, the integration of the microsystem can be realized in a smaller volume, the volume and the transmission distance of the heterogeneous integrated microsystem are further reduced, the packaging cost is reduced, and the transmission efficiency is improved.
Optionally, the metal bump 9 is a solder, a silver solder, or a gold-tin alloy solder, the metal bump 9 of this embodiment is a metal ball structure, and the metal ball is soldered and implanted in the pad region to achieve electrical leading-out of the redistribution layer 7.
Alternatively, the inorganic particles in the present embodiment include silica, but are not limited thereto, and other inorganic particles capable of adjusting the thermal expansion coefficient of the filling resin are suitable and not listed one by one.
Optionally, the filling resin in this embodiment is an epoxy resin, and the epoxy resin includes polyimide and cyanate type epoxy resin, but is not limited thereto, and is suitable for other resin materials whose thermal expansion coefficient can be adjusted by doping the inorganic particles;
optionally, the Molding layer 3 is any one of polyimide, silicone, and EMC (Epoxy Molding Compound), and the embodiment is preferably EMC.
In this embodiment, the embedded multi-chip and component SIP fan-out package structure further includes:
a dielectric layer 6 located on the first side surface of the plastic package layer 3, and the dielectric layer 6 is provided with a through hole 61 exposing the electrical signal connection position of the first chip 41 and the first passive element 42;
a seed layer covering the dielectric layer 6 and the inner wall of the through hole 61, wherein the rewiring layer 7 is positioned on the seed layer, and the seed layer and the rewiring layer 7 are provided with graphical holes exposing parts of the dielectric layer 6; wherein the seed layer is not shown in the figure;
and the electric connecting column is filled in the through hole 61 and is connected with the seed layer and the rewiring layer 7.
The dielectric layer 6 is made of ABF (Ajinomoto Build-up Film) or PP (Polypropylene), and is attached to the plastic sealing layer 3 to perform an insulating function. In this embodiment, the dielectric layer 6 may be drilled by laser drilling to form a through hole 61 exposing the electrical signal connection portion of the first chip 41 and the first passive element 42, and a seed layer is sputtered on the inner wall of the through hole 61 and the surface of the dielectric layer 6, followed by copper plating to form an electrical connection post (copper post) in the through hole 61, so that the electrical signals of the first chip 41 and the first passive element 42 are connected to the redistribution layer 7 through the copper post.
Further, the seed layer comprises a titanium metal layer on the side of the dielectric layer 6 remote from the carrier plate 1 and a copper metal layer on the titanium metal layer. The titanium metal layer has high adhesion, excellent conductivity and uniform thickness, and the copper metal layer can be stably adhered to the dielectric layer 6 through the titanium metal layer.
Of course, the seed layer in this embodiment is not limited to a two-layer structure (titanium metal layer, copper metal layer), and may have a single-layer structure, a two-layer structure, or a multilayer structure having two or more layers. The material of the seed layer is not limited to the stacked combination of two single metal materials, and may also be a single metal material or an alloy material, so that the redistribution layer 7 can be stably attached to the package structure, which is not described in detail.
The embedded multi-chip and component SIP fan-out package structure of the embodiment further comprises a solder mask layer 8, and the solder mask layer 8 covers the non-solder-pad area of the graphical hole and the rewiring layer 7. The solder mask layer 8 is a photosensitive ink layer. Photosensitive ink is used as the solder mask layer 8, so that the function of the rewiring layer 7 can be achieved, part of the seed layer can be removed through exposure, development and etching, and the process is simplified.
Further, the embedded multi-chip and component SIP fan-out package structure of the embodiment further includes a plurality of second chips or second passive components 43 located on a side of the solder mask layer 8 away from the molding layer 3, the metal bumps 9 include first metal bumps and second metal bumps smaller than the first metal bumps, and the second chips or second passive components 43 are soldered to the second metal bumps. By mounting a second chip or a second passive component 43 of a different kind from the first chip 41 and the first passive component 42, more components with different functions can be integrated in a small space, and the integration degree of the components is further improved.
Optionally, the redistribution layer 7 is one or more layers, that is, the redistribution layer 7 may be designed to be a multilayer structure with one layer, two layers, or more than two layers according to product requirements.
The embodiment of the invention also provides a manufacturing method of the embedded multi-chip and element SIP fan-out type packaging structure, which comprises the following steps:
s10, referring to fig. 1 to 4, manufacturing the plastic package layer 3 by using a plastic package material, and forming the mounting hole 31 on the plastic package layer 3;
s20, providing a plurality of first chips 41 and a plurality of first passive elements 42, placing the first chips 41 and the first passive elements 42 in the mounting holes 31, and filling gaps among the first chips 41, the first passive elements 42 and the mounting holes 31 with a composite material compounded by filling resin and inorganic particles;
s30, forming the redistribution layer 7, and electrically connecting the electrical signal extraction of the first chip 41 and the first passive element 42 to the redistribution layer 7;
and S40, providing the metal bump 9, and welding the metal bump 9 with the pad area of the redistribution layer 7.
In the embodiment, the plastic package layer 3 is manufactured in a pre-plastic package mode, then the plastic package layer 3 is subjected to hole opening processing to form the mounting hole 31, the first chip 41 and the first passive element 42 are filled and fixed in the mounting hole 31 through the composite material doped with inorganic particles, so that warping and deformation generated after the component is packaged can be effectively resisted, the heat dissipation efficiency of the component (the first chip 41 and the first passive element 42) can be improved, the integration degree of the component packaging can be increased, and the integration of a micro system can be realized under a smaller volume.
Further, step S10 specifically includes the following steps:
s10a, providing a carrier board 1 (fig. 1) and a temporary bonding glue 2, and attaching the temporary bonding glue 2 to a side surface of the carrier board 1 along the thickness direction thereof, referring to fig. 2;
s10b, providing a plastic package material, performing plastic package on a side surface of the carrier plate 1 to which the temporary bonding glue 2 is attached, and forming a plastic package layer 3 after the plastic package material is cured, referring to fig. 3;
s10c, mounting holes 31 are opened in the plastic package layer 3 along the thickness direction thereof, refer to fig. 4.
The carrier plate 1 is a plate-level carrier plate, the carrier plate 1 is made of stainless steel, glass or an organic substrate, and after the plastic package layer 3 is provided with the mounting hole 31, part of the temporary bonding glue 2 is exposed, so that the subsequent fast and stable mounting of the first chip 41 and the first passive element 42 is facilitated.
Further, step S20 specifically includes the following steps:
s20a, carrying out multi-chip and multi-element heterogeneous integration layout; specifically, a plurality of first chips 41 and a plurality of first passive elements 42 are provided, the first chips 41 and the first passive elements 42 are pasted on the temporary bonding glue 2 in the mounting holes 31 at the front sides, and referring to fig. 5, two different types of first chips 41 and one type of first passive element 42 are provided; in actual mounting, the number and types of the first chip 41 and the first passive component 42 can be designed according to actual requirements, and are not limited.
S20b, providing a composite material formed by compounding epoxy resin and inorganic particles, filling the composite material in the gaps among the first chip 41, the first passive element 42 and the mounting hole 31, and forming a composite layer 5 after the composite material is cured, referring to fig. 6; the thermal expansion coefficient of the epoxy resin can be adjusted based on inorganic particles, the composite material is applied to the mounting hole 31 of the plastic package layer 3, gaps among the first chip 41, the first passive element 42 and the inner wall of the mounting hole 31 are filled, the thermal expansion coefficients among the first chip 41, the first passive element 42 and the plastic package layer 3 can be effectively balanced, the warping amount of a product after the carrier plate 1 is removed can be effectively reduced after the composite material is cured, and the warping and deformation of a packaging structure are further reduced;
in this embodiment, the inorganic particles include silica, but are not limited thereto, and other inorganic particles capable of adjusting the thermal expansion coefficient of the epoxy resin are suitable and not illustrated herein; the epoxy resin is polyimide or cyanate type epoxy resin, but not limited thereto, and is suitable for other resin materials whose thermal expansion coefficient can be adjusted by doping the inorganic particles; the doping amount of the inorganic particles depends on the type of chip and passive components to be packaged actually.
S20c, removing the carrier board 1 and removing the temporary bonding glue 2, referring to fig. 7.
Further, step S30 specifically includes the following steps:
s30a, fabricating a dielectric layer 6 on the bonding surface (the side surface attached to the carrier 1 by the temporary bonding glue 2) of the plastic package layer 3, referring to fig. 8; specifically, the dielectric layer 6 is made of ABF (Ajinomoto Build-up Film) or PP (Polypropylene), but not limited thereto, the dielectric layer 6 is attached to the molding compound layer 3 to play an insulating role;
s30b, forming a through hole 61 in the dielectric layer 6 at a position corresponding to the electrical signal connection between the first chip 41 and the first passive element 42, so as to expose the electrical signal connection between the first chip 41 and the first passive element 42, as shown in fig. 9;
s30c, sputtering a seed layer on the surface of the dielectric layer 6 and the inner wall of the through hole 61, wherein the seed layer is not shown in the figure;
s30d, forming an electric connecting column in the through hole 61 through electroplating copper deposition and forming a copper plating layer connected with the electric connecting column on the surface of the seed layer;
s30e, performing a patterning process on the copper plating layer and the seed layer, where the copper plating layer after the patterning process forms a redistribution layer 7, referring to fig. 10;
in this embodiment, the method for manufacturing the redistribution layer 7 belongs to the prior art, and any one of a semi-additive method, an additive method, a subtractive method, and a semiconductor manufacturing method may be specifically used, which is not specifically limited, and is not described herein again.
Further, step S40 specifically includes the following steps:
s40a, coating photosensitive ink on the redistribution layer 7, exposing, developing, and curing to form a solder mask 8, and exposing the pad area of the redistribution layer 7, referring to fig. 11;
s40b, providing the metal bump 9, and soldering the metal bump 9 to the pad region of the redistribution layer 7, referring to fig. 12.
Further, as shown in fig. 13, the step S40 is followed by a step S50: a plurality of second chips or second passive elements 43 are provided, and the second chips or second passive elements 43 are welded with part of the metal bumps 9. The size of the metal bump 9 bonded to the second chip or the second passive element 43 is smaller than the other metal bumps 9.
The embedded multi-chip and component SIP fan-out package structure manufactured by the manufacturing method of the present embodiment is a board level package structure, and a top view thereof is shown in fig. 14.
In another embodiment of the present invention, the embedded multi-chip and component SIP fan-out package manufactured using the wafer-level carrier is a wafer-level package, and the top view thereof is shown in FIG. 15. The wafer level package structure and the manufacturing method thereof are substantially the same as those of the above embodiments, except that the carrier 1 is a wafer level carrier, which is not described in detail.
Compared with the prior art, the embedded multi-chip and element SIP fan-out type packaging structure and the manufacturing method thereof have the following advantages:
(1) the composite material doped with inorganic particles is added at the mounting hole of the plastic sealing layer, so that the effect of resisting the warping and deformation of the plastic sealing plate is achieved;
(2) the first chip and the first passive element are coated in the composite material, and the doped inorganic particles can improve the heat dissipation efficiency of the first chip and the first passive element;
(3) under the condition of pre-plastic encapsulation, the integration degree of chip encapsulation can be increased, the integration of a microsystem can be realized under a smaller volume, the volume and the transmission distance of a heterogeneous integrated microsystem are further reduced, the encapsulation cost is reduced, and the transmission efficiency is improved.
It should be understood that the above-described embodiments are merely preferred embodiments of the invention and the technical principles applied thereto. It will be understood by those skilled in the art that various modifications, equivalents, changes, and the like can be made to the present invention. However, such variations are within the scope of the invention as long as they do not depart from the spirit of the invention. In addition, certain terms used in the specification and claims of the present application are not limiting, but are used merely for convenience of description.
Claims (10)
1. The utility model provides an embedded multicore piece and component SIP fan-out type packaging structure which characterized in that includes:
the plastic packaging layer is provided with a mounting hole along the thickness direction and is provided with a first side surface and a second side surface along the thickness direction;
the first chips and the first passive elements are positioned in the mounting holes, the front surfaces of the first chips and the first passive elements face the first side surface, and composite layers are filled among the first chips, the first passive elements and the side walls of the mounting holes and comprise filling resin and inorganic particles uniformly distributed in the filling resin;
the rewiring layer is positioned on the first side face of the plastic packaging layer and is electrically connected with the first chip and the first passive element, and the rewiring layer is provided with a bonding pad area and a non-bonding pad area;
and the metal bump is welded with the bonding pad area of the redistribution layer.
2. The embedded multi-chip and component SIP fan-out package structure of claim 1, wherein the filling resin is an epoxy resin; the plastic packaging layer is EMC.
3. The embedded multi-chip and component SIP fan-out package structure of claim 1, further comprising:
the dielectric layer is positioned on the first side surface of the plastic packaging layer, and a through hole for exposing the electric signal connection part of the first chip and the first passive element is formed in the dielectric layer;
the seed layer covers the dielectric layer and the inner wall of the through hole, the rewiring layer is positioned on the seed layer, and the seed layer and the rewiring layer are provided with graphical holes which enable parts of the dielectric layer to be exposed;
and the electric connecting column is filled in the through hole and is connected with the seed layer and the rewiring layer.
4. The embedded multi-chip and component SIP fan-out package structure of claim 3, further comprising a solder resist layer covering the patterned holes and non-pad areas of the redistribution layer.
5. The embedded multi-chip and component SIP fan-out package structure of claim 4, further comprising a plurality of second chips or second passive components located on a side of the solder mask layer away from the molding layer, wherein the metal bumps comprise first metal bumps and second metal bumps having a smaller size than the first metal bumps, and the second chips or second passive components are soldered to the second metal bumps.
6. A manufacturing method of an embedded multi-chip and element SIP fan-out type packaging structure is characterized by comprising the following steps:
s10, manufacturing a plastic package layer by adopting a plastic package material, and forming a mounting hole on the plastic package layer;
s20, providing a plurality of first chips and a plurality of first passive elements, placing the first chips and the first passive elements in the mounting holes, and filling gaps among the first chips, the first passive elements and the mounting holes with a composite material formed by compounding filling resin and inorganic particles;
s30, manufacturing a rewiring layer, and leading out electric signals of the first chip and the first passive element to be electrically connected with the rewiring layer;
and S40, providing a metal bump, and welding the metal bump and the pad area of the redistribution layer.
7. The method of claim 6, wherein step S10 comprises the steps of:
s10a, providing a carrier plate and temporary bonding glue, and attaching the temporary bonding glue to one side surface of the carrier plate along the thickness direction of the carrier plate;
s10b, providing a plastic package material, carrying out plastic package on one side surface of the carrier plate, which is pasted with the temporary bonding glue, and forming the plastic package layer after the plastic package material is solidified;
and S10c, forming mounting holes in the plastic packaging layer along the thickness direction of the plastic packaging layer.
8. The method of claim 7, wherein step S20 comprises the steps of:
s20a, providing a plurality of first chips and a plurality of first passive elements, and pasting the front surfaces of the first chips and the first passive elements on the temporary bonding glue in the mounting holes;
s20b, providing a composite material formed by compounding epoxy resin and inorganic particles, filling the composite material into gaps among the first chip, the first passive element and the mounting hole, and forming a composite layer after the composite material is cured;
s20c, detaching the carrier plate and removing the temporary bonding glue.
9. The method of claim 8, wherein step S30 comprises the steps of:
s30a, manufacturing a dielectric layer on the bonding surface of the plastic packaging layer;
s30b, forming a through hole at the position of the dielectric layer corresponding to the electric signal connection position of the first chip and the first passive element, and exposing the electric signal connection position of the first chip and the first passive element;
s30c, sputtering seed layers on the surface of the dielectric layer and the inner wall of the through hole;
s30d, forming an electric connecting column in the through hole through electroplating copper deposition, and forming a copper plating layer connected with the electric connecting column on the surface of the seed layer;
and S30e, carrying out patterning treatment on the copper plating layer and the seed layer, wherein the copper plating layer after the patterning treatment forms the rewiring layer.
10. The method of claim 9, wherein step S40 comprises the steps of:
s40a, coating photosensitive ink on the rewiring layer, forming a solder mask layer after exposure, development and curing, and exposing a pad area of the rewiring layer;
s40b, providing a metal bump, and welding the metal bump to the pad area of the redistribution layer;
preferably, step S40 is followed by step S50: and providing a plurality of second chips or second passive elements, and welding the second chips or the second passive elements with part of the metal bumps.
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111403302A (en) * | 2020-03-27 | 2020-07-10 | 深圳杰微芯片科技有限公司 | Embedded chip packaging method |
| CN111430322A (en) * | 2020-03-05 | 2020-07-17 | 广东工业大学 | System-level fan-out packaging structure and packaging method |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0546069U (en) * | 1991-11-21 | 1993-06-18 | 日本無線株式会社 | High-density mounting circuit board |
| CN1543291A (en) * | 2003-02-18 | 2004-11-03 | ���µ�����ҵ��ʽ���� | Electronic component built-in module and method of manufacturing the same |
| CN103227164A (en) * | 2013-03-21 | 2013-07-31 | 日月光半导体制造股份有限公司 | Semiconductor package structure and manufacturing method thereof |
| CN108711569A (en) * | 2018-08-10 | 2018-10-26 | 付伟 | With the multichip packaging structure and preparation method thereof for accommodating filter chip chamber |
| CN210575899U (en) * | 2019-10-12 | 2020-05-19 | 广东佛智芯微电子技术研究有限公司 | Embedded multi-chip and element SIP fan-out type packaging structure |
-
2019
- 2019-10-12 CN CN201910968164.6A patent/CN110600438A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0546069U (en) * | 1991-11-21 | 1993-06-18 | 日本無線株式会社 | High-density mounting circuit board |
| CN1543291A (en) * | 2003-02-18 | 2004-11-03 | ���µ�����ҵ��ʽ���� | Electronic component built-in module and method of manufacturing the same |
| CN103227164A (en) * | 2013-03-21 | 2013-07-31 | 日月光半导体制造股份有限公司 | Semiconductor package structure and manufacturing method thereof |
| CN108711569A (en) * | 2018-08-10 | 2018-10-26 | 付伟 | With the multichip packaging structure and preparation method thereof for accommodating filter chip chamber |
| CN210575899U (en) * | 2019-10-12 | 2020-05-19 | 广东佛智芯微电子技术研究有限公司 | Embedded multi-chip and element SIP fan-out type packaging structure |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111430322A (en) * | 2020-03-05 | 2020-07-17 | 广东工业大学 | System-level fan-out packaging structure and packaging method |
| CN111403302A (en) * | 2020-03-27 | 2020-07-10 | 深圳杰微芯片科技有限公司 | Embedded chip packaging method |
| WO2021208961A1 (en) * | 2020-04-17 | 2021-10-21 | 江苏长电科技股份有限公司 | Fan-out packaging structure |
| CN113539978A (en) * | 2020-04-17 | 2021-10-22 | 江苏长电科技股份有限公司 | Fan-out packaging structure |
| CN113539978B (en) * | 2020-04-17 | 2023-11-10 | 江苏长电科技股份有限公司 | Fan-out packaging structure |
| CN111725153A (en) * | 2020-06-16 | 2020-09-29 | 杰群电子科技（东莞）有限公司 | Substrate-free system-in-package structure, method and electronic product |
| CN112466857A (en) * | 2021-01-28 | 2021-03-09 | 广东佛智芯微电子技术研究有限公司 | Chip packaging method based on light-transmitting plate and packaging structure thereof |
| CN113675166A (en) * | 2021-09-18 | 2021-11-19 | 江苏芯德半导体科技有限公司 | Passive element for fan-out type packaging, preparation method thereof and fan-out type packaging method |
| CN113991004A (en) * | 2021-10-26 | 2022-01-28 | 东莞市中麒光电技术有限公司 | LED substrate manufacturing method, LED substrate, LED device manufacturing method and LED device |
| WO2024016525A1 (en) * | 2022-07-21 | 2024-01-25 | 深南电路股份有限公司 | Bottom package and fabrication method therefor, and package on package structure and fabrication method therefor |
| CN116864494A (en) * | 2023-09-01 | 2023-10-10 | 甬矽电子(宁波)股份有限公司 | Fan-out type packaging structure and manufacturing method thereof |
| CN116864494B (en) * | 2023-09-01 | 2023-12-05 | 甬矽电子(宁波)股份有限公司 | Fan-out type packaging structure and manufacturing method thereof |
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Effective date of registration: 20230322 Address after: Room A107, scientific research building, block a, neifo high tech think tank center, Nanhai Software Science Park, Shishan town, Nanhai District, Foshan City, Guangdong Province, 528225 Applicant after: Guangdong fozhixin microelectronics technology research Co.,Ltd. Address before: Room A107, scientific research building, block a, neifo high tech think tank center, Nanhai Software Science Park, Shishan town, Nanhai District, Foshan City, Guangdong Province, 528225 Applicant before: Guangdong fozhixin microelectronics technology research Co.,Ltd. Applicant before: Guangdong Xinhua Microelectronics Technology Co.,Ltd. |