TWI465163B - Method of making cavity substrate with built-in stiffener and cavity substrate manufactured thereby - Google Patents

Description

Pocket substrate with built-in reinforcing layer and manufacturing method thereof

The invention relates to a method for manufacturing a cavity substrate and a cavity substrate manufactured thereby; and more particularly to a method for manufacturing a cavity substrate and a cavity substrate manufactured by the same, wherein the cavity substrate comprises a bump/flange layer The sacrificial carrier defines a recess and exposes an electrical pad from the recess.

In recent years, the trend of electronic devices, such as mobile Internet devices (MIDs), multimedia devices, and notebook notebooks, has been designed to be faster and lighter. In the frequency band of the general signal, the shorter the circuit path, the better the signal integrity. Therefore, in order to promote the signal conduction characteristics of the electronic device, it is necessary to reduce the size of the interlayer connection region, such as the diameter of the micropores and the covered perforations (PTH) in the substrate. Generally, the coated perforations in the core-clad copper foil laminate are formed by a mechanical CNC drilling machine, and the diameter of the coated perforations is required to increase the wire density, which is often severely technically limited and expensive. Therefore, the coreless substrate used to package the substrate allows the device to have a thinner, lighter, and faster design. However, since the coreless board does not have a core layer that provides the required flexural rigidity, the coreless board is more suitable under hot pressing than the conventional board having the core layer. It is susceptible to bending deformation problems.

U.S. Patent No. 7,164,198 to Nakamura et al., U.S. Patent No. 7,400,035 to Abe et al., U.S. Patent No. 7,582,961 to Chia et al., and U.S. Patent No. 7,934,313, the entire disclosure of which is incorporated herein by reference. A package substrate formed by etching a portion of a metal plate on which a build-up circuit is formed. The built-in reinforcement layer defines a recess as an area to which the semiconductor component is attached. In this regard, although the creation of a support platform can solve the problem of bending deformation, etching a thick metal block is too laborious, has a low yield, and may have many problems of yield reduction, such as the boundary line being difficult to control due to over-etching.

A method of forming a built-in reinforcement layer using a support substrate formed on a build-up circuit is disclosed in U.S. Patent No. 8,108,993 to Higashi et al. In this regard, the provision of the separation promoting layer on the support substrate allows the layer to be separated from the self-supporting substrate after completion of the coreless circuit board. Since the promoting separation layer, whether it is a thermosetting resin or an oxide film, has a peeling property under heat or light treatment, according to which there is a high risk of early delamination in coating and curing the dielectric layer, thereby possibly Lead to serious yield and reliability issues.

Looking at the various development states and limitations of coreless substrates that can be used today for high I/O and high performance semiconductor devices, there is a need for a package board that provides excellent signal integrity and maintains low bending distortion during assembly and operation. Degree, and low preparation costs.

The invention provides a method for manufacturing a cavity substrate, the concave The hole substrate comprises a built-in reinforcement layer and a coreless build-up circuit, wherein the electrical pads are exposed by the recesses. The method for manufacturing a cavity substrate can include: providing a support plate including a sacrificial carrier, a reinforcement layer, an adhesive layer, and one or more electrical pads; wherein (i) the sacrificial carrier comprises a bump and a flange layer, (ii) the bump is adjacent to the flange layer and integrally formed with the flange layer, and extends from the flange layer toward a first vertical direction, (iii) the flange a layer extending laterally from the bump toward a side direction perpendicular to the first vertical direction, (iv) the reinforcing layer is attached to the sacrificial carrier via the adhesive layer, the adhesive layer being disposed on the reinforcing layer and the convex layer Between the edge layers and between the reinforcement layer and the bump, and (v) the electrical pad extends outside the bump in the first vertical direction, and the bump is opposite to the first vertical direction a second vertical direction covering the electrical pad; forming a coreless build-up circuit covering the electrical pad, the bump and the reinforcing layer in the first vertical direction, and the coreless circuit Electrically connecting with the electrical pad; and removing the bump to form a recess and exposing the electrical connection from a closed end of the recess a portion of the pad and the coreless build-up circuit, wherein the adhesive layer laterally covers and surrounds the recess, and the recess faces the second vertical direction.

The step of providing the support plate may include: providing the sacrificial carrier plate including the bump and the flange layer; disposed between the reinforcement layer and the flange layer, and between the reinforcement layer and the bump The adhesive layer is attached to the sacrificial carrier, the step comprising aligning the bump with one of the through holes of the reinforcement layer; and before or after attaching the reinforcement layer to the sacrificial carrier via the adhesive layer The electrical pad is provided at the bump of the sacrificial carrier.

The coreless build-up circuit can include a dielectric layer, one or more blind vias, and one or more wires. Accordingly, the step of forming the coreless build-up circuit may include providing a dielectric layer covering the electrical pad, the bump and the reinforcement layer in the first vertical direction, and including one or more blinds a hole aligned with the electrical pad and selectively aligning the conductive layer of the reinforcing layer; and then providing one or more wires extending from the dielectric layer toward the first vertical direction and on the dielectric layer The upper side extends laterally and extends through the blind hole in the second vertical direction to the electrical pad and to the conductive layer of the reinforcing layer for grounding.

If additional signal routing is required, the coreless circuit can further include another dielectric layer, another blind via layer, and another conductor layer. For example, the coreless build-up circuit may further include a second dielectric layer, one or more second blind holes, and one or more second wires. Accordingly, the step of forming the coreless build-up circuit may further include: providing a second dielectric layer on the dielectric layer and the wire, extending from the dielectric layer and the wire toward the first vertical direction, and Having one or more second blind vias aligned with the wire; and providing one or more second wires on the second dielectric layer extending from the second dielectric layer toward the first vertical direction and The second dielectric layer extends laterally and extends through the second blind via the second vertical direction to the wire to electrically connect the wire to the second wire.

According to an aspect of the present invention, the step of providing the support plate and the coreless build-up circuit may include: providing the sacrificial carrier, wherein the sacrificial carrier has the electrical pad at the bump; And the adhesive layer between the reinforcing layer and the flange layer, and between the reinforcing layer and the bump, Attaching the reinforcement layer to the sacrificial carrier, the step of aligning the bump with the via of the reinforcement layer; and then providing the dielectric layer covering the electrical pad in the first vertical direction, a bump and the reinforcement layer; then forming a blind via in the dielectric layer, wherein the blind via is aligned with the electrical pad; and providing a wire extending from the dielectric layer toward the first vertical direction And extending laterally on the dielectric layer and extending through the blind via to the electrical pad in the second vertical direction.

According to another aspect of the present invention, the step of providing the support plate and the coreless build-up circuit may include: providing the sacrificial carrier; and then passing between the reinforcement layer and the flange layer, and the reinforcement layer and The adhesive layer between the bumps causes the reinforcing layer to adhere to the sacrificial carrier, the step comprising aligning the bump with the through hole of the reinforcing layer; and then providing the electrical pad at the bump And then providing the dielectric layer covering the electrical pad, the bump and the reinforcing layer in the first vertical direction; then forming a blind hole in the dielectric layer, wherein the blind hole is aligned with the An electrical pad; the wire is then provided extending from the dielectric layer toward the first vertical direction and laterally extending over the dielectric layer and extending through the blind via toward the second vertical direction.

According to still another aspect of the present invention, the step of providing the support plate and the coreless build-up circuit may include: providing the sacrificial carrier, wherein the sacrificial carrier has the electrical pad at the bump; Providing the adhesive layer between the reinforcing layer and the flange layer and between the reinforcing layer and the bump, attaching the reinforcing layer to the sacrificial carrier, and simultaneously laminating the dielectric layer to the bump On the electrical pad and the reinforcing layer, the step includes aligning the bump with the through hole of the reinforcing layer; and then forming the blind hole in the dielectric layer, The blind via is aligned with the electrical pad; the wire is then provided, extending from the dielectric layer toward the first vertical direction, and extending laterally on the dielectric layer, and facing the second vertical The direction extends through the blind hole to the electrical pad.

The step of attaching the reinforcement layer to the sacrificial carrier via the adhesive layer may include providing an uncured adhesive layer between the flange layer of the sacrificial carrier and the reinforcement layer (eg, uncured epoxy resin) The film includes: aligning the bump of the sacrificial carrier with the opening of the adhesive layer and the through hole of the reinforcing layer; and then flowing the adhesive layer into the through hole between the bump And a gap between the reinforcing layers; and curing the adhesive (for example, curing the uncured epoxy resin).

The step of attaching the reinforcing layer and simultaneously laminating the dielectric layer may include: providing the uncured adhesive layer, and the reinforcing layer disposed between the flange layer of the sacrificial carrier and the dielectric layer, the step comprising: The bump is aligned with an opening of the adhesive layer and the through hole of the reinforcing layer; then the adhesive layer flows into the through hole and is notched between the bump and the reinforcing layer; and the dielectric is imprinted And bonding the bonding layer to the bump, the electrical pad and the reinforcing layer; and then curing the adhesive and the dielectric layer.

The step of flowing the adhesive layer into the notch may include: applying heat to melt the adhesive layer; and pressing the sacrificial carrier and the reinforcing layer to press the bump in the first vertical direction in the through hole Moving, and applying pressure to the flanged layer and the melted adhesive layer between the reinforcing layers, wherein the pressure of the melted adhesive layer is caused to flow into the opening in the first vertical direction to be between the convex The gap between the block and the reinforcing layer.

The step of curing the adhesive layer may include: applying heat to cure the The melted adhesive layer thus mechanically adheres the reinforcing layer to the bump and the flange layer.

The step of providing the wire may include depositing on the dielectric layer a coating that extends through the blind via to the electrical pad and selectively extends to the conductive layer of the stiffener; the selected portion of the coating is then removed using an etch stop layer defining the trace.

The step of removing the bump may include a chemical etching process and may Performing at any step after providing the dielectric pad, the bump, and the dielectric layer of the reinforcement layer. Preferably, the bump is removed after all metal deposition steps are completed, such that the bump acts as a barrier to metal deposition onto the electrical pad. Depending on process performance, the bump can be removed simultaneously while patterning the coating. According to the method of manufacturing a cavity substrate of the present invention, the method may further include: providing a covered via extending through the adhesive layer and the reinforcement layer to electrically connect the two sides of the cavity substrate. Specifically, in the method of manufacturing a cavity substrate according to the present invention, the method may further include: providing a terminal and a covered via extending through the adhesive layer and the reinforcement layer to electrically connect the coreless buildup layer Circuit and the terminal.

The step of providing the coated perforation may include: forming a perforation, It extends through the adhesive layer and the reinforcement layer in the first and second vertical directions; and then provides a connection layer on the inner side wall of one of the perforations.

The covered layer can be provided during the formation of the coreless build-up circuit The vias are provided prior to forming the coreless build-up circuitry and after the reinforcement layer is attached to the sacrificial carrier. For example, the method of the present invention can include providing an inner contact pad extending from the reinforcing layer toward the first vertical direction; And providing the coated perforation extending through the adhesive layer and the reinforcement layer in the first and second perpendicular directions, and adjoining the inner contact pad after the reinforcement layer is attached to the sacrificial carrier; and then providing the dielectric a layer covering the electrical pad, the bump, the reinforcing layer and the inner contact pad in the first vertical direction; and then providing the wire extending from the dielectric layer toward the first vertical direction The dielectric layer extends laterally and extends through the blind via of the dielectric layer and the other blind via to the second vertical direction to the electrical pad and the inner contact pad. In this regard, the connection layer of the inner contact pad and the covered via may be simultaneously deposited, and the electrical connection may be provided after depositing the connection layer of the inner contact pad and the covered via and providing the dielectric layer. pad. Alternatively, the method of the present invention may include providing the dielectric layer covering the electrical pad, the bump and the reinforcing layer in the first vertical direction; and then providing the wire from the dielectric layer toward the a first vertical direction extending laterally on the dielectric layer and extending through the blind via the second vertical direction to the electrical pad; and providing the covered via to the first A second vertical direction extends through the adhesive layer, the reinforcement layer, and the one or more dielectric layers and abuts the wire or/and an additional wire. In this regard, the coated via may extend through the adhesive layer, the reinforcement layer, and the single dielectric layer in the first and second vertical directions, and the connection layer may be provided during the provision of the conductive via. Moreover, the covered perforations may extend through the flange layer, the adhesive layer, the reinforcement layer and the plurality of dielectric layers in the first and second perpendicular directions, and the covered perforations may be provided during the provision of an additional wire. The connection layer.

Accordingly, the coated via is extendable at a first end and electrically connected to one of the outer conductive layers of the coreless build-up circuit, and is extendable at a second end And electrically connected to the flange layer. Alternatively, the coated via is extendable at the first end and electrically connected to the conductive layer in one of the coreless build-up circuits. Or the coated via is extendable at the first end and electrically connected to an inner contact pad extending from the reinforcing layer toward the first vertical direction and held by the adhesive layer and the reinforcing layer and the flange layer distance. In either case, the coated perforations extend vertically through the adhesive layer and the reinforcement layer and are located on the electrically conductive path between the flange layer and the coreless build-up circuit.

According to an embodiment of the present invention, the coated perforation is provided The step of the coreless build-up circuit may include: forming the through hole extending through the adhesive layer and the reinforcement layer in the first and second vertical directions; and then providing the connection layer on the inner sidewall of the through hole; Providing the inner contact pad extending from the reinforcing layer toward the first vertical direction and adjoining the connecting layer; and then providing the dielectric layer covering the electrical pad, the bump in the first vertical direction The reinforcing layer and the inner contact pad; then forming the blind via and another blind via in the dielectric layer, wherein the blind via is aligned with the electrical pad, and the other blind via is aligned with the Inner contact pad; then providing the wire extending from the dielectric layer toward the first vertical direction and extending laterally on the dielectric layer and passing through the blind via and the other in the second vertical direction A blind hole extends to the electrical pad and the inner contact pad.

According to another embodiment of the present invention, the coated perforation is provided And the step of the coreless build-up circuit may include: providing the dielectric layer covering the electrical pad, the bump and the reinforcement layer in the first vertical direction; and then forming a blindness in the dielectric layer a hole, wherein the blind hole is aligned with the electrical pad; forming the through hole extending through the adhesive in the first and second vertical directions a layer, the reinforcement layer and the dielectric layer; providing the connection layer on the inner sidewall of the via; and providing the wire extending from the dielectric layer toward the first vertical direction and on the dielectric layer Extending laterally and extending through the blind hole toward the second vertical direction to the electrical pad.

The step of providing the terminal may include removing one of the flange layers Selected part. In other words, the terminal can be the remainder of one of the flange layers and abuts the coated perforations and extends from the adhesive layer in the second vertical direction. Depending on process performance, the terminal can be defined at the same time as the bump is removed. In other words, the step of removing the bumps can include simultaneously removing selected portions of the flange layer to define the terminals.

The step of providing the inner contact pad may include: at the bump, the An inner coating is deposited on the adhesive and the reinforcement layer in the first vertical direction; then a selected portion of the inner coating is removed to define the inner contact pad. After depositing the undercoat layer, the electrical pad can be provided on the undercoat layer on the bump.

The dielectric layers can be formed by various techniques and can be extended To the peripheral edge of the assembly, it includes film pressing, roller coating, spin coating, and spray deposition. The blind vias can be used to penetrate the dielectric layer by a variety of techniques including laser drilling, plasma etching, and lithography. The perforations can be formed by a variety of techniques including mechanical drilling, laser drilling, and plasma etching and lithography techniques with or without wet etching. The coating layer and the connecting layer can be deposited by various techniques to form a single layer or a multilayer structure including electroplating, electroless plating, evaporation, sputtering, and combinations thereof. The coating layers can be patterned by various techniques to define the wires, including wet etching and electrochemical etching. Engraved, laser assisted etching and combinations thereof.

The bump of the sacrificial carrier and the flange layer can be integrated with each other It can be molded and can be made of any material with excellent handleability and excellent removal. For example, the bump and the flange layer may be a single metal body or comprise a single metal body at the interface, and the single metal body may be copper, aluminum, nickel, iron, tin or alloys thereof. Furthermore, the bump and the flange layer can be formed by a mechanical stamping process. For example, the step of providing the sacrificial carrier having the bump and the flange layer can include mechanically stamping a metal plate. The sacrificial carrier may further include a stamping pocket in the bump, and the stamping pocket in the bump faces the second vertical direction, and the bump covers the stamping in the first vertical direction Pocket. The bump and the recess in the bump may be a stamped portion of the metal sheet, and the flange layer may be an unembossed portion of the metal sheet.

The protrusion may have a large diameter or size in the second vertical direction The diameter or size of the first vertical direction. For example, the bump may be in the form of a flat-topped cone or pyramid having a diameter or dimension that decreases from the flange layer in a first vertical direction. Accordingly, since the adhesive layer extends into the first vertical direction into the gap between the bump and the reinforcing layer, the thickness of the adhesive layer adjacent to the bump increases. The bump may also be a cylindrical shape having a fixed diameter. Accordingly, the adhesive layer can have a fixed thickness at the gap between the bump and the reinforcing layer.

The diameter or size of the entrance of the bump pocket may be larger than the recess The diameter or size of the bottom plate. For example, the stamping pocket may be in the form of a flat-topped cone or pyramid having a diameter or dimension that increases from its bottom plate toward its entrance along a second vertical direction. Alternatively, the stamping pocket can also be a fixed diameter circle Column shape. The entrance and bottom of the stamping pocket may also have a circumference of a circle, a square or a rectangle. The stamping pocket may also have a shape conforming to the bump and extend into the opening and the through hole and extend across the majority of the bump in the vertical and side directions.

As described above, the adhesion between the flange layer and the reinforcement layer The layer may flow into the through hole between the bump and the reinforcing layer. Accordingly, the adhesive layer can contact the bump, the flange layer and the reinforcing layer, extending laterally from the bump to a peripheral edge of the recess substrate, and having a first thickness adjacent to the flange layer (in the vertical direction) and adjacent to the bump having a second thickness different from the first thickness.

The sacrificial carrier can be completely removed. However, it is better to retain A selected portion of the flange layer acts as a support platform attached to one of the heat sinks. Furthermore, the flange layer can also be processed to introduce a terminal and electrically connected to the build-up circuit through the covered via, and can be used to ground or provide electrical connection to the next layer or another electronic component.

The electrical pad can be resisted during any removal of the bump Made of a stable material for etching. For example, in the case where the sacrificial carrier is made of copper, the electrical pad can be a gold pad. Alternatively, the support plate may further include a barrier layer between the electrical pad and the bump. For example, the sacrificial carrier may further include a barrier layer such as a Sn layer covering the bump in the first vertical direction, such that the electrical pad uses the same material as the bump. The barrier layer is formed to protect the electrical pad from etching during removal of the bump. The barrier layer can be made of any material that can be effectively removed without damaging the electrical pads. However, even if not mentioned The barrier layer or the electrical pad is not made of the above-described etch-resistant material, and the result of the electrical pad that is slightly etched during the removal of the bump is acceptable, and even better.

By the above method, the present invention can provide a cavity substrate, The utility model comprises a cavity, an adhesive layer, a reinforcing layer, an electrical pad and a coreless circuit, wherein (i) the cavity has a closed end in the first vertical direction, and a second vertical direction having an open end; (ii) the reinforcing layer comprising a through hole, wherein the recess extends into the through hole; (iii) the adhesive layer laterally covering, surrounding and conforming to the covering a sidewall of the recess extending laterally from the recess to a peripheral edge of the substrate and covering and contacting the reinforcing layer in the second vertical direction; (iv) the electrical pad from the recess The closed end extends toward the first vertical direction; and (V) the coreless build-up circuit covering the electrical pad, the closed end of the recess, and the adhesive layer in the first vertical direction, and The closed end of the recess is coplanar or higher than the electrical pad and electrically connected to the electrical pad.

The reinforcing layer may extend to a peripheral edge of the pocket substrate to provide mechanical support of the coreless build-up circuit and may be made of an organic material such as a copper foil laminate. The reinforcing layer may also be made of an inorganic material (such as alumina (Al ₂ O ₃ ), aluminum nitride (AlN), tantalum nitride (SiN), bismuth (Si), copper (Cu), aluminum (Al), stainless steel, etc.) production. Alternatively, the reinforcing layer may be a single layer structure or a multilayer structure such as a circuit board or a multilayer ceramic board or a laminate of a substrate and a conductive layer.

The adhesive layer may extend to a peripheral edge of the pocket substrate, and The mechanical stiffness of the cured adhesive layer can also provide mechanical support for the coreless build-up circuit. In addition, the adhesive layer may cover the plus in the second vertical direction a strong layer extending into the through hole of the reinforcing layer and being shaped to cover the side wall of the recess. Accordingly, the adhesive layer may have a first thickness at the side wall adjacent to the recess, and a second thickness different from the first thickness at the reinforcing layer in the second vertical direction. The adhesive layer may be selected from at least one selected from the group consisting of epoxy resin, bismaleimide-triazabenzene (BT), benzocyclobutene (BCB), ABF film (Ajinomoto build-up film), liquid crystal polymer. It is made of a material consisting of polyamidamine, poly(phenylene ether), poly(tetrafluoroethylene), aromatic aramide and glass fiber.

The cavity substrate provided by the present invention may further comprise: a terminal, Extending the second vertical direction outside the adhesive layer, and maintaining a distance from the coreless build-up circuit via the adhesive layer and the reinforcement layer; and a covered perforation extending through the adhesive layer and the reinforcement layer, The coreless build-up circuit and the terminal are electrically connected.

The coreless build-up circuit can be from the closed end, the electrical pad, The adhesive layer and the reinforcing layer extend toward the first vertical direction, and contact and cover the closed end, the electrical pad, the adhesive layer and the reinforcing layer in the first vertical direction. Furthermore, the coreless build-up circuit can include one or more interconnect pads defined from selected portions of the outer leads and electrically connected to the electrical pads and from a dielectric layer toward the first vertical The direction extends; and includes exposing the contact surface toward the first vertical direction to provide electrical connection to the next layer or another electronic component, such as a semiconductor wafer, a plastic package, or another semiconductor package. Similarly, the terminal may include an exposed contact surface toward the second vertical direction for another electrical connection to the next set of components or another electronic component. Therefore, the cavity substrate can include electrical connections to each other The electrical contacts are located on opposite surfaces facing in opposite vertical directions, so that the semiconductor package is a stackable stack.

The invention also provides a semiconductor assembly, wherein a semiconductor The component can extend into the recess defined by the adhesive layer and electrically interconnect the semiconductor component to the electrical pad in the recess using a plurality of bonding media (including gold or solder bumps or wire bonding). An underfill may optionally be used in the recess and a heat sink may be attached to the semiconductor component to enhance thermal performance.

Furthermore, the present invention further includes a three-dimensional stacked structure in which A plurality of stackable semiconductor packages are stacked with a plurality of connection media, each having a semiconductor component embedded in the recess. For example, the group can be vertically stacked in a face-to-back manner by using a solder ball between the terminals of the lower group and the connection pads of the upper group.

The semiconductor component can be a packaged or unpackaged semiconductor Wafer. For example, the semiconductor component can be a land grid array (LGA) package or a wafer level package (WLP) comprising a semiconductor wafer or a stack of wafers on an interposer. Alternatively, the semiconductor component can be a semiconductor wafer.

The group can be a first or second stage single crystal or polycrystalline device. For example, the group can be a first level package containing a single wafer or multiple wafers. Alternatively, the group may be a second level module comprising a single package or a plurality of packages, wherein each package may comprise a single wafer or multiple wafers.

Unless specifically described or used in the words "then" Or steps that must occur in sequence, the order of the above steps is not limited to the above Listed and can be changed or rearranged depending on the desired design.

The invention has several advantages. The support comprising a reinforcing layer The board provides a flat and stable platform for forming the coreless build-up circuitry to make the process easy to operate. The bump of the sacrificial carrier defines a recess space for the component that can be separated from the build-up circuit by etching, thereby ensuring high manufacturing yield and avoiding undesired peeling or delamination problems. Furthermore, there are many options for built-in reinforcements, from low thermal expansion coefficient (CTE) materials (such as ceramics) to high thermal conductivity materials (such as metal sheets) to low-cost materials (such as fiberglass epoxy), offering a variety of package designs. Way. Therefore, the semiconductor component can be placed in the recess without using a specific tool for it to achieve low profile and small factor requirements. The electrical connection between the semiconductor component and the build-up circuit can be successfully established through the precise electrical pads in the recess without the complexity of the displacement and bending deformation caused by the stacking which often causes the semiconductor package to fail. problem. The covered perforations provide vertical signal routing between the build-up circuitry and the terminals, thereby providing a recessed substrate having a stacking function.

The above and other features and advantages of the present invention will be further described hereinafter by way of various preferred embodiments.

10‧‧‧ sacrificial carrier

12,14‧‧‧ surface

16‧‧‧Bumps

17‧‧‧Electrical pads

18‧‧‧Flange layer

20,31‧‧‧ recesses

22,24‧‧‧Bend angle

26‧‧‧ tapered sidewall

28‧‧‧floor

30‧‧‧Adhesive layer

32,311,361‧‧‧ openings

33‧‧‧ Strengthening layer

34‧‧‧Substrate

36‧‧‧ Conductive layer

40‧‧‧through hole

42‧‧‧ gap

60‧‧‧First coating

61‧‧‧Second coating

62‧‧‧Connection layer

63‧‧‧Insulation filler

72, 73‧‧‧ semiconductor components

82‧‧‧ solder balls

100,200‧‧‧ pocket substrate

101,102‧‧‧support board

110, 120, 130‧‧ ‧ body

161‧‧‧Barrier layer

182‧‧‧ terminals

201,202‧‧‧ Coreless circuit

211‧‧‧First dielectric layer

221‧‧‧ first blind hole

231‧‧‧metal layer

241‧‧‧First wire

261‧‧‧Second dielectric layer

281‧‧‧ second blind hole

291‧‧‧second wire

301‧‧‧ solder mask

341,342‧‧‧Internal connection pad

362‧‧‧Inner pad

401‧‧‧Perforation

402‧‧‧Covered perforation

711‧‧‧ wafer

712‧‧‧Intermediary

T1‧‧‧first thickness

T2‧‧‧second thickness

D1, D2‧‧‧ distance

1A and 1B are cross-sectional views of a bump and a flange layer in accordance with an embodiment of the present invention.

1C and 1D are a plan view and a bottom view, respectively, of Fig. 1B.

2A and 2B are cross-sectional views showing an adhesive layer according to an embodiment of the present invention.

2C and 2D are a plan view and a bottom view, respectively, of Fig. 2B.

3A and 3B are cross-sectional views of a reinforcing layer including a substrate and a conductive layer in accordance with an embodiment of the present invention.

3C and 3D are a plan view and a bottom view, respectively, of Fig. 3B.

4A to 4G are cross-sectional views showing a method of fabricating a support plate according to an embodiment of the present invention.

5A to 5I are cross-sectional views showing a method of fabricating a cavity substrate according to an embodiment of the present invention, wherein the cavity substrate comprises a support plate, a coreless build-up circuit, and a coated via, the support plate having a recess defined by a self-adhesive layer. An electrical pad, and the coreless circuit is electrically connected to the electrical pad.

5J is a cross-sectional view of a semiconductor package in accordance with an embodiment of the present invention, in which a semiconductor element is packaged in a recess substrate.

5K is a cross-sectional view of a three-dimensional stacked structure including a stacked semiconductor package vertically stacked in a face-to-back manner, in accordance with an embodiment of the present invention.

6A to 6I are cross-sectional views showing a method of fabricating a cavity substrate according to another embodiment of the present invention, wherein the cavity substrate has a coated via connected to an inner conductive layer of the coreless build-up circuit.

7A to 7J are cross-sectional views showing a method of fabricating a cavity substrate according to still another embodiment of the present invention, wherein the cavity substrate has a coated via connected to an inner pad of the support plate.

The invention will be more apparent from the following detailed description of the preferred embodiments.

[Example 1]

1A and 1B show a bump and a bump according to an embodiment of the invention. A cross-sectional view of a method of manufacturing a sacrificial carrier of a rim layer, and FIGS. 1C and 1D are a plan view and a bottom view, respectively, of FIG. 1B.

1A is a cross-sectional view of a sacrificial carrier 10, which is a metal plate and includes opposing major surfaces 12 and 14. The illustrated sacrificial carrier 10 is a copper plate having a thickness of 200 microns. Copper has the advantages of flexibility and low cost. The sacrificial carrier 10 can be made from a variety of metals such as copper, aluminum, iron-nickel alloy 42, iron, nickel, silver, gold, tin, mixtures thereof, and alloys thereof.

1B, 1C, and 1D are a cross-sectional view, a plan view, and a bottom view, respectively, of the bump 16, the flange layer 18, and the recess 20 formed by the sacrificial carrier 10. The bumps 16 and the recesses 20 are mechanically stamped from the sacrificial carrier 10. Thus, the bumps 16 are portions of the sacrificial carrier 10 that are stamped, while the flange layer 18 is the portion of the sacrificial carrier 10 that is not stamped.

The bump 16 is adjacent to the flange layer 18 and integrally formed with the flange layer 18 and extends downward from the flange layer 18. The bumps 16 include bend corners 22 and 24, tapered sidewalls 26 and a bottom plate 28. The bending angles 22 and 24 are bent by the press work. The bend angle 22 abuts the flange layer 18 and the tapered sidewall 26, while the bend angle 24 abuts the tapered sidewall 26 and the bottom plate 28. The tapered side walls 26 extend outwardly in the upward direction, while the bottom plate 28 extends in a side direction (e.g., left and right) perpendicular to the upward and downward directions. Thus, the projections 16 are in the form of a flat-topped pyramid (similar to a frustum) having a diameter that decreases downwardly from the flange layer 18 toward the bottom plate 28, i.e., upwardly from the bottom plate 28 toward the flange layer 18. The height of the bumps 16 (relative to the flange layer 18) is 300 microns, the dimensions at the flange layer 18 are 10.5 mm x 8.5 mm, and the dimensions at the bottom plate 28 are 10.25 mm x 8.25 mm. In addition, the bumps 16 have no due to the stamping operation. The thickness of the rule. For example, the tapered side wall 26 elongated by stamping is thinner than the bottom plate 28. For ease of illustration, the bumps 16 have a uniform thickness in the figures.

The flat flange layer 18 extends from the side of the projection 16 in the side direction and has a thickness of 200 μm.

The stamping pocket 20 faces upwardly and extends into the bump 16 and is covered by the bump 16 from below. The pocket 20 is provided with an inlet at the flange layer 18. The shape of the stamping pocket 20 also conforms to the bump 16. Thus, the pocket 20 also has a flat-topped pyramid shape (like a frustum) having a diameter that decreases downwardly from the entrance of the flange layer 18 toward the bottom plate 28, i.e., from the bottom plate 28 toward the flange layer. The entrance of 18 is incremented upwards. Furthermore, the stamping pockets 20 extend across the majority of the bumps 16 in the vertical and side directions, and the stamping pockets 20 have a depth of 300 microns.

2A and 2B are cross-sectional views of an adhesive layer according to an embodiment of the present invention, and Figs. 2C and 2D are a plan view and a bottom view, respectively, of Fig. 2B.

2A is a cross-sectional view of the adhesive layer 30 in which the adhesive layer 30 is a B-stage uncured epoxy film which is an uncured and patterned sheet having a thickness of 150 microns.

Adhesive layer 30 can be a variety of dielectric films or films made from a variety of organic or inorganic electrical insulators. For example, the adhesive layer 30 may initially be a film in which a resin-type thermosetting epoxy resin is partially cured to a medium stage after being incorporated into a reinforcing material. The epoxy resin may be FR-4, but other epoxy resins such as polyfunctional and bismaleimide-triazabenzene (BT) resins may also be suitable. Cyanate esters, polyimine and polytetrafluoroethylene (PTFE) are also suitable for specific applications. The reinforcing material may be an electronic grade glass (E-glass) or other reinforcing material. Such as high-strength glass (S-glass), low-inducing rate glass (D-glass), quartz, kevlar aramid and paper. The reinforcing material can also be a woven fabric, a non-woven fabric or a non-directional microfiber. Fillers such as enamel (melt fused silica) can be added to the film to improve thermal conductivity, thermal shock resistance and thermal expansion matching. Commercially available prepregs can be utilized, such as the SPEEDBOARD C film from W. L. Gore & Associates of Oakley, Wisconsin, USA.

2B, 2C and 2D are adhesive layers having openings 32, respectively 30 cross-sectional view, top view and bottom view. The opening 32 is a window that penetrates the adhesive layer 30 and has a size of 10.55 mm x 8.55 mm. The opening 32 is formed by mechanically breaking the film, but may be fabricated by other techniques, such as laser cutting.

3A and 3B illustrate the manufacture of a reinforcement layer in accordance with an embodiment of the present invention A cross-sectional view of the method, and FIGS. 3C and 3D are a plan view and a bottom view, respectively, of FIG. 3B.

3A is a cross-sectional view of a reinforcing layer 33 including a substrate 34 and conductive layer 36. For example, the substrate 34 can be a glass-epoxy material having a thickness of 150 microns, in contact with the substrate 34 and extending over the substrate 34, and the conductive layer 36 laminated to the substrate 34 can be unpatterned and having a thickness of 30 microns. Copper plate.

3B, 3C and 3D are respectively reinforcing layers having through holes 40 33, cross-sectional view, top view and bottom view. The through hole 40 is a window that penetrates the reinforcing layer 33 and has a size of 10.55 mm × 8.55 mm. The vias 40 are formed by mechanically breaking through the substrate 34 and the conductive layer 36, but may be fabricated by other techniques, such as laser cutting with or without wet etching. Therefore, open The port 32 has the same size as the through hole 40. Further, the punch 32 having the same opening as the through hole 40 can be formed in the same manner on the same punch.

The substrate 34 is illustrated as a single layer dielectric structure, and the reinforcing layer 33 may be other electrical interconnects such as a multilayer printed circuit board or a multilayer ceramic board. Accordingly, the reinforcement layer 33 can comprise an inlaid circuit layer.

4A to 4G are cross-sectional views showing a method of fabricating a support plate according to an embodiment of the present invention. As shown in FIG. 4G, the support plate includes a sacrificial carrier 10, an adhesive layer 30, a reinforcing layer 33, and an electrical pad 17.

4A and 4B are in a state in which the pockets are inverted downward so that the adhesive layer 30 and the reinforcing layer 33 are placed on the flange layer 18 by gravity, while the structures in Figs. 4C to 5G still maintain the recesses downward. . Thereafter, the structures in Figs. 5H to 5I are again flipped to the recessed up state as shown in Figs. 1A to 1D. Therefore, the punching pocket 20 faces downward in FIGS. 4A to 5G, and faces upward in FIGS. 5H to 5I. Nevertheless, the relative orientation of the structure has not changed. Regardless of whether the structure is inverted, rotated or tilted, the stamping pockets 20 are always facing in the second vertical direction and are covered by the bumps 16 in the first vertical direction. Likewise, regardless of whether the structure is inverted, rotated or tilted, the bumps 16 extend outwardly of the reinforcing layer 33 in a second vertical direction and extend from the flange layer 18 in a first vertical direction. Thus, the first and second vertical directions are oriented relative to the structure, are always opposite each other, and are perpendicular to the aforementioned side direction.

4A is a cross-sectional view showing the structure in which the adhesive layer 30 is provided on the flange layer 18. The adhesive layer 30 is lowered onto the flange layer 18 such that the bumps 16 are inserted upwardly through the opening 32, and finally the adhesive layer 30 is contacted and positioned on the flange layer 18. Preferably, the bump 16 is inserted into the opening 32 and is aligned with the opening. 32 is located at a central position within the opening 32 without contacting the adhesive layer 30.

4B is a cross-sectional view showing the structure in which the reinforcing layer 33 is provided on the adhesive layer 30. The reinforcing layer 33 is lowered onto the adhesive layer 30 such that the bumps 16 are inserted upward into the through holes 40, and finally the reinforcing layer 33 is brought into contact with and positioned on the adhesive layer 30.

The bump 16 is aligned with the through hole 40 after being inserted (but not penetrating) through the through hole 40 and located at a central position within the through hole 40 without contacting the reinforcing layer 33. Therefore, the bump 16 and the reinforcing layer 33 have a notch 42 in the through hole 40. The notch 42 laterally surrounds the bump 16 while being surrounded laterally by the reinforcing layer 33. Further, the opening 32 and the through hole 40 are aligned with each other and have the same size.

At this time, the reinforcing layer 33 is disposed on and in contact with the adhesive layer 30 and extends over the adhesive layer 30. The bump 16 extends through the opening 32 and enters the through hole 40. The bump 16 is 30 micrometers lower than the top surface of the conductive layer 36, and is exposed outward through the through hole 40. The adhesive layer 30 contacts the flange layer 18 and the reinforcing layer 33 and is interposed therebetween, and the adhesive layer 30 contacts the substrate 34 but is kept at a distance from the conductive layer 36. At this stage, the adhesive layer 30 is still a film of B-stage uncured epoxy, while the gap 42 is air.

4C is a cross-sectional view showing the structure in which the adhesive layer 30 flows into the notch 42. The adhesive layer 30 flows into the notch 42 via application of heat and pressure. In this figure, the method of forcing the adhesive layer 30 into the notch 42 applies downward pressure to the conductive layer 36 and/or applies upward pressure to the flange layer 18, that is, the flange layer 18 is pressed against the reinforcing layer 33. Thereby, the adhesive layer 30 is pressed; at the same time, the adhesive layer 30 is also heated. The heated adhesive layer 30 can be formed under pressure and can be formed into any shape. Therefore, after the adhesive layer 30 between the flange layer 18 and the reinforcing layer 33 is pressed, its original shape is changed and it flows upward. Mouth 42. The flange layer 18 and the reinforcing layer 33 are continuously pressed toward each other until the adhesive layer 30 fills the notch 42. Further, the adhesive layer 30 is still located between the flange layer 18 and the reinforcing layer 33, and continuously fills the gap between the flange layer 18 and the reinforcing layer 33, and reduces the gap therebetween.

For example, the flange layer 18 and the conductive layer 36 can be disposed on A press machine is placed above and between the lower press table (not shown). In addition, an upper baffle and an upper buffer paper (not shown) may be interposed between the conductive layer 36 and the upper pressing table, and the lower baffle and the lower cushioning paper (not shown) are placed on the flange layer. 18 between the lower pressing table. The stacked body thus constructed is, in order from top to bottom, an upper pressing table, an upper baffle, an upper cushioning paper, a substrate 34, a conductive layer 36, an adhesive layer 30, a flange layer 18, a lower cushioning paper, a lower baffle plate, and a lower pressing plate. station. In addition, the stacking body can be positioned on the lower pressing table by means of a tool pin (not shown) extending upward from the lower pressing table and passing through a registration hole (not shown) of the flange layer 18.

Then, the upper and lower press tables are heated and pushed forward, thereby The adhesive layer 30 is heated and pressed. The baffle disperses the heat of the press table to apply heat evenly to the flange layer 18 and the reinforcing layer 33 or even the adhesive layer 30. The cushioning paper disperses the pressure of the platen so that the pressure is uniformly applied to the flange layer 18 and the reinforcing layer 33 or even the adhesive layer 30. Initially, the reinforcing layer 33 contacts and is pressed down onto the adhesive layer 30. As the platen continues to move and continues to heat, the adhesive layer 30 between the flange layer 18 and the reinforcing layer 33 is squeezed and begins to melt, thereby flowing upward into the notch 42 and after reaching the substrate 34 to reach the conductive layer 36. For example, after the uncured epoxy resin is melted by heat, it is pressed into the notch 42 by pressure, but the reinforcing material and the filler remain between the flange layer 18 and the reinforcing layer 33. The adhesive layer 30 rises faster in the through hole 40 than the bump 16 and ends up filling the gap 42. Adhesive The layer 30 also rises slightly above the through hole 40 and overflows to the top surface of the bump 16 and the top surface of the conductive layer 36 before the platen stops operating. This may occur if the film thickness is slightly larger than the actual required thickness. As a result, the adhesive layer 30 forms a thin layer of cover on the top surface of the bump 16 and the top surface of the conductive layer 36. The pressing table stops after touching the bumps 16, but continues to heat the adhesive layer 30.

The direction in which the adhesive layer 30 flows upward in the notch 42 is as shown in the figure. As indicated by the upward bold arrow, the bump 16 and the flange layer 18 are moved relative to the reinforcing layer 33 as indicated by the upwardly fine arrow, and the reinforcing layer 33 is moved downward relative to the bump 16 and the flange layer 18. As indicated by the fine arrow down.

4D is a cross-sectional view showing the structure in which the adhesive layer 30 has been cured.

For example, after the platen stops moving, the bump 16 and the flange layer 18 are continuously clamped and heated, thereby converting the melted and uncured B-stage epoxy resin into the C-stage (C- Stage) An epoxy resin that cures or hardens. Therefore, the epoxy resin is cured in a manner similar to conventional lamination. After the epoxy resin is cured, the platen is separated to remove the structure from the press.

The cured adhesive layer 30 provides a strong mechanical bond between the bumps 16 and the reinforcement layer 33 and between the flange layer 18 and the reinforcement layer 33. The adhesive layer 30 can withstand normal operating pressure without deformation and damage, and is only temporarily distorted when excessive pressure is applied. Furthermore, the adhesive layer 30 can absorb the misalignment between the bumps 16 and the reinforcing layer 33 and between the flange layer 18 and the reinforcing layer 33 due to thermal expansion.

At this stage, the bumps 16 are substantially coplanar with the conductive layer 36, and the adhesive layer 30 and the conductive layer 36 extend to the top surface of the face up direction. For example, the thickness of the adhesive layer 30 between the flange layer 18 and the reinforcing layer 33 is 120 micro. The meter is reduced by 30 microns from its initial thickness of 150 microns; that is, the bump 16 is raised by 30 microns in the via 40 and the substrate 34 is lowered by 30 microns relative to the bump 16. The height of the 300 micron bumps 16 is substantially equivalent to the combined height of the conductive layer 36 (30 microns), the substrate 34 (150 microns) and the underlying adhesive layer 30 (120 microns). In addition, the bump 16 is still located at a central position within the opening 32 and the through hole 40 and at a distance from the reinforcing layer 33, and the adhesive layer 30 fills the space between the flange layer 18 and the reinforcing layer 33 and fills the notch 42. Adhesive layer 30 extends across reinforcement layer 33 within notch 42. In other words, the adhesive layer 30 in the notch 42 extends toward the upper and lower directions and spans the thickness of the reinforcing layer 33 of the outer side wall of the notch 42. The adhesive layer 30 also includes a thin top portion over the indentation 42 that contacts the top surface of the bump 16 and the top surface of the conductive layer 36 and extends 10 microns above the bump 16.

4E is a cross-sectional view showing the structure after polishing the removal of the bump 16, the adhesive layer 30, and the top of the conductive layer 36. For example, the top of the structure is treated with a rotating diamond wheel and distilled water. Initially, the diamond wheel only grinds the adhesive layer 30. When the grinding is continued, the adhesive layer 30 is thinned by the worn surface being moved downward. Finally, the diamond wheel will contact the bump 16 and the conductive layer 36 (not necessarily simultaneously), thus beginning to polish the bump 16 and the conductive layer 36. After continuous grinding, the bumps 16, the adhesive layer 30, and the conductive layer 36 are all thinned by the worn surface being moved down. The grinding continues until the desired thickness is removed. Thereafter, the structure was rinsed with distilled water to remove dirt.

The above grinding step abraded the top of the adhesive layer 30 by 20 microns, the top of the bump 16 by 10 microns, and the top of the conductive layer 36 by 10 microns. The thickness reduction has no significant effect on the bump 16 or the adhesive layer 30, However, the thickness of the conductive layer 36 is greatly reduced from 30 microns to 20 microns. After the polishing, the bumps 16, the adhesive layer 30 and the conductive layer 36 are coplanar on the top surface of the smooth splicing side in the upward direction on the substrate 34.

In this stage, as shown in FIG. 4E, the support plate 101 includes The carrier 10, the adhesive layer 30, and the reinforcement layer 33 are sacrificed. At this time, the sacrificial carrier 10 includes the bumps 16 and the flange layer 18. The bump 16 abuts the flange layer 18 at the bend angle 22 and extends upward from the flange layer 18 and is integrally formed with the flange layer 18. The bump 16 enters the opening 32 and the through hole 40 and is located at a central position within the opening 32 and the through hole 40. In addition, the top of the bump 16 is coplanar with the adjacent portion of the adhesive layer 30. The bump 16 is spaced apart from the reinforcing layer 33 and has a flat top pyramid shape whose size increases in a downward direction.

The punching pocket 20 faces downward and extends into the bump 16. The opening 32 and the through hole 40 are always located at a central position within the projection 16, the opening 32, and the through hole 40. Also, the bump 16 covers the punching pocket 20 from the upward direction. The stamping pocket 20 has a shape that conforms to the bumps 16 and extends across the majority of the bumps 16 in the vertical and side directions and maintains a flat top pyramid shape that decreases in size from the entrance at the flange layer 18.

The flange layer 18 extends laterally from the bump 16 while extending to the adhesive The layer 30, the reinforcing layer 33, the opening 32 and the through hole 40 are underneath and are in contact with the adhesive layer 30, but are kept at a distance from the reinforcing layer 33.

Adhesive layer 30 in notch 42 and bump 16 and reinforcing layer 33 Contacted and located between the bump 16 and the reinforcing layer 33 while filling the space between the bump 16 and the reinforcing layer 33. Further, the adhesive layer 30 is in contact with the reinforcing layer 33 and the flange layer 18 outside the notch 42. The adhesive layer 30 is covered in the lateral direction and The tapered sidewall 26 of the bump 16 is surrounded and extends laterally from the bump 16 to the peripheral edge of the assembly and solidifies. Accordingly, the adhesive layer 30 has a first thickness T1 adjacent the flange layer 18 and a second thickness T2 at the adjacent bump 16 wherein the first thickness T1 is different from the second thickness T2. That is, the distance D1 in the vertical direction between the flange layer 18 and the reinforcing layer 33 is different from the distance D2 in the side direction between the bump 16 and the reinforcing layer 33. In addition, when the adhesive layer 30 extends away from the flange layer 18 and enters the gap 42 between the bump 16 and the reinforcing layer 33, since the size of the bump 16 as it extends toward the flange layer 18 is in an increasing state, the adhesive layer 30 is adjacent The thickness at the bumps 16 also shows an increasing trend.

If a plurality of bumps are to be formed on the support plate 101, additional bumps 16 may be punched on the sacrificial carrier 10, and the adhesive layer 30 may be adjusted to include more openings 32 while adjusting the reinforcing layer 33 and the conductive layer 36. To include more through holes 40.

Next, as shown in FIG. 4F, an opening 361 penetrating the conductive layer 36 is formed at a predetermined position to facilitate subsequent fabrication of the coated via.

4G is a cross-sectional view showing the structure in which the electrical pads 17 are formed on the sacrificial carrier 10 of the bumps 16. The electrical pads 17 extend from the bumps 16 in the upward direction, and the bumps 16 cover the electrical pads 17 from the downward direction. The electrical pads 17 can be deposited and patterned by a variety of techniques including electroplating, electroless plating, evaporation, sputtering, and combinations thereof or etching after deposition of the film. The illustrated electrical pads 17 are gold pads, but may be made of other stable materials that resist etching during removal of the bumps 16. In this embodiment, the electrical pads 17 are deposited after the reinforcing layer 33 is attached to the sacrificial carrier, but the electrical pads 17 may also be deposited before the bumps 16 and the recesses 20 are formed. 5A to 5I are an embodiment of the present invention A cross-sectional view of a method for fabricating a cavity substrate, wherein the cavity substrate comprises a support plate, a coreless build-up circuit and a coated via, the support plate having an electrical pad exposed from the cavity, the coreless build-up circuit being electrically connected The electrical pad is electrically connected to both sides of the cavity substrate.

As shown in FIG. 5I, the pocket substrate 100 includes a support plate 101, The coreless build-up circuit 201 and the covered via 402. The support plate 101 includes an adhesive layer 30, a reinforcement layer 33, an electrical pad 17 and a terminal 182. The electrical pads 17 are exposed from the recesses 31, and the recesses 31 are laterally covered and surrounded by the adhesive layer 30. The coreless build-up circuit 201 includes a first dielectric layer 211, a first conductive line 241, a second dielectric layer 261, and a second conductive line 291.

FIG. 5A is deposited on the bump 16, the electrical pad 17, and the adhesive layer. 30 and a structural cross-sectional view of the first dielectric layer 211 on the reinforcing layer 33, wherein the first dielectric layer 211 can be exemplified by an epoxy resin, a glass epoxy, a polyimide, and the like. The first dielectric layer 211 can be formed by various techniques including film pressing, roller coating, spin coating, and spray deposition; the first dielectric layer 211 can be treated by plasma etching or coating an adhesion promoter. (not shown) to improve adhesion. The first dielectric layer 211 has a thickness of about 50 microns.

FIG. 5B is a first blind via formed through the first dielectric layer 211 A cross-sectional view of the structure of 221, excluding the electrically conductive pads 17 and selected portions of the conductive layer 36. The first blind via 211 can be formed by a variety of techniques including laser drilling, plasma etching, and lithography. Pulsed lasers can be used to improve laser drilling performance. Alternatively, a laser scanning beam can be used with a metal mask. The first blind hole 221 has a diameter of about 50 microns.

Referring to FIG. 5C, a first wire is formed on the first dielectric layer 211 241. The first wire 241 extends from the first dielectric layer 211 in the upward direction, and extends laterally on the first dielectric layer 211 and extends downwardly into the first blind hole 221 to electrically connect the electrical pad 17 and the conductive layer. 36. The first wire 241 can be deposited by various techniques to form a single layer or multilayer structure including electroplating, electroless plating, evaporation, sputtering, and combinations thereof.

For example, the structure may be immersed in an activator solution, Therefore, the first dielectric layer 211 can react with the electroless copper to generate a catalyst, and then a thin copper layer is formed by electroless plating to serve as a seed layer, and then a second copper layer having a predetermined thickness is plated by electroplating. On the seed layer, a first wire 241 which is respectively a first conductive layer is deposited. Alternatively, a thin film (such as titanium/copper) as a seed layer may be formed on the first dielectric layer 211 and the first blind via 221 by sputtering before depositing the copper plating layer on the seed layer. Once the predetermined thickness is reached, the first conductive layer (ie, the combination of the plated copper layer and the seed layer) is patterned to form the first wire 241, respectively. The patterning step of the first wire 241 can be performed by various techniques including wet etching, electrochemical etching, laser assisted etching, and combinations thereof, and an etching resist layer (not shown) defining the first wire 241 is used.

As also shown in FIG. 5C, the first coating 60 is sunken from the downward direction. It is accumulated on the bump 16 and the flange layer 18. Depositing the first coating layer 60 may use the same activator solution, electroless copper seed layer, and electroplated copper layer as the first wire 241. Preferably, the first coating layer 60 and the first wire 241 are simultaneously deposited in the same manner and have the same thickness. The first coating 60 is an unpatterned copper layer that contacts the bumps 16 and the flange layer 18 at the side lower surface and covers the bumps 16 and the flange layer 18 from the downward direction. For ease of illustration, the bumps 16 and convex The edge layer 18 and the first coating 60 are depicted as a single layer. Since copper is a homogeneous coating, the boundary between the bump 16 and the first coating 60 and between the flange layer 18 and the first coating 60 (both shown in dashed lines) may be less noticeable or even undetectable. The first wire 241 can provide a horizontal signal route in the X and Y directions, and can pass through the first blind hole 221 to provide vertical signal routing (from top to bottom) to electrically connect the electrical pad 17 and the conductive layer 36.

FIG. 5D is on the first wire 241 and the first dielectric layer 211 A structural cross-sectional view of the second dielectric layer 261 is deposited. Like the first dielectric layer 211, the second dielectric layer 261 can be epoxy, glass-epoxy, polyimine, and the like, and by various techniques (including film pressing, roller coating, Spin coating and spray deposition) were deposited to a thickness of 50 microns. Preferably, the first dielectric layer 211 and the second dielectric layer 261 are of the same material and are formed in the same manner and formed to have the same thickness.

FIG. 5E is a cross-sectional view of the structure having the perforations 401. Piercing 401 Corresponding to the opening 361 of the conductive layer 36, and axially aligned and located at the center of the opening 361. The through hole 401 extends through the second dielectric layer 261, the first dielectric layer 211, the reinforcement layer 33, the adhesive layer 30, the flange layer 18, and the first coating layer 60 in the vertical direction. The perforations 401 are formed by mechanical drilling, which may also be formed by other techniques, such as laser drilling and plasma etching with or without wet etching.

FIG. 5F is a second blind via formed through the second dielectric layer 261 A cross-sectional view of the structure of 281 exposes selected portions of the first wire 241. Like the first blind via 221, the second blind via 281 can be formed by various techniques including laser drilling, plasma etching, and lithography, and the second blind via 281 has It has a diameter of about 50 microns. Preferably, the first blind hole 221 and the second blind hole 281 are formed in the same manner and have the same size.

Referring to FIG. 5G, the second wire 291 is formed in the second layer. On the electrical layer 261. The second wire 291 extends from the second dielectric layer 261 in the upward direction, and extends laterally on the second dielectric layer 261 and extends from the downward direction into the second blind hole 281 to electrically connect the first wire 241.

The second wire 291 can use the same variety as the second conductive layer Techniques for deposition, including electroplating, electroless plating, evaporation, sputtering, and combinations thereof, are then patterned by various techniques, including wet etching, electrochemical etching, laser assisted etching, and combinations thereof, and using a defined second wire 291 The etching resist layer (not shown). Preferably, the first wire 241 and the second wire 291 are of the same material and are formed in the same thickness in the same manner.

Figure 5G also shows a second coating formed on the outside of the perforation 401 61 and a connection layer 62 formed in the through hole 401. The second coating 61 covers the bumps 16 and the flange layer 18 and extends downwardly from the bumps 16 and the flange layer 18, and a tie layer 62 is deposited in the vias 401 to provide the coated vias 402. The second coating layer 61 and the connection layer 62 may be formed by the same activator solution, electroless copper seed layer, and electroplated copper layer as the second wire 291. Preferably, the second coating layer 61, the connection layer 62, and the second wire 291 are deposited in the same manner and have the same thickness.

The second coating 61 is an unpatterned copper layer on the lower side surface The first coating 60 is contacted and the first coating 60 is covered by a downward direction. The connecting layer 62 is a hollow tubular shape that covers the inner side wall of the through hole 401 in the lateral direction and extends vertically to electrically connect the flange layer 18 and the first and second coating layers 60, 61 thereon. Connected to the second wire 291. Alternatively, the tie layer 62 can fill the perforations 401, whereby the coated perforations 402 are metal posts.

For ease of illustration, the bump 16, the flange layer 18, the first coating 60. The second coating layer 61 and the connecting layer 62 are illustrated as a single layer. Since copper is a homogeneous coating, the boundaries between the metal layers (both shown in dashed lines) may be difficult to detect or even detect. However, the boundary between the metal layer and the adhesive layer 30, the substrate 34, the first dielectric layer 211, and the second dielectric layer 261 is clearly visible.

At this stage, as shown in Figure 5G, the completed coreless build-up The circuit 201 includes a first dielectric layer 211, a first conductive line 241, a second dielectric layer 261, and a second conductive line 291. Further, the covered vias 402 are substantially shared by the support plate 101 and the coreless build-up circuit 201.

Fig. 5H is a cross-sectional view showing the structure obtained after inverting Fig. 5G.

FIG. 5I is a cross-sectional view showing the structure of the recess substrate 100 exposing the electrical pads 17 from the recess 31. The recess 31 is defined in the adhesive layer 30 by removing the bumps 16 and the first and second coating layers 60, 61 thereon, thereby exposing the electrical pads 17 from the recesses 31. At the same time, selected portions of the flange layer 18 and the first and second coating layers 60, 61 thereon are removed to define the terminals 182. Selected portions of the bumps 16 and flange layers 18 and the first and second coatings 60, 61 thereon may be removed by various techniques, including the use of an acid solution (e.g., ferric chloride, copper sulfate solution) or a base. Wet chemical etching, electrochemical etching, or mechanical procedures (such as drilling or end milling) of a solution (such as an ammonia solution) followed by chemical etching. The recess 31 is located at the center of the opening 32 and the through hole 40 and has a closed end in the downward direction and an open end in the upward direction. At the closed end, the recess 31 is coplanar with the adhesive layer 30 and the reinforcing layer 31, and the electrical pad 17 It is coplanar with the first dielectric layer 211. Further, the recess 31 has a flat bottom pyramid shape and its size increases as it extends upward.

At this stage, as shown in FIG. 5I, the support plate 101 includes adhesive The layer 30, the reinforcement layer 33, the electrical pads 17 and the terminals 182, and the mechanical support of the coreless build-up circuit 201 can be provided even if the sacrificial carrier 10 is removed. In this embodiment, the recess substrate 100 includes an adhesive layer 30, a reinforcing layer 33, an electrical pad 17, a terminal 182, a coreless build-up circuit 201, and a covered via 402. However, in some implementations, the terminals 182 and the covered vias 402 can be omitted depending on the desired design. Furthermore, the support plate 101 can include a plurality of pockets 31 by providing a sacrificial carrier plate 10 having a plurality of bumps 16 and thus defining a plurality of pockets 31.

The electrical pad 17 extends from the closed end of the recess 31 in a downward direction. The electrical pad 17 can serve as an electrical contact for the semiconductor component embedded in the recess 31 and electrically connect the semiconductor component to the coreless build-up circuit 201.

After the adhesive layer 30 is cured, laterally covering, surrounding and conforming the sidewalls of the recess 31, extending from the recess 31 to the peripheral edge of the recess substrate 100, sandwiched between the terminal 182 and the outside of the gap 42 of the reinforcing layer 33, The reinforcing layer 33 is covered and contacted in the upward direction, covered and joined by the terminal 182 in the downward direction, and the connecting layer 62 is connected by the lateral direction. The adhesive layer 30 has a first thickness at the side wall of the adjoining pocket 31 and a second thickness different from the first thickness at the reinforcing layer 33 in the upward direction. The mechanical stiffness of the cured adhesive layer 30 and the reinforcement layer 33 provides mechanical support for the coreless build-up circuit 201.

The terminal 182 extends from the adhesive layer 30 in the upward direction, maintains a distance from the coreless build-up circuit 201, and abuts the covered via 402, and one of them Body molding. The terminal 182 has a thickness of the bonding flange layer 18, the first coating layer 60 and the second coating layer 61, and can be used for grounding or/and supporting the heat sink to be attached to the semiconductor element embedded in the recess 31 or as another semiconductor. The electrical contact of the component or group.

The covered via 402 and the conductive layer 36 and the first conductive line 241 The distance is maintained on the electrical conduction path between the terminal 182 and the second wire 291, and extends from the terminal 182 through the second dielectric layer 261, the first dielectric layer 211, the substrate 34, and the adhesive layer 30 to the second. Wire 291. Therefore, the covered via 402 extends from the terminal 182 to the conductive layer outside the coreless build-up circuit 201 and is kept at a distance from the conductive layer within the coreless build-up circuit 201.

The coreless build-up circuit 201 can include an additional interconnect layer (eg, a third dielectric layer having a third blind via, a third lead, etc.).

The pocket substrate 100 can have a single recess or a plurality of recesses that can accommodate a plurality of semiconductor components rather than just a single semiconductor component. Thus, a plurality of semiconductor components can be disposed in a single recess or separate semiconductor components can be disposed in separate recesses. Accordingly, an additional electrical pad 17 can be provided, and the coreless build-up circuit 201 can include additional wires for additional components.

5J is a cross-sectional view of a plurality of wafers 711 having a plurality of wafers 711 attached to the interposer 712, wherein the interposer 712 is electrically coupled to the electrical pads 17 in the recesses 31. The inner connection pad 341 exposed from the opening 311 of the solder resist layer 301 can be used to form conductive contacts (such as solder bumps, solder balls, pins, and the like) to be electrically connected to external components or printed circuit boards (PCBs). Conducted and mechanically connected. The solder mask opening 311 can be formed by various methods including lithography, laser drilling, and plasma etching.

Figure 5K is a cross-sectional view of a three-dimensional stacked structure. The upper and lower assemblies 120, 130 respectively have semiconductor elements 72, 73 located in the recess 31, and are stacked by the solder balls 341 between the lower inner connection pads 341 of the upper assembly 120 and the upper inner connection pads 342 of the lower assembly 130. In this embodiment, two groups are stacked, however, more groups can be stacked if necessary.

[Embodiment 2]

6A to 6I are cross-sectional views showing a method of fabricating a recessed substrate according to another embodiment of the present invention, wherein the recessed substrate has a coated via and the coated via is connected to an inner conductive layer of the coreless build-up circuit.

For the purpose of brief description, any of the descriptions in Embodiment 1 may be incorporated in the same application portions herein, and the same description will not be repeated.

FIG. 6A is a cross-sectional view showing a structure in which the sacrificial carrier 10 has a barrier layer 161 at the bump 16 and an electrical pad 17 on the barrier layer 161. The sacrificial carrier 10 used in this embodiment is shown as being the same as in Embodiment 1, except that no punching pocket is defined in the bump 16, and the bump 16 according to this embodiment has a rectangular shape of uniform diameter. Further, the sacrificial carrier 10 according to the present embodiment further includes a barrier layer 161 on the bumps 16. The barrier layer 161 extends upward from the bump 16 and covers the bump 16. Barrier layer 161 can be deposited by a variety of techniques including electroplating, electroless plating, evaporation, sputtering, and combinations thereof. The barrier layer 161 is illustrated as a tin layer, but other barrier materials that protect the electrical pads 17 from being etched during removal of the bumps 16 may also be used. The electrical pads 17 are deposited on the barrier layer 161 and at a distance from the bumps 16 and extend outwardly from the bumps 16 . The electrical pads 17 are shown as copper pads, but other materials that can be stabilized when the barrier layer 161 is removed are also suitable. use.

Figure 6B shows the adhesive layer 30 on the flange layer 18, adhered to The reinforcing layer 33 on the layer 30, the first dielectric layer 211 on the reinforcing layer 33 and the electrical pad 17, and the metal layer 231 on the first dielectric layer 211. The bump 16 is inserted into the opening 32 and the through hole 40 without contacting the adhesive layer 30 and the reinforcing layer 33, and is aligned with the opening 32 and the through hole 40 and located at the center of the opening 32 and the through hole 40. Therefore, the notch 42 is located between the bump 16 and the reinforcing layer 33 in the through hole 40. In addition, the opening 32 and the through hole 40 are aligned with each other and have the same diameter, and the first dielectric layer 211 and the metal layer 231 are covered with the reinforcing layer 33, the bump 16, the barrier layer 161 and the electrical pad 17 in the upward direction. . In this embodiment, the substrate 34 having no conductive layer serves as the reinforcing layer 33.

6C shows the adhesive layer 30 in the notch 42 and the first dielectric A cross-sectional view of the structure in which the layer 211 is laminated on the reinforcing layer 33, the barrier layer 161, and the electrical pad 17. The adhesive layer 30 flows into the notch 42 under application of heat and pressure. In detail, by applying a downward pressure to the metal layer 231 and/or applying an upward pressure to the sacrificial carrier, the adhesive layer 30 is caused to flow into the notch 42, thereby pressing the reinforcing layer 33 and the sacrificial carrier 10 against each other. Pressure and heat are applied to the adhesive layer 30. The adhesive layer 30 can be arbitrarily shaped under heat and pressure. At the same time, the first dielectric layer 211 is pressed under heat and pressure and laminated on the reinforcing layer 33, the barrier layer 161, and the electrical pad 17 and contacts the adhesive layer 30. Even though the reinforcement layer 33, the adhesion layer 30, and the barrier layer 161 are depicted as being coplanar with each other, in practice they may not be coplanar and the first dielectric layer 211 may also be squeezed into the gap 42.

The sacrificial carrier 10 moves upward relative to the metal plate 231 as upwards The fine arrow is shown, and the metal plate 231 is moved downward relative to the sacrificial carrier 10 as Shown below the fine arrow.

Adhesive layer 30 fills up gap 42 and laminates first dielectric layer After 211, the adhesive cures the adhesive layer 30 and the first dielectric layer 211. Accordingly, the separately cured adhesive layer 30 and the first dielectric layer 211 can be between the sacrificial carrier 10 and the reinforcing layer 33, between the metal layer 231 and the electrical pad 17, and between the metal layer 231 and the reinforcing layer 33. Provide a strong mechanical connection between the two.

At this stage, as shown in FIG. 6C, the completed support plate 102 The device includes a sacrificial carrier 10 having a barrier layer 161 at the bumps 16, an adhesive layer 30, a reinforcing layer 33, and an electrical pad 17.

6D is formed through the first dielectric layer 211 and the metal layer 231 A first blind via 221 and a cross-sectional view of a via 401 formed through the metal layer 231, the first dielectric layer 211, the reinforcement layer 33, the adhesive layer 30, and the flange layer 18. The first blind hole 221 is aligned and exposes the electrical pad 17, and the through hole 401 extends through the structure in a vertical direction.

6E is a first dielectric by depositing and patterning a metal A structural cross-sectional view of the first wire 241 is formed on the layer 211. The first conductive layer 241 is formed by depositing a first coating layer 60 on the metal layer 231 and the first blind via 221, and then patterning the metal layer 231 and the first coating layer 60 thereon. The first coating layer 60 covers the metal layer 231 from the upward direction and extends upward from the metal layer 231 , and extends into the first blind hole 221 in the downward direction to electrically connect the electrical pads 17 . The first coating 60 also covers the side lower surface from a downward direction.

For ease of illustration, the metal layer 231 and the first coating 60 thereon It is depicted as a single layer. Since copper is a homogeneous coating, the boundaries between the metal layers (both shown in dashed lines) may be difficult to detect or even detect. However, the first coating The boundary between 60 and the first dielectric layer 211 is clearly visible.

As shown in FIG. 6E, the through hole 401 has a connecting layer 62 and an insulating filler 63 therein. The tie layer 62 provides a covered perforation 402 in the perforation 401. The connecting layer 62 is hollow tubular, which covers the inner side wall of the through hole 401 in the lateral direction and extends vertically to electrically connect the flange layer 18 and the first coating layer 60 thereon to the first wire 241, and the insulating filler 63 is filled. The remaining space in the perforation 401. Alternatively, the tie layer 62 may fill the perforations 401, whereby the tie layer 62 is a metal post and the voids 401 have no space for insulating filler 63 therein.

Preferably, the first coating 60 and the tie layer 62 simultaneously deposit the same material and have the same thickness in the same manner.

For ease of illustration, the bumps 16, flange layer 18, first coating 60, and tie layer 62 are depicted as a single layer. Since copper is a homogeneous coating, the boundaries between the metal layers (both shown in dashed lines) may be difficult to detect or even detect. However, the boundary between the metal layer and the adhesive layer 30, the reinforcing layer 33, and the first dielectric layer 211 is clearly visible.

FIG. 6F is a cross-sectional view showing the structure of the second dielectric layer 261 having the second blind via 281. The second dielectric layer 261 is deposited on the first conductive line 241 and the first dielectric layer 211, and the second blind via 281 extends through the second dielectric layer 261 and exposes selected portions of the first conductive line 241.

FIG. 6G is a cross-sectional view showing the structure of the second wiring 291 formed on the second dielectric layer 261. The second wire 291 extends upward from the second dielectric layer 261 and extends laterally on the second dielectric layer 261 and extends into the second blind hole 281 to electrically connect the wires 241.

At this stage, as shown in Figure 6G, the completed coreless build-up The circuit 201 includes a first dielectric layer 211, a first conductive line 241, a second dielectric layer 261, and a second conductive line 291. The coated vias 402 are connected to the inner conductive layer of the coreless build-up circuit 201.

Fig. 6H is a cross-sectional view showing the structure obtained after inverting Fig. 6G.

Figure 6I is a recess having an electrical pad 17 exposed from the recess 31. Substrate 200. The selected portions of the bumps 16 and flange layers 18 and the first coating 60 thereon are removed, the barrier layer 161 is exposed and the terminals 182 are defined. Then, the barrier layer 161 is removed to expose the electrical pads 17 from the recesses 31. Terminal 182 has a thickness that bonds flange layer 18 and first coating 60.

At this stage, as shown in FIG. 6I, the support plate 102 includes: sticky The layer 30, the reinforcing layer 33, the electrical pads 17 and the terminals 182 are formed. The terminal 182 extends from the adhesive layer 30 in the upward direction, and is spaced apart from the coreless build-up circuit 201 by the adhesive layer 30 and the reinforcing layer 33, and is electrically connected to the covered via 402. The coated vias 402 are shared by the support plate 102 and the coreless build-up circuit 201, and pass through the adhesive layer 30, the reinforcement layer 33, and the first terminal 182 on the electrical conduction path between the terminal 182 and the coreless build-up circuit 201. A dielectric layer 211 extends to the first wire 241.

[Example 3]

7A to 7J are drawings of a cavity substrate according to still another embodiment of the present invention. A cross-sectional view of the method, wherein the pocket substrate has a coated perforation connected to an inner pad of the support plate.

For the purpose of brief description, any of the examples in Embodiment 1 The description may be incorporated into the same application section herein, and the same description will not be repeated.

Figure 7A is a support plate made by the steps shown in Figures 1A-4E A cross-sectional view of the structure of 101.

7B is a cross-sectional view showing the structure of the through hole 401. The through hole 401 extends from the vertical direction and penetrates the flange layer 18, the adhesive layer 30, and the reinforcing layer 33.

7C is a cross-sectional view showing the structure in which the first coating layer 60 is located outside the through hole 401, and the connecting layer 62 and the insulating filler 63 are located in the through hole 401. The first coating 60 covers the bump 16 and the flange layer 18 and extends from the bump 16 and the flange layer 18 in a downward direction. The first coating layer 60 also covers the bumps 16, the adhesive layer 30, and the conductive layer 36 in the upward direction.

As also shown in FIG. 7C, a tie layer 62 is deposited in the perforations 401 to provide a covered perforation 402. The connecting layer 62 is hollow tubular, which covers the inner side wall of the through hole 401 in the lateral direction and extends vertically to electrically connect the flange layer 18 and the first coating layer 60 thereon to the conductive layer 36 and the first coating thereon. 60, and the insulating filler 63 fills the remaining space of the perforations 401. Alternatively, the tie layer 62 may fill the perforations 401, whereby the coated perforations 402 are metal posts and there is no space in the perforations 401 to insulate the filler material 63.

Preferably, the first coating 60 and the tie layer 62 are the same in the same manner and simultaneously deposit the same material and have the same thickness.

For ease of illustration, the bumps 16, the flange layer 18, the first coating 60, the conductive layer 36, and the tie layer 62 are depicted as a single layer. Since copper is a homogeneous coating, the boundaries between the metal layers (both shown in dashed lines) may be difficult to detect or even detect. However, the boundary between the metal layer and the adhesive layer 30 and the first coating layer 60, between the adhesive layer 30 and the connection layer 62, and between the substrate 34 and the connection layer 62 is clearly visible.

FIG. 7D is for sinking on the first coating layer 60 and the insulating filler 63. A cross-sectional view showing the structure of the second coating layer 61. The second coating layer 61 is an unpatterned copper layer that covers the first coating layer 60 and the insulating filler 63 and extends upward and downward from the first coating layer 60 and the insulating filler 63.

For ease of illustration, the bumps 16, the flange layer 18, the first coating 60, the second coating 61, the conductive layer 36, and the tie layer 62 are depicted as a single layer. Since copper is a homogeneous coating, the boundaries between the metal layers (both shown in dashed lines) may be difficult to detect or even detect.

7E is a cross-sectional view showing the formation of the inner pad 362 on the coated via 402 via the selectively patterned conductive layer 36, the first metal layer 60, and the second metal layer 61 on the upper surface using lithography and wet etching. The inner pad 362 abuts and is electrically connected to the covered perforation 402, extending laterally from the covered perforation 402 and covering the covered perforation 402 from the upward direction.

7F is a cross-sectional view showing the structure of the support plate 101 having the electrical pads 17 at the bumps 16. The electrical pads 17 extend from the second coating 61 upwardly beyond the bumps 16 .

At this stage, as shown in FIG. 7F, the support plate 101 includes a sacrificial carrier 10, a first coating 60, a second coating 61, an adhesive layer 30, a reinforcing layer 33, an inner pad 362, and an electrical pad 17. The covered perforations 402 extend through the support plate 101 in a vertical direction to electrically connect the inner pad 362 and the flange layer 18 and the first and second coating layers 60, 61 thereon.

7G is a cross-sectional view showing the structure of depositing the first dielectric layer 211 from the upward direction on the second coating layer 61 and the electrical pads 17. FIG. 7G also shows that the first blind via 221 is formed through the first dielectric layer 211, and the electrically exposed pad 17 and the inner pad 362 are formed.

Referring to FIG. 7H, a first layer is formed on the first dielectric layer 211. Wire 241. The first wire 241 extends from the first dielectric layer 211 in the upward direction, and extends laterally on the first dielectric layer 211 and extends through the first blind hole 211 in the upward direction to electrically contact the electrical pad 17 . And an inner pad 362.

At this stage, as shown in Figure 7H, the completed coreless build-up The circuit 202 includes a first dielectric layer 211 and a first conductive line 241.

Fig. 7I is a cross-sectional view showing the structure obtained after inverting Fig. 7H.

FIG. 7J is a recessed substrate 300 having exposed electrical pads 17 from the recesses 31. By removing the bumps 16 and the flange layer 18 and selected portions of the first and second coating layers 60, 61 thereon, recesses 31 are defined in the adhesive layer 30, thereby exposing the electrical pads from the recesses 31. 17 and define terminal 182. Terminal 182 has a thickness that bonds flange layer 18, first coating 60, and second coating 61.

At this stage, as shown in FIG. 7J, the support plate 101 includes an adhesive layer 30, a reinforcing layer 33, an electrical pad 17, an inner pad 362, and a terminal 182. The terminal 182 extends upward from the adhesive layer 30 and is adjacent and electrically connected to the covered via 402. The inner pad 362 extends from the reinforcing layer 33 toward the lower direction, and is adjacent to and electrically connected to the covered through hole 402 and the first wire 241. The coated via 402 extends from the terminal 182 to the inner pad 362 and extends through the adhesive layer 30 and the reinforcing layer 33 on the electrically conductive path between the coreless build-up circuit 202 and the terminal 182.

The above-mentioned recessed substrate, stacked semiconductor package and 3D stacked structure are merely illustrative examples, and the present invention can be implemented by other various embodiments. In addition, the above embodiments may be used in combination with each other or in combination with other embodiments based on design and reliability considerations. For example, the reinforcing layer may comprise a ceramic material or an epoxy-based laminate, and a single-layer wire may be embedded Or multilayer wires. The support plate can include a plurality of bumps to define a plurality of pockets in the adhesive layer. Accordingly, the recess substrate can include a plurality of recesses arranged in an array for use with a plurality of semiconductor components, and can include additional electrical pads to connect additional semiconductor components. Also, the build-up circuitry can include additional wires to receive additional electrical pads and provide routing for additional electrical pads.

The semiconductor component of the present invention can be used alone or in combination with other semiconductor components. For example, a single semiconductor component can be placed in a built-in recess or a plurality of semiconductor components can be placed in a built-in recess. For example, four small wafers arranged in a 2x2 array can be placed in built-in pockets to provide additional electrical pads and leads for additional wafers. This method is more economical than providing a small pocket for each wafer.

The semiconductor component of the present invention can be a packaged or unpackaged wafer. In addition, the semiconductor component can be a bare die, a grid array package (LGA), or a quad flat no-lead package (QFN). The semiconductor element can be mechanically and electrically connected to the cavity substrate by a plurality of connection media, including by soldering or the like. The recess substrate can be customized by the semiconductor component embedded therein. For example, the bottom of the pocket may be square or rectangular, and the shape of the crucible is the same as or similar to that of the semiconductor component.

The support plate provides stable mechanical support for the coreless build-up circuit, and the coreless build-up circuit provides short signal routing to reduce signal loss and distortion under accelerated operation of the semiconductor component.

As used herein, the term "adjacent" means that the elements are integrally formed (forming a single individual) or in contact with one another (with or without separation from one another). For example, the bump abuts the flange layer but does not abut the reinforcement layer.

The term "overlapping" means located above and extending below a lower element Within the perimeter of the piece. "Overlap" includes extending within, outside of, or within the circumference of the circumference. For example, in the state where the pocket is facing upward, the flange layer of the present invention overlaps the reinforcing layer because an imaginary vertical line can penetrate the flange layer and the reinforcing layer at the same time, regardless of the flange layer and the reinforcing layer. Whether there is another component (such as an adhesive layer) that is also penetrated by the imaginary vertical line, and whether or not another imaginary vertical line only penetrates the flange layer and does not penetrate the reinforcement layer (that is, the through hole in the reinforcement layer) . Similarly, the adhesive layer is superposed on the reinforcing layer, the flange layer is superposed on the adhesive layer, and the adhesive layer is overlapped by the reinforcing layer. In addition, "overlap" is synonymous with "below" and "overlap" is synonymous with "below".

The term "contact" means direct contact. For example, reinforcement splicing Touched the adhesive layer but did not touch the bump.

The term "covering" means ending in the vertical and / or side direction Full coverage. For example, in the state where the pocket is facing upward, if the adhesive layer covers the reinforcing layer, the adhesive layer does not cover the electrical pad from the upward direction.

The "layer" word contains patterned and unpatterned layers. E.g, When the reinforcing layer comprises a conductive layer and the substrate is disposed on the adhesive layer, the conductive layer may be a blank unpatterned flat plate on the substrate. In addition, a "layer" may comprise a plurality of superposed layers.

The words "opening", "through hole" and "perforation" refer to the through hole. hole. For example, in a state where the pocket is facing downward, after the bump is inserted into the opening of the adhesive layer, the projection is exposed from the adhesive layer in the upward direction. Similarly, after the bump is inserted into the through hole of the reinforcing layer, it is exposed from the reinforcing layer in the upward direction.

The term "insertion" means the relative movement between components. E.g, "Insert the bump into the through hole" includes: the flange layer is fixed and moved by the reinforcing layer toward the flange layer; the reinforcing layer is fixed and moved by the flange layer toward the reinforcing layer; or both the flange layer and the reinforcing layer are mutually Rely on. For another example, "inserting (or extending into) the through hole" includes: a through hole (through and through) of the through hole; and a through hole that is inserted but not penetrated (penetrated but not worn out).

The phrase "together with each other" means the relative movement between components. example For example, "the flange layer and the reinforcing layer abut each other" include: the flange layer is fixed and moved by the reinforcing layer toward the flange layer; the reinforcing layer is fixed and moved by the flange layer toward the reinforcing layer; or the flange layer and the reinforcement The layers are close to each other.

The term "alignment" means the relative position between components. E.g, When the adhesive layer has been disposed on the flange layer, the reinforcement layer has been disposed on the adhesive layer, the bump has been inserted and aligned with the opening, and the through hole has been aligned with the opening, whether the bump is inserted into the through hole or under the through hole and Keeping away from it, the bumps are aligned with the through holes.

The phrase "set in" encompasses a single or multiple support elements Contact and non-contact. For example, a heat sink is disposed on the semiconductor component regardless of whether the heat sink contacts the semiconductor component or is separated from the semiconductor component by an adhesive layer.

The phrase "adhesive layer in the gap..." means located in the gap Adhesive layer. For example, "the adhesion layer extends across the reinforcement layer within the gap" means that the adhesive layer within the gap extends across the reinforcement layer. Similarly, "the contact of the adhesive layer in the gap and between the bump and the reinforcing layer" means that the adhesive layer in the notch contacts and is between the bump of the inner side wall of the notch and the reinforcing layer of the outer side wall of the notch.

The term "electrical connection (or link)" means direct or indirect electricity Sexual connection (or link). For example, the first wire electrically connects (or joins) the inner contact pad and the electrical pad whether the first wire is adjacent to the inner connecting pad or electrically connected (or connected) to the inner connecting pad by the second wire.

The word "above" means extending upwards and includes adjacency and non- Adjacent elements as well as overlapping and non-overlapping elements. For example, in a state in which the pocket is facing downward, the bump extends over the flange layer while adjoining, overlapping the base and projecting out of the flange layer.

The word "below" is intended to mean extending downwards and includes adjacency and non- Adjacent elements as well as overlapping and non-overlapping elements. For example, in a state in which the pocket is facing upward, the base extends below the flange layer, abutting the flange layer and projecting downward from the flange layer. Likewise, the bumps may extend below the reinforcement layer even if they are not adjacent to or overlapped by the reinforcement layer.

"First vertical direction" and "second vertical direction" are not taken Depending on the orientation of the pocket substrate (or support plate), anyone familiar with the art can easily understand the direction in which it actually refers. For example, the bumps extend vertically to the outside of the reinforcing layer in a second vertical direction and extend perpendicularly to the first vertical direction to the outside of the flange layer, regardless of whether the support plate is inverted. Similarly, the flange layer projects "laterally" from the bump along a lateral plane, regardless of whether the support plate is inverted, rotated or tilted. Thus, the first and second vertical directions are opposite each other and perpendicular to the side direction, and further, the laterally aligned elements are coplanar with each other in a lateral plane perpendicular to the first and second perpendicular directions. Furthermore, when the pocket is upward, the first vertical direction is the downward direction and the second vertical direction is the upward direction; when the pocket is downward, the first vertical direction is the upward direction and the second vertical direction is the downward direction.

Pocket substrate of the invention and semiconductor group body using the same There are many advantages. The cavity substrate and the semiconductor package have high reliability, are inexpensive, and are extremely suitable for mass production. A heat sink can be attached to the original piece disposed in the recessed hole of the recessed substrate to enhance heat dissipation. Therefore, the cavity substrate is particularly suitable for high-power semiconductor components, large-sized semiconductor wafers, and a plurality of semiconductor components (for example, a plurality of small semiconductor wafers arranged in an array) which are easy to generate high heat and require excellent heat dissipation effects to operate efficiently and reliably. .

The production method of this case is highly applicable and unique. The way of progress combines the use of a variety of mature electrical, thermal and mechanical bonding technologies. In addition, the production method of this case can be implemented without expensive tools. As a result, this approach can significantly increase throughput, yield, performance and cost efficiency compared to traditional packaging techniques. Furthermore, the group in this case is extremely suitable for copper wafers and lead-free environmental requirements.

The embodiments described herein are for illustrative purposes, wherein the The components or steps that are well known in the art may be simplified or omitted in order to avoid obscuring the features of the present invention. Similarly, in order to make the drawings clear, the drawings may also omit redundant or non-essential components and component symbols.

Those skilled in the art will be able to readily appreciate various changes and modifications to the embodiments described herein. For example, the foregoing materials, dimensions, shapes, sizes, steps, and order of steps are merely examples. Variations, adjustments, and equalizations may be made by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

10‧‧‧ sacrificial carrier

17‧‧‧Electrical pads

30‧‧‧Adhesive layer

31‧‧‧ recess

33‧‧‧ Strengthening layer

60‧‧‧First coating

61‧‧‧Second coating

100‧‧‧ pocket substrate

101‧‧‧Support board

182‧‧‧ terminals

201‧‧‧ Coreless circuit

211‧‧‧First dielectric layer

241‧‧‧First wire

261‧‧‧Second dielectric layer

401‧‧‧Perforation

402‧‧‧Covered perforation

Claims (19)

A method for manufacturing a recessed substrate, comprising: providing a support plate comprising a sacrificial carrier, a reinforcing layer, an adhesive layer and an electrical pad; wherein (i) the sacrificial carrier comprises a bump and a a flange layer, (ii) the bump is adjacent to the flange layer and integrally formed with the flange layer, and extends from the flange layer toward a first vertical direction, (iii) the flange layer from the bump Extending laterally toward a side direction perpendicular to the first vertical direction, (iv) the reinforcing layer is attached to the sacrificial carrier via the adhesive layer, the adhesive layer being disposed between the reinforcing layer and the flange layer and Between the reinforcing layer and the bump, and (v) the electrical pad extends outside the bump in the first vertical direction, and the bump is in a second vertical direction opposite to the first vertical direction Covering the electrical pad; forming a coreless build-up circuit covering the electrical pad, the bump and the reinforcement layer in the first vertical direction, and the coreless build-up circuit is connected to the electrical connection Electrically connecting; and removing the bump to form a recess and exposing the electrical pad from the closed end of the recess A portion of a core buildup circuit, wherein the adhesive layer laterally covers and surrounds the recess, and the recess faces the second vertical direction. The method of claim 1, wherein the sacrificial carrier further includes a stamping pocket in the bump, and the bump covers the stamping pocket in the first vertical direction. The method of claim 1, wherein the step of providing the support plate comprises: providing the sacrificial carrier plate including the bump and the flange layer; Attaching the reinforcement layer to the sacrificial carrier via the adhesive layer disposed between the reinforcement layer and the flange layer and between the reinforcement layer and the bump, the step comprising aligning the bump a through hole of one of the reinforcing layers; and the electrical pad is provided at the bump of the sacrificial carrier before or after attaching the reinforcing layer to the sacrificial carrier via the adhesive layer. The method of claim 3, wherein the step of providing the sacrificial carrier comprises: mechanically stamping a metal plate. The method of claim 3, wherein the step of attaching the reinforcement layer to the sacrificial carrier via the adhesive layer comprises: providing between the flange layer of the sacrificial carrier and the reinforcement layer The uncured adhesive layer, the step of aligning the bump of the sacrificial carrier with an opening of the adhesive layer and the through hole of the reinforcing layer; and then flowing the adhesive layer into the through hole a gap between the bump and the reinforcing layer; and curing the adhesive, thereby mechanically attaching the reinforcing layer to the bump and the flange layer. The method of claim 1, wherein the step of forming the coreless build-up circuit comprises: providing a dielectric layer covering the electrical pad, the bump, and the first vertical direction Reinforcing the layer and including a blind hole aligned with the one of the electrical pads; then providing a wire extending from the dielectric layer toward the first vertical direction and extending laterally on the dielectric layer, and facing the first Two perpendicular directions extend through the blind hole to the electrical pad. The method of claim 1, further comprising: providing a covered perforation extending through the adhesive layer and the reinforcement layer to electrically connect the two sides of the recess substrate. The method of claim 7, wherein the step of providing the coated perforation comprises: providing a perforation extending through the adhesive layer and the reinforcement layer in the first and second vertical directions; A connecting layer is provided on one of the inner side walls of the perforation. The method of claim 1, wherein the step of removing the bump comprises: a chemical etching process. The method of claim 7, wherein the removing the bump comprises: simultaneously removing a selected portion of the flange layer to define a terminal, and the covered via is electrically connected to the terminal And the coreless build-up circuit. The method of claim 1, wherein the step of providing the support plate and the coreless build-up circuit comprises: providing the sacrificial carrier, wherein the bump of the sacrificial carrier has the electrical connection a pad; then attaching the reinforcement layer to the sacrificial carrier via the adhesive layer disposed between the reinforcement layer and the flange layer and between the reinforcement layer and the bump, the step comprising: causing the bump Aligning the via of the reinforcement layer; then providing a dielectric layer covering the electrical pad, the bump, and the reinforcement layer in the first vertical direction; Forming a blind via in the dielectric layer, wherein the blind via is aligned with the electrical pad; and providing a wire extending from the dielectric layer toward the first vertical direction and on the upper side of the dielectric layer Extending, and extending through the blind hole toward the second vertical direction to the electrical pad. The method of claim 1, wherein the step of providing the support plate and the coreless build-up circuit comprises: providing the sacrificial carrier; and then passing between the reinforcement layer and the flange layer, And the adhesive layer between the reinforcing layer and the bump, the reinforcing layer is attached to the sacrificial carrier, the step comprising aligning the bump with the through hole of the reinforcing layer; and then providing the bump The electrical pad; then providing a dielectric layer covering the electrical pad, the bump and the reinforcing layer in the first vertical direction; and then forming a blind hole in the dielectric layer, wherein the blind hole Aligning the hole with the electrical pad; then providing a wire extending from the dielectric layer toward the first vertical direction and laterally extending over the dielectric layer and extending through the second vertical direction Blind hole. The method of claim 1, wherein the step of providing the support plate and the coreless build-up circuit comprises: providing the sacrificial carrier, wherein the bump of the sacrificial carrier has the electrical connection Pad; then Attaching the reinforcing layer to the sacrificial carrier via a bonding layer disposed between the reinforcing layer and the flange layer and between the reinforcing layer and the bump, and simultaneously laminating a dielectric layer to the convex layer On the block, the electrical pad and the reinforcing layer, the step includes aligning the bump with the through hole of the reinforcing layer; then forming a blind hole in the dielectric layer, wherein the blind hole is aligned with the hole An electrical pad; then providing a wire extending from the dielectric layer toward the first vertical direction and extending laterally over the dielectric layer and extending through the blind via the second vertical direction to the electrical Sexual pads. The method of claim 7, wherein the step of providing the coated perforation and the coreless build-up circuit comprises: providing a through hole extending through the adhesive layer in the first and second vertical directions and The reinforcing layer; then providing a connecting layer on one of the inner sidewalls of the through hole; providing an inner contact pad extending from the reinforcing layer toward the first vertical direction and adjoining the connecting layer; and then providing a dielectric layer Covering the electrical pad, the bump, the reinforcing layer and the inner contact pad in the first vertical direction; then forming a blind hole and another blind hole in the dielectric layer, wherein the blind hole is Aligning the electrical pad, and the other blind via is aligned with the inner contact pad; then providing a wire extending from the dielectric layer toward the first vertical direction and extending laterally on the dielectric layer And extending through the blind hole and the other blind hole toward the second vertical direction to the electrical pad and the inner contact pad. The method of claim 7, wherein the step of providing the coated via and the coreless build-up circuit comprises: providing a dielectric layer covering the electrical pad in the first vertical direction, a bump and the reinforcing layer; then forming a blind via in the dielectric layer, wherein the blind via is aligned with the electrical pad; forming a through hole extending through the first and second vertical directions An adhesive layer, the reinforcement layer and the dielectric layer; a connection layer provided on one of the inner sidewalls of the through hole; and a wire extending from the dielectric layer toward the first vertical direction and on the dielectric layer The upper side extends and extends through the blind hole toward the second vertical direction to the electrical pad. A recess substrate prepared by a method comprising the steps of: providing a support plate comprising a sacrificial carrier, a reinforcing layer, an adhesive layer and an electrical pad; wherein (i) The sacrificial carrier includes a bump and a flange layer, (ii) the bump is adjacent to the flange layer and integrally formed with the flange layer, and extends from the flange layer toward a first vertical direction, Iii) the flange layer extends laterally from the bump toward a side perpendicular to the first vertical direction, (iv) the reinforcing layer is attached to the sacrificial carrier via the adhesive layer, the adhesive layer is disposed on the Between the reinforcing layer and the flange layer and between the reinforcing layer and the bump, and (v) the electrical pad extends outside the bump in the first vertical direction, and the bump is in the same a second vertical direction opposite one of the vertical directions covers the electrical pad; then Forming a coreless build-up circuit that covers the electrical pad, the bump, and the reinforcement layer in the first vertical direction, and the coreless build-up circuit is electrically connected to the electrical pad; Excluding the bump to form a recess and expose a portion of the electrical pad and the coreless build-up circuit from a closed end of the recess, wherein the adhesive layer laterally covers and surrounds the recess, and The pocket faces the second vertical direction. The pocket substrate of claim 16, wherein the pocket substrate comprises: the pocket having a closed end in the first vertical direction and an open end in the second vertical direction; The reinforcing layer includes a through hole, wherein the recess extends into the through hole; the adhesive layer laterally covers, surrounds and conforms to cover one side wall of the recess, and extends laterally from the recess to the substrate a peripheral edge covering and contacting the reinforcing layer in the second vertical direction; the electrical pad extending from the closed end of the recess toward the first vertical direction; and the coreless build-up circuit Covering the electrical pad, the closed end of the recess, and the adhesive layer in the first vertical direction, and being coplanar or higher than the electrical connection at the closed end of the recess a pad and electrically connected to the electrical pad. The pocket substrate of claim 17, wherein the pocket substrate comprises: a terminal extending outward from the adhesive layer toward the second vertical direction, and maintaining a distance from the coreless build-up circuit by the adhesive layer and the reinforcement layer; and a covered perforation extending through the adhesive layer and The reinforcing layer electrically connects the coreless build-up circuit and the terminal. The pocket substrate of claim 17, wherein the adhesive layer has a first thickness at the side wall adjacent to the recess, and the reinforcing layer at the second vertical direction has a different One of the first thicknesses of the second thickness.