KR20000046722A - Method for direct attachment bonding semiconductor chips - Google Patents
Method for direct attachment bonding semiconductor chips Download PDFInfo
- Publication number
- KR20000046722A KR20000046722A KR1019980063439A KR19980063439A KR20000046722A KR 20000046722 A KR20000046722 A KR 20000046722A KR 1019980063439 A KR1019980063439 A KR 1019980063439A KR 19980063439 A KR19980063439 A KR 19980063439A KR 20000046722 A KR20000046722 A KR 20000046722A
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- South Korea
- Prior art keywords
- bare chip
- semiconductor bare
- circuit board
- semiconductor chips
- semiconductor
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 title claims abstract description 27
- 229910000679 solder Inorganic materials 0.000 claims abstract description 13
- 239000002245 particle Substances 0.000 claims abstract description 4
- 239000004020 conductor Substances 0.000 claims description 7
- 239000011347 resin Substances 0.000 claims description 5
- 229920005989 resin Polymers 0.000 claims description 5
- 238000007747 plating Methods 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 2
- 239000000956 alloy Substances 0.000 claims description 2
- 239000007788 liquid Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 9
- 230000008878 coupling Effects 0.000 abstract 1
- 238000010168 coupling process Methods 0.000 abstract 1
- 238000005859 coupling reaction Methods 0.000 abstract 1
- 239000000853 adhesive Substances 0.000 description 7
- 230000001070 adhesive effect Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 235000002017 Zea mays subsp mays Nutrition 0.000 description 1
- 241000482268 Zea mays subsp. mays Species 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000010891 electric arc Methods 0.000 description 1
- 238000004880 explosion Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
Description
본 발명은, 패키지를 하지 않은 상태의 베어 칩(Bare Chip)과 회로기판을 직접 다이렉트 어테치 본딩하는 기술에 관한 것으로서, 특히 접속할 기판의 패드 위에 솔더 범프를 형성시킨 후, 반도체 베어칩을 다이렉트 어테치하여 접속시키는 반도체 베어 칩 다이렉트 어태치 본딩 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a technique for directly attaching a bare chip and a circuit board without a package, and in particular, after forming a solder bump on a pad of a substrate to be connected, the semiconductor bare chip is directly connected. The present invention relates to a semiconductor bare chip direct attach bonding method for attaching and connecting.
반도체 집적회로와 회로기판의 패턴과의 사이에 전기적 접속을 위한 방법으로서, 반도체 집적회로를 패키지하지 않고 베어칩 그대로를 직접 회로기판과 접속하는 다이렉트 어테치 본딩 공정은, 도 1 내지 도 7에 도시된 바와 같이, 반도체 베어칩(1)의 Al 패드(2)위에 스터드 범프(3)를 형성한 후, 균일한 높이를 유지하기 위하여 지그(4)를 이용하여 범프 레벨링(Levelling)을 실시하고 그 이후, 상기 범프(3)위에 도전성 접착제를 전사방법을 이용하여 공급한 다음, 회로기판(7)의 접속 패턴(6)과 가열 가압하여 접합시킨 후, 베어칩(1)과 기판(7)간의 갭에 수지를 충진(언더필링)하고 경화시킨다.As a method for electrical connection between a semiconductor integrated circuit and a pattern of a circuit board, a direct attach bonding process of connecting a bare chip directly to a circuit board without packaging the semiconductor integrated circuit is illustrated in FIGS. 1 to 7. As described above, after the stud bumps 3 are formed on the Al pads 2 of the semiconductor bare chip 1, bump leveling is performed using the jig 4 to maintain a uniform height. Thereafter, a conductive adhesive is supplied onto the bumps 3 using a transfer method, and then bonded by heating and pressing to the connection pattern 6 of the circuit board 7, and then between the bare chip 1 and the substrate 7. The gap is filled (underfilled) and cured.
한편, 상기 도전성 접착제의 전사방법은 도 8 내지 도10에 도시된 바와 같이, 도전성접착제(5)가 수용된 용기(12)에 베어칩(1)의 범프(3)를 담그어서 이루어진다.Meanwhile, the transfer method of the conductive adhesive is performed by dipping the bump 3 of the bare chip 1 in a container 12 in which the conductive adhesive 5 is accommodated, as shown in FIGS. 8 to 10.
이와 같이, 반도체 베어 칩의 Al 패드 위에 스터드 범프를 형성하는 방법은 Au 와이어 선단에 아크 방전을 통해 볼을 형성한 다음, 열과 압력 그리고 초음파 진동으로 Al 패드의 산화막을 파괴하여 Al 신생면과 Au간의 금속간화합물이 형성하여 접속하기 때문에 어레이 타입(Array Type)의 다핀 대응 패드를 갖는 IC에는 IC상의 회로 손상 때문에 적용할 수 없으며, 접착제 전사의 경우 범프 위에 적량의 접착제를 콘트롤하기가 쉽지 않고, 또, 회로기판 패턴과 접속시 수지로 언더필링(Underfilling)을 하는 공정에 있어서 수지를 충진하는 방법이 매우 까다로우며, 시간이 과도하게 소비되며, 불완전한 충진시 경화공정에서 기포의 폭발로 인한 팝콘 현상으로 인해 불량 발생이 용이하여 품질과 생산성, 비용 측면에 있어서 많은 단점을 갖고 있다.As described above, the method of forming the stud bump on the Al pad of the semiconductor bare chip is to form a ball through the arc discharge on the tip of the Au wire, and then destroy the oxide film of the Al pad by heat, pressure, and ultrasonic vibration, so that the Al new surface is separated from the Au. Because the intermetallic compound is formed and connected, it cannot be applied to ICs having array type multi-pin pads because of circuit damage on the IC, and it is not easy to control an appropriate amount of adhesive on the bumps in case of adhesive transfer. In the process of underfilling with resin when connecting with circuit board pattern, the method of filling resin is very difficult, time is excessively consumed, and popcorn phenomenon due to bubble explosion in curing process during incomplete filling. Due to the easy generation of defects have a number of disadvantages in terms of quality, productivity, cost.
본 발명은 이러한 종래 기술의 문제점을 해결하기 위한 것으로, 접속할 기판의 패드 위에 솔더 범프를 형성시킨 후, 반도체 베어칩을 다이렉트 어테치하여 접속하여, 베어칩의 외부전극과 회로기판의 전극 패턴간의 전기적 접속을 간단히 완성할 수 있는 반도체 베어 칩의 다이렉트 어태치 본딩 방법의 제공을 목적으로 한다.The present invention is to solve the problems of the prior art, and after forming a solder bump on the pad of the substrate to be connected, the semiconductor bare chip is directly attached and connected, the electrical between the bare electrode and the electrode pattern of the circuit board An object of the present invention is to provide a direct attach bonding method for a semiconductor bare chip which can easily complete a connection.
도 1 내지 도 7은 종래의 반도체 베어 칩의 다이렉트 어테치 본딩 공정도1 to 7 is a direct attach bonding process diagram of a conventional semiconductor bare chip
도 8 내지 도 10은 베어칩의 도전성 접착제의 전사 공정도8 to 10 is a transfer process diagram of the conductive adhesive of the bare chip
도 11 내지 도 14 는 본 발명의 반도체 베어 집적회로 다이렉트 어태치 본딩 공정도11 to 14 are diagrams illustrating a semiconductor bare integrated circuit direct attach bonding process of the present invention.
도 15 내지 도 18 은 본 발명에서 솔더 범프의 형성 공정도15 to 18 is a process chart of the formation of solder bumps in the present invention
도면의 주요 부분의 부호의 설명Explanation of Signs of Major Parts of Drawings
1 : 반도체 베어 칩 2 : 전극1 semiconductor bare chip 2 electrode
6 : 패턴패드 7 : 회로기판6: pattern pad 7: circuit board
3, 19 : 솔더범프 16 : 이방성 도체 페이스트3, 19: solder bump 16: anisotropic conductor paste
22 : 도전 입자22: conductive particles
본 발명의 반도체 베어 칩 다이렉트 어태치 본딩 방법은, 도 11 내지 도 14에 도시된 바와 같이, 반도체 베어칩(1)과 전기적 접속을 하는 회로기판(7) 패턴패드(7) 위에 솔더범프(3)을 형성한 후 그 위에 도포기(17)을 이용하여 이방성 도체 페이스트(Anisotropic Conductive Paste)(16)를 도포하고, 그 위에 베어칩(1)를 마운팅하여 경화시키어, 베어 칩의 외부전극과 회로기판의 전극 패턴간의 전기적 접속을 간단히 완성하는 방법이다.In the semiconductor bare chip direct attach bonding method of the present invention, as shown in FIGS. 11 to 14, the solder bumps 3 are formed on the circuit board 7 pattern pad 7, which is electrically connected to the semiconductor bare chip 1. ) And then apply an anisotropic conductive paste (16) on the applicator (17) using the applicator (17), and harden by mounting the bare chip (1) thereon. It is a method of simply completing the electrical connection between the electrode patterns of a board | substrate.
상기 이방성 도체 페이스트(16)는, 파인피치(Fine pitch)의 전극부의 전기적 접속을 위하여 사용되는 것으로서, 직경이 3∼10㎛의 많은 도전입자(22)를 액체 형태의 수지에 분산시킨 구조물로 정의한다.The anisotropic conductor paste 16 is used for electrical connection of fine pitch electrode portions, and is defined as a structure in which many conductive particles 22 having a diameter of 3 to 10 μm are dispersed in a liquid resin. do.
상기 이방성 도체 페이스트(16)의 도포는, 도포기(17)를 이용하여 진공의 적정 제어로 적량 간단히 도포한다. 상기 도포의 정도는 기판 위의 다른 혼재 부품에 영향을 주지 않는 정도로 양호하게 도포할 수 있다. 회로기판 패턴 패드에 이방성도체 페이스트의 도포가 완료된 다음, 기판과 반도체 베어 칩를 미리 카메라로 위치 인식시켜 놓고, 그 인식 위치에 마운팅하므로서 회로기판과 반도체 베어칩과의 접속이 간단하게 완료된다.The application of the anisotropic conductor paste 16 is simply applied in an appropriate amount by appropriate control of vacuum using the applicator 17. The degree of application can be applied well to such an extent that it does not affect other mixed parts on the substrate. After the application of the anisotropic conductor paste to the circuit board pattern pad is completed, the connection between the circuit board and the semiconductor bare chip is simply completed by positioning the substrate and the semiconductor bare chip with a camera in advance and mounting at the recognition position.
한편, 도 15 내지 도 18은, 반도체 베어칩과 전기적 접속을 하고자 하는 회로기판 패턴 패드 위에 접속용 솔더 범프를 형성하는 원리도로서, 회로기판(7)의 패턴(6)상에 도금용 레지스트(Resist)(18)를 도포한 다음, 솔더 합금 도금층(19)을 형성하고, 상기 레지스트(18)를 제거하고 퓨징(fusing)함으로서 간단히 범프(19)를 형성한다.15 to 18 are diagrams illustrating the formation of solder bumps for connection on a circuit board pattern pad to be electrically connected to a semiconductor bare chip. The plating resist (pattern 6) is formed on the pattern 6 of the circuit board 7. After applying the resist 18, the solder alloy plating layer 19 is formed, and the bump 18 is simply formed by removing and fusing the resist 18.
이상, 설명한 바와 같이, 본 발명에 따르면, 반도체 베어칩의 외부 전극 Al 패드에 범프를 형성하고, 도전성 접착제를 범프 위에 전사하고, 이를 회로기판에 마운팅한 후 회로기판과 반도체 칩 사이에 수지로 충진하여 전기적 접속을 시도했던 방법과는 달리, 반도체 베어 칩과 전기적 접속을 하는 회로기판 패턴 패드 위에 범프를 형성하고, 그 위에 이방성 도체 페이스트를 도포한 후, 반도체 베어 칩을망운팅한 다음, 경화함으로서 간단히 작업을 완료할 수 있어, 어레이 타입의 다핀 대응용 반도체 IC의 베어 칩 실장용으로 그 우수성이 있고, 범프형성시의 반도체 IC에 미치는 영향이 전혀 없어 고품질 달성은 물론, 비용을 대폭 절감할 수 있으며, 생산성을 극대화할 수 있다.As described above, according to the present invention, bumps are formed on an external electrode Al pad of a semiconductor bare chip, a conductive adhesive is transferred onto the bumps, mounted on a circuit board, and then filled with resin between the circuit board and the semiconductor chip. Unlike the method in which the electrical connection was attempted, the bumps were formed on the circuit board pattern pads in electrical connection with the semiconductor bare chip, the anisotropic conductor paste was applied thereon, and then the semiconductor bare chip was networked and then cured. Simple operation can be completed, and it is excellent for bare chip mounting of array type multi-pin semiconductor IC, and it has no influence on semiconductor IC during bump formation, thus achieving high quality and significantly reducing costs. And maximize productivity.
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Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980063439A KR100306116B1 (en) | 1998-12-31 | 1998-12-31 | Direct attach bonding method of semiconductor bare chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980063439A KR100306116B1 (en) | 1998-12-31 | 1998-12-31 | Direct attach bonding method of semiconductor bare chip |
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| Publication Number | Publication Date |
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| KR20000046722A true KR20000046722A (en) | 2000-07-25 |
| KR100306116B1 KR100306116B1 (en) | 2001-11-30 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002015259A1 (en) * | 2000-08-02 | 2002-02-21 | Korea Advanced Institute Of Science And Technology | High reliability non-conductive adhesives for non-solder flip chip bondings and flip chip bonding method using the same |
| KR100413587B1 (en) * | 2001-05-03 | 2003-12-31 | 주식회사 쏘타 테크놀로지 | Compressing device for electrically connecting semiconductor package to PCB by applying compression |
| WO2004064143A1 (en) * | 2003-01-08 | 2004-07-29 | Lg Cable Ltd. | Method of microelectrode connection and connected structure of use threof |
| KR100452025B1 (en) * | 2000-10-04 | 2004-10-08 | 가부시끼가이샤 도시바 | Semiconductor device and method of manufacturing the same |
| KR100810459B1 (en) * | 2005-12-15 | 2008-03-07 | 티디케이가부시기가이샤 | Method for forming an outer electrode |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100225398B1 (en) * | 1995-12-01 | 1999-10-15 | 구자홍 | Bonding structure of semiconductor bump and its method |
-
1998
- 1998-12-31 KR KR1019980063439A patent/KR100306116B1/en not_active IP Right Cessation
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002015259A1 (en) * | 2000-08-02 | 2002-02-21 | Korea Advanced Institute Of Science And Technology | High reliability non-conductive adhesives for non-solder flip chip bondings and flip chip bonding method using the same |
| US6930399B2 (en) | 2000-08-02 | 2005-08-16 | Korea Advanced Institute Of Science And Technology | High reliability non-conductive adhesives for non-solder flip chip bondings and flip chip bonding method using the same |
| KR100452025B1 (en) * | 2000-10-04 | 2004-10-08 | 가부시끼가이샤 도시바 | Semiconductor device and method of manufacturing the same |
| KR100413587B1 (en) * | 2001-05-03 | 2003-12-31 | 주식회사 쏘타 테크놀로지 | Compressing device for electrically connecting semiconductor package to PCB by applying compression |
| WO2004064143A1 (en) * | 2003-01-08 | 2004-07-29 | Lg Cable Ltd. | Method of microelectrode connection and connected structure of use threof |
| KR100810459B1 (en) * | 2005-12-15 | 2008-03-07 | 티디케이가부시기가이샤 | Method for forming an outer electrode |
| US7803421B2 (en) | 2005-12-15 | 2010-09-28 | Tdk Corporation | External electrode forming method |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100306116B1 (en) | 2001-11-30 |
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