KR100306115B1 - Component mixing method of circuit board - Google Patents
Component mixing method of circuit board Download PDFInfo
- Publication number
- KR100306115B1 KR100306115B1 KR1019980063437A KR19980063437A KR100306115B1 KR 100306115 B1 KR100306115 B1 KR 100306115B1 KR 1019980063437 A KR1019980063437 A KR 1019980063437A KR 19980063437 A KR19980063437 A KR 19980063437A KR 100306115 B1 KR100306115 B1 KR 100306115B1
- Authority
- KR
- South Korea
- Prior art keywords
- circuit board
- printed
- resin
- bare chip
- semiconductor
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
Abstract
본 발명은, 솔더 범프의 솔더링공정과 수지의 언더필링공정을 단일화하도록 한 반도체 베어 칩과 패키지형 반도체 칩과 그외 일반전자 부품의 회로기판에의 혼재 실장공법에 관한 것으로, 반도체 베어 칩 IC(11)가 실장되는 회로기판(2)의 패턴(1) 위에 열경화성 수지를 인쇄하고, 패키지형 반도체 IC(9)와 일반전자부품(8)이 실장되는 회로기판(2)의 패턴(1)위에 솔더 페이스트(4)를 인쇄하고, 상기 각 패턴 위에 패키지형 반도체 IC(9), 그 외 일반전자부품(8), 솔더 범프(12) 및 도전성 접착제(13)를 전사시킨 반도체 베어 칩 IC(11)를 마운팅하고, 일괄 리플로우 솔더링하여, 솔더링과 수지 경화작업을 동시에 처리하는 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor bare chip, a packaged semiconductor chip, and a mixed mounting method on a circuit board of other general electronic components in which a solder bump soldering step and a resin underfilling step are unified. The thermosetting resin is printed on the pattern 1 of the circuit board 2 on which the package is mounted, and the solder is printed on the pattern 1 of the circuit board 2 on which the packaged semiconductor IC 9 and the general electronic component 8 are mounted. The semiconductor bare chip IC 11 in which the paste 4 is printed and the packaged semiconductor IC 9, the other general electronic components 8, the solder bumps 12, and the conductive adhesive 13 are transferred onto the patterns. Mounting, batch reflow soldering, and simultaneous soldering and resin curing.
Description
본 발명은, 회로기판 위에 회로기판의 부품 실장공법에 관한 것으로, 특히, 솔더 범프의 솔더링공정과 수지의 언더필링공정을 단일화하도록 한 반도체 베어 칩과 패키지형 반도체 칩과 그외 일반전자 부품의 회로기판에의 혼재 실장공법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a circuit board component on a circuit board, and more particularly, to a semiconductor bare chip, a packaged semiconductor chip, and a circuit board of other general electronic components, which unitize a solder bump soldering process and a resin underfilling process. It is about mixed method of construction.
회로기판과 전자부품을 접합하여 회로를 완료하는 전자기기의 회로기판 조립공정에 있어서, 패키지 형태의 반도체 집적회로와, 패키지를 실시하지 않은 베어 칩(Bare Chip)형태의 반도체 집적회로 그리고 일반 전자부품을 하나의 회로기판 패턴과 전기적 접속을 목적으로 접합하는 경우, 도 1 내지 도 11에 도시된 바와 같이, 먼저 회로기판(2)의 동박패턴(1) 위에 솔더 페이스트(4)를 인쇄하고, 그 위에 일반 수동소자(8)와 패키지형 반도체 집적회로(9)를 마운팅한 다음, 리플로우 솔더링(Reflow Soldering)하여 접합시키고 그 다음, 범핑(Bumping)공정과 도전성 접착제 전사공정을 거친 베어 칩 집적회로(11)를 기판(2) 위에 마운팅하여, 가열/가압하여 접합시킨후, 베어 칩 IC(11)와 회로기판(2)간의 갭에 수지(16)를 충진하고 경화시킴으로서 작업을 완료한다. 도면에 있어서, (3)은 솔더 페이스트 도포를 위한 스퀴이지이고, (5)는 인쇄개구부(6)가 형성된 솔더 페이스트 마스크이고, (12)는 솔더범프, (13)도전성접착제, (15)는 수지 도포를 위한 도포기이다.In the circuit board assembly process of an electronic device which joins a circuit board and an electronic component to complete a circuit, a semiconductor integrated circuit in the form of a package, a semiconductor integrated circuit in the form of a bare chip, and a general electronic component are not packaged. In the case of bonding the circuit board pattern with one circuit board for the purpose of electrical connection, first, the solder paste 4 is printed on the copper foil pattern 1 of the circuit board 2, as shown in FIGS. After mounting the general passive element 8 and the packaged semiconductor integrated circuit 9 on the top, and then reflow soldering and bonding, and then a bare chip integrated circuit through a bumping process and a conductive adhesive transfer process (11) is mounted on the substrate 2, heated / pressurized to be bonded, and the work is completed by filling and curing the resin 16 in the gap between the bare chip IC 11 and the circuit board 2. In the figure, reference numeral 3 denotes a squeegee for solder paste application, reference numeral 5 denotes a solder paste mask in which the printing opening 6 is formed, reference numeral 12 denotes a solder bump, reference numeral 13 denotes a conductive adhesive, and reference numeral 15 denotes a conductive paste. It is an applicator for resin application.
이러한 종래의 방법에서는 솔더 범프와 회로기판 패턴을 접속하는 솔더링 공정과, 수지를 언더필링하는 공정이 각각 나누어져 진행되므로 인해 공정수가 많아지고, 작업시간이 과다하게 소요되는 문제점이 있었다.In this conventional method, since the soldering process for connecting the solder bumps and the circuit board pattern and the process for underfilling the resin are divided, the number of processes is increased and the work time is excessively required.
또한 반도체 베어 칩 IC와 회로기판과의갭은 불과 50∼80㎛로, 모세관 현상을 이용하는 경화성 수지의 충진 언더필링 공정은 베어 칩 IC 전면에 경화성 수지를 충진하기 위하여 상당한 시간이 소요될 뿐만 아니라, 충진 과정에 있어서 야기되는 보이드(Void)가 경화공정에서 급격한 온도로 인하여 폭발되며 팝콘현상을 일으켜 반도체 IC의 신뢰성에 결정적인 영향을 미칠수 있으며, 수율을 저하시키는 커다란 요인으로 작용하고, 전체 생산성을 저하하는 단점을 갖고 있다.In addition, the gap between the semiconductor bare chip IC and the circuit board is only 50 to 80 μm, and the filling underfilling process of the curable resin using the capillary phenomenon takes a considerable time to fill the curable resin on the entire bare chip IC as well as the filling. Voids caused in the process may explode due to rapid temperature in the curing process and may cause popcorn, which may have a decisive effect on the reliability of the semiconductor IC. It has a disadvantage.
또한 반도체 베어 칩 IC와 회로기판 사이에 베어 칩과 회로기판의 접착력을 강화시키기 위한 열경화형 수지의 언더필링공정을 최후에 전극간의 접합이 완료된 후에 실시함으로서, 가공공정이 복잡하고, 시간이 과다하게 소요되며, 복수의 가열로 반도체 신뢰성에 영향을 주며, 비용 상승 요인이 있었다.In addition, the underfilling process of the thermosetting resin for strengthening the adhesion between the bare chip and the circuit board between the semiconductor bare chip IC and the circuit board is carried out after the bonding between the electrodes is completed. A plurality of heating elements affect the reliability of the semiconductor and increase the cost.
본 발명은 이러한 종래 기술의 문제점을 해결하기 위한 것으로, 반도체 베어 칩 IC의 접합력 강화를 위해 실시하는 경화성 수지의 언더필링 처리를 생략하고, 최초의 공정에서 경화성 주지를 인쇄한 다음, 반도체 베어 칩 IC와 그 외 회로기판위에 접합될 모든 부품을 동시에 일괄 리플로우 솔더링하여 부품접합과 수지접합을 동시에 처리할 수 있는 회로기판의 부품 혼재 실장 공법의 제공을 목적으로 한다.SUMMARY OF THE INVENTION The present invention solves the problems of the prior art, omits the underfilling treatment of the curable resin to enhance the bonding strength of the semiconductor bare chip IC, and prints the curable resin at the first step, and then the semiconductor bare chip IC It is an object of the present invention to provide a mixed component mounting method for circuit boards capable of simultaneously processing component joints and resin joints by collectively reflow soldering all components to be joined on the circuit board.
상기 목적을 달성하기 위하여, 본 발명의 회로기판의 부품 혼재 실장 공법은, 반도체 베어 칩과 패키지형 반도체 칩과 일반전자 부품의 회로기판에의 혼재 실장공법에 있어서, 반도체 베어 칩 IC가 실장되는 회로기판의 패턴 위에 열경화성 수지를 인쇄하고, 패키지형 반도체 IC와 일반전자부품이 실장되는 회로기판의 패턴위에 솔더 페이스트를 인쇄하고, 상기 각 패턴 위에 패키지형 반도체 IC, 일반전자부품, 솔더 범프 및 도전성 접착제를 전사시킨 반도체 베어 칩 IC를 마운팅하고, 일괄 리플로우 솔더링하여, 솔더링과 수지 경화작업을 동시에 처리하는 것을 특징으로 한다.In order to achieve the above object, the mixed component mounting method of the circuit board of the present invention is a circuit in which the semiconductor bare chip IC is mounted in the mixed mounting method of the semiconductor bare chip, the package type semiconductor chip, and the general electronic component on the circuit board. A thermosetting resin is printed on a pattern of a substrate, a solder paste is printed on a pattern of a circuit board on which a packaged semiconductor IC and a general electronic component are mounted, and a packaged semiconductor IC, a general electronic component, a solder bump, and a conductive adhesive are printed on each pattern. The semiconductor bare chip IC, which has been transferred, is mounted, and batch reflow soldering is performed to simultaneously process soldering and resin curing.
도 1 내지 도 11는 종래의 회로기판의 부품 혼재 실장 공법의 공정도1 to 11 is a process diagram of a component mixture mounting method of a conventional circuit board
도 12 내지 도 18는 본 발명의 회로기판의 부품 혼재 실장 공법의 공정도12 to 18 is a process chart of the component mixture mounting method of the circuit board of the present invention
도 19 는 본 발명의 열경화성 수지 인쇄용 마스크 단면도19 is a cross-sectional view of the thermosetting resin printing mask of the present invention.
도 20 는 본 발명의 솔더 페이스트 마스크 단면도20 is a cross-sectional view of the solder paste mask of the present invention.
도면의 주요부분의 부호의 설명Explanation of Signs of Major Parts of Drawings
1 : 동박패턴 2 : 회로기판1: Copper foil pattern 2: Circuit board
8 : 일반 수동소자부품 9 : 패키지형 반도체 칩8: general passive component 9: package type semiconductor chip
11 : 반도체 베어 칩 18 : 열경화성수지11: semiconductor bare chip 18: thermosetting resin
20 : 열경화성 수지 인쇄용 마스크 21 : 솔더 페이스트 마스크20: thermosetting resin printing mask 21: solder paste mask
24 : 인쇄된 열경화성 수지 25 : 열경화후의 수지24: printed thermosetting resin 25: resin after thermosetting
본 발명의 회로기판의 부품 혼재 실장 공법은, 도 12내지 도 18에 도시된 바와 같이, 먼저 반도체 베어 칩 IC(11)가 실장되는 회로기판(2)의 패턴(1) 위에 열경화성 수지를 인쇄할 수 있도록, 도 19에 도시된 바와 같은, 열경화수지 인쇄용 마스크(20)의 개구부(19)를 이용하여 열경화성수지(18)를 인쇄한다. 그리고 도 20에 도시된 바와 같은, 인쇄된 수지를 보존하기 위하여 수지가 인쇄된 자리를 음각으로 파낸 하프에칭부(23)과 패키지형 반도체 IC(9) 및 그 외 일반전자부품(8)에 대응하여 솔더페이스트(4)가 인쇄될 자리에 개구부(22)가 형성된 솔더페이스트 인쇄용 마스크(21)를 이용하여 패키지형 반도체 IC(9)와 일반전자부품(8)이 실장되는 회로기판(2)의 패턴(1)위에 솔더 페이스트(4)를 인쇄한다. 그 다음, 패키지형 반도체 IC(9)를 마운팅하고 그 외 일반전자부품(8)을 차례로 마운팅하고, 외부 전극 Al 패드위에 솔더 범프(12) 및 도전성 접착제(13)를 전사시킨 반도체 베어 칩 IC(11)를 마운팅한다. 인쇄회로기판(2) 위에 접합할 모든 부품을 마운팅한 후, 이것을 일괄 리플로우 솔더링하는 공정을 통하여 솔더링과 반도체 베어칩IC와 기판간 접합력을 위한 수지 경화작업을 동시에 처리한다. 도면에서,(24)는 인쇄된 열경화성 수지이고, (25)는 열경화후의 수지이다.12 to 18, the thermosetting resin may be printed on the pattern 1 of the circuit board 2 on which the semiconductor bare chip IC 11 is mounted, as shown in FIGS. 12 to 18. As shown in FIG. 19, the thermosetting resin 18 is printed using the opening 19 of the thermosetting resin printing mask 20. In addition, as shown in FIG. 20, the half-etching part 23 in which the resin is printed is engraved in a recess to preserve the printed resin, the package-type semiconductor IC 9, and other general electronic components 8. Of the circuit board 2 on which the packaged semiconductor IC 9 and the general electronic component 8 are mounted using the solder paste printing mask 21 having the opening 22 formed at the place where the solder paste 4 is to be printed. The solder paste 4 is printed on the pattern 1. Next, the semiconductor bare chip IC in which the packaged semiconductor IC 9 is mounted and the other general electronic components 8 are sequentially mounted, and the solder bumps 12 and the conductive adhesive 13 are transferred onto the external electrode Al pads ( Mount 11). After mounting all the components to be bonded on the printed circuit board 2, a batch reflow soldering process is performed to simultaneously process soldering and resin curing for bonding strength between the semiconductor bare chip IC and the substrate. In the figure, 24 is a printed thermosetting resin, and 25 is a resin after thermosetting.
이상, 설명한 바와 같이, 본 발명에 따르면, 반도체 베어 칩 IC와 회로기판 위에 접합될 모든 부품을 동시에 일괄 하나의 작업으로 처리하므로, 과다한 시간이 소요되어 생산성을 저하시키는 언더필링 공정을 생략할 수 있어 생산성을 증대할수 있을 뿐 만 아니라, 복수의 가열에 따른 반도체 IC의 신뢰성 향상에도 기여하며, 저 비용를 실현할 수 있다.As described above, according to the present invention, since all parts to be bonded on the semiconductor bare chip IC and the circuit board are processed simultaneously in one operation, an underfilling process that takes excessive time and reduces productivity can be omitted. Not only can the productivity be increased, but it also contributes to the improvement of the reliability of the semiconductor IC by the plurality of heating, and the low cost can be realized.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980063437A KR100306115B1 (en) | 1998-12-31 | 1998-12-31 | Component mixing method of circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980063437A KR100306115B1 (en) | 1998-12-31 | 1998-12-31 | Component mixing method of circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20000046720A KR20000046720A (en) | 2000-07-25 |
| KR100306115B1 true KR100306115B1 (en) | 2002-03-25 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980063437A KR100306115B1 (en) | 1998-12-31 | 1998-12-31 | Component mixing method of circuit board |
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| Country | Link |
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| KR (1) | KR100306115B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10178769B2 (en) | 2016-08-26 | 2019-01-08 | Samsung Display Co., Ltd. | Bonded assembly and display device including the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002359461A (en) * | 2001-06-01 | 2002-12-13 | Nec Corp | Electronic component mounting method, mounting structure, and metal mask |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0555736A (en) * | 1991-08-22 | 1993-03-05 | Fujitsu General Ltd | Chip component mounting method |
-
1998
- 1998-12-31 KR KR1019980063437A patent/KR100306115B1/en not_active IP Right Cessation
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0555736A (en) * | 1991-08-22 | 1993-03-05 | Fujitsu General Ltd | Chip component mounting method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10178769B2 (en) | 2016-08-26 | 2019-01-08 | Samsung Display Co., Ltd. | Bonded assembly and display device including the same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20000046720A (en) | 2000-07-25 |
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