CN110620053A - Fan-out type packaging structure with laser opening blocking layer and preparation method thereof - Google Patents

Fan-out type packaging structure with laser opening blocking layer and preparation method thereof Download PDF

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Publication number
CN110620053A
CN110620053A CN201910841901.6A CN201910841901A CN110620053A CN 110620053 A CN110620053 A CN 110620053A CN 201910841901 A CN201910841901 A CN 201910841901A CN 110620053 A CN110620053 A CN 110620053A
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layer
laser opening
chip
laser
opening blocking
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CN201910841901.6A
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CN110620053B (en
Inventor
蔡琨辰
匡自亮
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Guangdong Fozhixin Microelectronics Technology Research Co ltd
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Guangdong Xinhua Microelectronics Technology Co Ltd
Guangdong Fozhixin Microelectronics Technology Research Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/111—Manufacture and pre-treatment of the bump connector preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13008—Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting

Abstract

The invention discloses a fan-out type packaging structure with a laser opening blocking layer and a preparation method thereof, wherein the preparation method comprises the following steps: s10, providing a carrier plate and a plurality of chips, packaging the chips on one side of the carrier plate by adopting a plastic package material, and then removing the carrier plate to expose the front surfaces of the chips out of the plastic package material; s20, providing a laser opening barrier layer and a dielectric layer, attaching the laser opening barrier layer to the front surface of the chip and the dielectric layer to the laser opening barrier layer, performing laser opening treatment on the dielectric layer to form a through hole, and removing the laser opening barrier layer at the through hole to expose the I/O interface of the chip; and S30, manufacturing a seed layer and a rewiring layer, and leading out the chip to be electrically connected with the metal bump in a welding mode. According to the invention, the laser opening barrier layer is attached between the dielectric layer and the chip, so that the problem that the laser opening directly hits the chip I/O to damage the chip or the electrical connection is not thoroughly influenced by the laser opening can be avoided.

Description

Fan-out type packaging structure with laser opening blocking layer and preparation method thereof
Technical Field
The invention relates to the technical field of integrated circuit packaging, in particular to a fan-out type packaging structure with a laser opening blocking layer and a preparation method thereof.
Background
With the trend of miniaturization and integration of electronic products, the densification of microelectronic packaging technology has gradually become the mainstream of new generation of electronic products. In order to comply with the development of the new generation of electronic products, especially the development of mobile phones, notebooks and other products, the chip is developed in the direction of higher density, faster speed, smaller size, lower cost and the like. Compared with the traditional package, the fan-out package greatly increases the pin number of the chip, reduces the package size, simplifies the package steps, shortens the distance between the chip and the substrate, improves the chip function, and has the advantages of supporting the chip with the process procedure of less than 10nm, short interconnection path, high integration degree, ultrathin thickness, high reliability, high heat dissipation capability and the like.
In the fan-out type packaging process, laser opening of the dielectric layer is needed to expose the chip I/O, but the laser opening process may damage the chip I/O. On one hand, due to the heating problem of the laser opening, the temperature near the I/O of the chip is too high, the chip can be scrapped, on the other hand, the depth of the laser opening is difficult to accurately control, and particularly, the electrical connection is poor under the condition of opening multiple laser beams once, so that the high yield of the packaging body is difficult to achieve. In order to solve the above problems, a laser is usually used to form a hole with a trace thickness, but the hole-forming method has a very high requirement on the thickness uniformity of the dielectric layer, and the thickness uniformity of the current dielectric layer cannot meet the requirement, so that the trace thickness remaining in the hole-forming process is difficult to control accurately.
Disclosure of Invention
The invention aims to provide a preparation method of a fan-out type packaging structure with a laser opening blocking layer and the fan-out type packaging structure with the laser opening blocking layer prepared by the method, which can effectively ensure that the I/O of a chip is not damaged when laser is opened, and can solve the problem of incomplete laser opening.
In order to achieve the purpose, the invention adopts the following technical scheme:
in one aspect, a method for manufacturing a fan-out package structure with a laser opening blocking layer is provided, which includes the following steps:
s10, providing a carrier plate and a plurality of chips, packaging the chips on one side of the carrier plate by adopting a plastic package material, and then removing the carrier plate to expose the front surfaces of the chips out of the plastic package material;
s20, providing a laser opening blocking layer and a dielectric layer, attaching the laser opening blocking layer to the front surface of the chip and attaching the dielectric layer to the laser opening blocking layer, carrying out laser opening processing on the dielectric layer to form a through hole, and removing the laser opening blocking layer at the through hole to expose an I/O interface of the chip;
and S30, manufacturing a seed layer and a rewiring layer, and leading out the chip to be electrically connected with the metal bump in a welding mode.
The dielectric layer is made of ABF (Ajinomoto Build-up Film) or PP (Polypropylene), and is attached to the laser opening blocking layer to play an insulating role.
The laser opening blocking layer is attached in advance before the dielectric layer is attached, when the dielectric layer is subjected to laser opening, the depth of the laser opening is not required to be set, the laser penetrates through the dielectric layer and is blocked by the laser opening blocking layer, the problem that the laser is continuously opened and directly hit to a chip I/O to damage the chip or the problem that the electrical connection of the chip is influenced due to incomplete laser opening is solved, the laser opening blocking layer at the chip I/O is removed by using plasma dry etching or chemical removing, and the chip is electrically led out to be welded with the metal bump by manufacturing the seed layer and the rewiring layer.
Wherein, the plasma dry etching mode is that plasma is obtained by laser or ionized etching gas in a plasma etching machine, and the plasma is used for making radio frequency plasma to bombard the film for etching; the chemical removal mode is to remove the laser opening barrier layer by chemical etching with chemical solution.
As a preferred scheme of the preparation method of the fan-out type packaging structure with the laser opening blocking layer, the raw materials of the laser opening blocking layer comprise: organic silicon resin, polycarbosilane, glass powder and heat-resistant filler. The organic silicon resin, the polycarbosilane and the glass powder are used as adhesives of the laser blocking layer, the adhesives have enough viscosity to be stably adhered to the chip and the plastic packaging layer, and the laser hole-forming blocking layer has a good heat-resistant effect due to the addition of the heat-resistant filler, so that laser breakdown is prevented.
As a preferred scheme of the preparation method of the fan-out type packaging structure with the laser opening blocking layer, the heat-resistant filler comprises BN and/or SiO2。
As a preferred scheme of the preparation method of the fan-out type packaging structure with the laser opening blocking layer, the thickness of the laser opening blocking layer is 5-10 mu m, and when the laser opening blocking layer is too thin, heat generated after laser breaks down a dielectric layer can affect the I/O of a chip; when the laser-opened barrier layer is too thick, the subsequent removal time is prolonged.
As a preferable scheme of the preparation method of the fan-out type packaging structure with the laser opening blocking layer, the thickness difference of the laser opening blocking layer is less than 5% so as to have certain uniformity.
As a preferable scheme of the method for manufacturing the fan-out package structure with the laser opening blocking layer, the step S10 specifically includes:
s10a, providing a carrier plate and a temporary bonding layer, and attaching the temporary bonding layer to one side face of the carrier plate;
s10b, providing a plurality of chips, and adhering the front surfaces of the chips to the temporary bonding layer towards the side far away from the carrier plate;
s10c, packaging the chip by adopting a plastic package material, and forming a plastic package layer after the plastic package material is solidified;
s10d, grinding the plastic packaging layer to enable the front surface of the chip to be flush with the ground surface of the plastic packaging layer;
s10e, removing the temporary bonding layer and the carrier plate.
The chip is adhered to the temporary bonding layer in the Face up mode.
Of course, in other technical solutions, the chip may also be adhered to the temporary bonding layer in a Face down manner.
When the chip may also be attached to the temporary bonding layer in a Face down manner, step S10 specifically includes:
s10a, providing a carrier plate and a temporary bonding layer, and attaching the temporary bonding layer to one side face of the carrier plate;
s10b, providing a plurality of chips, and adhering the front surfaces of the chips to the temporary bonding layer towards one side close to the carrier plate;
s10c, packaging the chip by adopting a plastic package material, and forming a plastic package layer after the plastic package material is solidified;
s10d, removing the temporary bonding layer and the carrier plate;
and S10e, cleaning the front surface of the chip by using plasma.
As a preferable scheme of the method for manufacturing the fan-out package structure with the laser opening blocking layer, the step S30 specifically includes:
s30a, manufacturing seed layers in the through holes and on the dielectric layer in an electroplating, chemical plating or PVD mode;
s30b, providing a photosensitive dry film, and attaching the photosensitive dry film to the seed layer;
s30c, forming a patterning hole exposing part of the seed layer on the photosensitive dry film through exposure and development processing, and enabling the patterning hole to at least correspond to the I/O interface position of the chip;
s30d, electroplating the patterned holes to form a rewiring layer in the patterned holes;
s30e, removing the residual photosensitive dry film to expose part of the seed layer;
s30f, etching the exposed seed layer, and removing the seed layer;
s30g, coating photosensitive ink on one surface, far away from the plastic package layer, of the dielectric layer, and enabling the photosensitive ink to cover the dielectric layer and the pad area of the rewiring layer; forming a solder mask hole with a graphical hole through exposure, development and curing treatment, wherein a pad area of the rewiring layer is exposed out of the solder mask;
and S30h, providing a metal bump, and implanting the metal bump into the pad area.
Optionally, the metal bump is a solder, a silver solder or a gold-tin alloy solder, and the embodiment is preferably a solder ball made of the solder, and the solder ball is welded and implanted in the pad region to achieve electrical leading-out of the redistribution layer.
As a preferred embodiment of the method for manufacturing a fan-out package structure with a laser opening blocking layer, step S30a specifically includes: and sequentially manufacturing a titanium metal layer and a copper metal layer in the through hole and on the dielectric layer in an electroplating, chemical plating or PVD (physical vapor deposition) mode, wherein the titanium metal layer and the copper metal layer form the seed layer. The titanium metal layer has high adhesion, excellent conductivity and uniform thickness, and the copper metal layer can be stably adhered to the plastic packaging layer through the titanium metal layer.
On the other hand, the fan-out type packaging structure with the laser opening blocking layer is provided and is manufactured by the manufacturing method.
The invention has the beneficial effects that: according to the invention, a laser opening barrier layer is attached in advance before a dielectric layer is attached to protect a chip, when the dielectric layer is subjected to laser opening, the depth of the laser opening is not required to be set, and the laser penetrates through the dielectric layer and is blocked by the laser opening barrier layer, so that the problem that the laser continues to open the opening to directly impact the I/O of the chip to damage the chip or the electrical connection of the chip is influenced due to incomplete laser opening is prevented.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly described below. It is obvious that the drawings described below are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
Fig. 1 is a cross-sectional view of a carrier according to a first embodiment of the invention.
Fig. 2 is a cross-sectional view of a temporary bonding layer attached to a carrier according to a first embodiment of the invention.
Fig. 3 is a cross-sectional view of an intermediate product after a chip is attached to a temporary bonding layer according to a first embodiment of the present invention.
Fig. 4 is a cross-sectional view of an intermediate product after a chip is molded by using a molding compound according to a first embodiment of the present invention.
Fig. 5 is a cross-sectional view of an intermediate product after grinding of a molding layer according to a first embodiment of the present invention.
Fig. 6 is a cross-sectional view of an intermediate product after removing the temporary bonding layer and the carrier according to a first embodiment of the invention.
Fig. 7 is a cross-sectional view of an intermediate product of a laser-cut barrier layer attached to a chip according to a first embodiment of the present invention.
Fig. 8 is a cross-sectional view of an intermediate product after a dielectric layer is attached to a laser opening blocking layer according to a first embodiment of the present invention.
Fig. 9 is a cross-sectional view of an intermediate product after opening a dielectric layer according to a first embodiment of the present invention.
Fig. 10 is a cross-sectional view of an intermediate product after removing a laser blocking layer according to a first embodiment of the present invention.
Fig. 11 is a cross-sectional view of an intermediate product after a seed layer is formed by sputtering according to a first embodiment of the present invention.
Fig. 12 is a cross-sectional view of an intermediate product of a photosensitive dry film attached to a seed layer according to a first embodiment of the invention.
Fig. 13 is a cross-sectional view of an intermediate product after exposure and development of the photosensitive dry film according to the first embodiment of the present invention.
Fig. 14 is a cross-sectional view of an intermediate product after pattern plating to obtain a redistribution layer according to a first embodiment of the present invention.
Fig. 15 is a cross-sectional view of an intermediate product after etching to remove a portion of the seed layer according to a first embodiment of the invention.
Fig. 16 is a cross-sectional view of an intermediate product after a solder resist layer is formed according to the first embodiment of the present invention.
Fig. 17 is a cross-sectional view of an intermediate product after solder balls are implanted into the pad region according to a first embodiment of the present invention.
Fig. 18 is a cross-sectional view of a carrier according to a second embodiment of the invention.
Fig. 19 is a cross-sectional view of a temporary bonding layer attached to a carrier according to a second embodiment of the invention.
Fig. 20 is a cross-sectional view of an intermediate product after a chip is attached to a temporary bonding layer according to the second embodiment of the present invention.
Fig. 21 is a cross-sectional view of an intermediate product after a chip is molded with a molding compound according to a second embodiment of the present invention.
Fig. 22 is a cross-sectional view of an intermediate product after removing the temporary bonding layer and the carrier according to the second embodiment of the invention.
Fig. 23 is a cross-sectional view of an intermediate product of a laser-cut barrier layer attached to a chip according to a second embodiment of the present invention.
Fig. 24 is a cross-sectional view of an intermediate product after a dielectric layer is attached to a laser opening blocking layer according to the second embodiment of the present invention.
Fig. 25 is a cross-sectional view of an intermediate product after opening a dielectric layer according to the second embodiment of the present invention.
Fig. 26 is a cross-sectional view of an intermediate product after the laser blocking layer is removed according to the second embodiment of the present invention.
Fig. 27 is a cross-sectional view of an intermediate product after a seed layer is formed by sputtering according to the second embodiment of the present invention.
Fig. 28 is a cross-sectional view of an intermediate product of a photosensitive dry film attached to a seed layer according to a second embodiment of the present invention.
Fig. 29 is a cross-sectional view of an intermediate product after exposure and development of a photosensitive dry film according to the second embodiment of the present invention.
Fig. 30 is a cross-sectional view of an intermediate product after pattern plating to obtain a redistribution layer according to the second embodiment of the present invention.
Fig. 31 is a cross-sectional view of an intermediate product after etching to remove a portion of the seed layer according to the second embodiment of the present invention.
Fig. 32 is a cross-sectional view of an intermediate product after a solder resist layer is formed according to the second embodiment of the present invention.
Fig. 33 is a cross-sectional view of an intermediate product after solder balls are implanted into the pad region according to the second embodiment of the present invention.
In the figure:
1. a carrier plate;
2. a temporary bonding layer;
3. a chip;
4. a plastic packaging layer;
5. laser drilling a barrier layer;
6. a dielectric layer;
7. a seed layer;
8. photosensitive dry film;
9. a wiring layer is arranged;
10. a solder resist layer;
11. solder balls.
Detailed Description
The technical solution of the present invention is further explained by the following embodiments.
Unless otherwise specified, various starting materials of the present invention are commercially available or prepared according to conventional methods in the art.
Example one
The fan-out package structure with the laser opening blocking layer is manufactured by the following method:
1. covering a temporary bonding layer 2 (temporary bonding glue) which is easy to be debonded on the glass carrier 1 shown in fig. 1, as shown in fig. 2;
2. the chip 3 is adhered on the temporary bonding layer 2 in the form of Face up, as shown in fig. 3;
3. as shown in fig. 4, the chip 3 is subjected to injection molding to form a molding layer 4 to protect the chip;
4. as shown in fig. 5, the bumps (I/O interfaces) of the chip 3 are exposed by grinding away a certain plastic package layer 4;
5. as shown in fig. 6, the temporary bonding layer 2 and the carrier 1 therebelow are removed, and the surface is plasma-cleaned to avoid organic residue;
6. as shown in fig. 7, a laser opening blocking layer 5(Stop layer) with a thickness of 7 μm is adhered above the salient points of the chip 3;
7. as shown in fig. 8, an ABF dielectric layer 6 is adhered on the laser opening blocking layer 5;
8. as shown in fig. 9, the ABF dielectric layer 6 is opened by using a laser, and the laser cannot open any more when encountering the laser opening blocking layer 5;
9. as shown in fig. 10, the laser barrier layer 5 is removed by plasma dry etching to expose the bumps of the chip 3;
10. as shown in fig. 11, a Ti/Cu seed layer 7 is formed by PVD, sputtering;
11. a photosensitive dry film 8 is laminated on the surface of the seed layer 7 (fig. 12), and exposure and development (fig. 13) and pattern plating are performed at positions where a subsequent wiring is not required to be formed, to obtain a rewiring layer 9 (fig. 14).
12. Then, a film removing process is performed, and an unnecessary Ti/Cu seed layer 7 is removed by a differential etching method (FIG. 15).
13. And finally, coating photosensitive ink, carrying out exposure, development, curing treatment and surface treatment to form a solder mask layer 10, exposing a pad area of the wiring layer 9 to the solder mask layer 10 (figure 16), implanting solder balls 11 into the pad area (figure 17), and cutting to obtain the required single packaging body.
Example two
The fan-out package structure with the laser opening blocking layer is manufactured by the following method:
1. covering a temporary bonding layer 2 (temporary bonding glue) which is easy to be debonded on the stainless steel carrier plate 1 shown in fig. 18, as shown in fig. 19;
2. the chip 3 is stuck on the temporary bonding layer 2 in a Face down manner, as shown in fig. 20;
3. as shown in fig. 21, the chip 3 is subjected to injection molding to form a molding layer 4 to protect the chip 3;
4. as shown in fig. 22, the temporary bonding layer 2 and the carrier 1 therebelow are removed, and the surface is plasma cleaned to avoid organic residue;
5. as shown in fig. 23, a laser hole-opening blocking layer 5 with a thickness of 8 μm is adhered on the I/O interface of the chip 3;
6. as shown in fig. 24, an ABF dielectric layer 6 is stuck on the laser opening blocking layer 5;
7. as shown in fig. 25, the ABF dielectric layer 6 is opened by using a laser, and the laser cannot open any further when encountering the laser opening blocking layer 5;
8. as shown in fig. 26, the laser barrier layer 5 is removed by plasma dry etching to expose the I/O interface of the chip 3;
9. as shown in fig. 27, a Ti/Cu seed layer 7 is formed by PVD, sputtering;
10. a photosensitive dry film 8 is laminated on the surface of the seed layer 7 (fig. 28), and exposure and development (fig. 29) and pattern plating are performed at positions where a subsequent wiring is not required to be formed, to obtain a rewiring layer 9 (fig. 30).
11. Then, a film removing process is performed, and an unnecessary Ti/Cu seed layer 7 is removed by a differential etching method (FIG. 31).
12. And finally, coating photosensitive ink, carrying out exposure, development, curing treatment and surface treatment to form a solder mask layer 10, exposing a pad area of the rewiring layer 9 (figure 32), implanting solder balls 11 into the pad area (figure 33), and cutting to obtain the required single packaging body.
The above examples are only intended to illustrate the detailed process of the present invention, and the present invention is not limited to the above detailed process, i.e., it is not intended that the present invention necessarily depends on the above detailed process for its implementation. It is understood by those skilled in the art that any modification of the present invention, equivalent substitutions of the raw materials of the product of the present invention and the addition of auxiliary components, selection of specific modes, etc., are within the scope and disclosure of the present invention.

Claims (10)

1. A preparation method of a fan-out type packaging structure with a laser opening blocking layer is characterized by comprising the following steps:
s10, providing a carrier plate and a plurality of chips, packaging the chips on one side of the carrier plate by adopting a plastic package material, and then removing the carrier plate to expose the front surfaces of the chips out of the plastic package material;
s20, providing a laser opening blocking layer and a dielectric layer, attaching the laser opening blocking layer to the front surface of the chip and attaching the dielectric layer to the laser opening blocking layer, carrying out laser opening processing on the dielectric layer to form a through hole, and removing the laser opening blocking layer at the through hole to expose an I/O interface of the chip;
and S30, manufacturing a seed layer and a rewiring layer, and leading out the chip to be electrically connected with the metal bump in a welding mode.
2. The method for manufacturing the fan-out package structure with the laser opening blocking layer according to claim 1, wherein the raw materials of the laser opening blocking layer comprise: organic silicon resin, polycarbosilane, glass powder and heat-resistant filler.
3. The method of claim 2, wherein the heat resistant filler comprises BN and/or SiO2。
4. The method for manufacturing the fan-out package structure with the laser opening blocking layer according to claim 1, wherein the thickness of the laser opening blocking layer is 5-10 μm.
5. The method of claim 1, wherein the difference in thickness of the laser aperture stop layer is less than 5%.
6. The method for manufacturing the fan-out package structure with the laser opening blocking layer according to claim 1, wherein the step S10 specifically includes:
s10a, providing a carrier plate and a temporary bonding layer, and attaching the temporary bonding layer to one side face of the carrier plate;
s10b, providing a plurality of chips, and adhering the front surfaces of the chips to the temporary bonding layer towards the side far away from the carrier plate;
s10c, packaging the chip by adopting a plastic package material, and forming a plastic package layer after the plastic package material is solidified;
s10d, grinding the plastic packaging layer to enable the front surface of the chip to be flush with the surface of the ground plastic packaging layer;
s10e, removing the temporary bonding layer and the carrier plate.
7. The method for manufacturing the fan-out package structure with the laser opening blocking layer according to claim 1, wherein the step S10 specifically includes:
s10a, providing a carrier plate and a temporary bonding layer, and attaching the temporary bonding layer to one side face of the carrier plate;
s10b, providing a plurality of chips, and adhering the front surfaces of the chips to the temporary bonding layer towards one side close to the carrier plate;
s10c, packaging the chip by adopting a plastic package material, and forming a plastic package layer after the plastic package material is solidified;
s10d, removing the temporary bonding layer and the carrier plate;
and S10e, cleaning the front surface of the chip by using plasma.
8. The method for manufacturing the fan-out package structure with the laser opening blocking layer according to claim 1, wherein the step S30 specifically includes:
s30a, manufacturing seed layers in the through holes and on the dielectric layer in an electroplating, chemical plating or PVD mode;
s30b, providing a photosensitive dry film, and attaching the photosensitive dry film to the seed layer;
s30c, forming a patterning hole exposing part of the seed layer on the photosensitive dry film through exposure and development processing, and enabling the patterning hole to at least correspond to the I/O interface position of the chip;
s30d, electroplating the patterned holes to form a rewiring layer in the patterned holes;
s30e, removing the residual photosensitive dry film to expose part of the seed layer;
s30f, etching the exposed seed layer, and removing the seed layer;
s30g, coating photosensitive ink on one surface, far away from the plastic package layer, of the dielectric layer, and enabling the photosensitive ink to cover the dielectric layer and the rewiring layer; forming a solder mask layer with a patterned hole through exposure, development and curing treatment, wherein a pad area of the rewiring layer is exposed out of the solder mask layer;
and S30h, providing a metal bump, and implanting the metal bump into the pad area.
9. The method for manufacturing the fan-out package structure with the laser opening blocking layer according to claim 8, wherein the step S30a specifically comprises: and sequentially manufacturing a titanium metal layer and a copper metal layer in the through hole and on the dielectric layer in an electroplating, chemical plating or PVD (physical vapor deposition) mode, wherein the titanium metal layer and the copper metal layer form the seed layer.
10. A fan-out package structure having a laser-open barrier layer, characterized in that it is manufactured by the method of any one of claims 1 to 9.
CN201910841901.6A 2019-09-06 2019-09-06 Fan-out type packaging structure with laser opening blocking layer and preparation method thereof Active CN110620053B (en)

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Denomination of invention: Fan out packaging structure with laser opening barrier layer and its preparation method

Effective date of registration: 20211229

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Pledgee: Guangdong Shunde Rural Commercial Bank Co.,Ltd. science and technology innovation sub branch

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Address before: Room A107, scientific research building, block a, neifo high tech think tank center, Nanhai Software Science Park, Shishan town, Nanhai District, Foshan City, Guangdong Province, 528225

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Patentee before: Guangdong Xinhua Microelectronics Technology Co.,Ltd.