CN115101427A - Manufacturing method of chip packaging structure and chip packaging structure - Google Patents

Manufacturing method of chip packaging structure and chip packaging structure Download PDF

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Publication number
CN115101427A
CN115101427A CN202211029413.3A CN202211029413A CN115101427A CN 115101427 A CN115101427 A CN 115101427A CN 202211029413 A CN202211029413 A CN 202211029413A CN 115101427 A CN115101427 A CN 115101427A
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China
Prior art keywords
chip
layer
barrier layer
substrate
stop barrier
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CN202211029413.3A
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Chinese (zh)
Inventor
张康
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Chengdu Yisiwei System Integrated Circuit Co ltd
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Chengdu Yisiwei System Integrated Circuit Co ltd
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Priority to CN202211029413.3A priority Critical patent/CN115101427A/en
Publication of CN115101427A publication Critical patent/CN115101427A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Abstract

In the embodiment, a stop barrier layer is firstly formed on a chip to be packaged, then the chip with the stop barrier layer is packaged to form a packaging layer, finally the packaging layer is ground, and the stop barrier layer is removed after being exposed from the packaging layer. Therefore, in the packaging process of the chip, the stop barrier layer is introduced above the chip to protect the chip, so that the problem that the quality of a connecting part of the chip is affected due to the damage of the chip in the grinding process of the packaging layer can be avoided, for example, the problem that the alignment is difficult in the subsequent process due to the fact that the pin of the chip is broken and the like caused by grinding can be avoided.

Description

Manufacturing method of chip packaging structure and chip packaging structure
Technical Field
The application relates to the technical field of semiconductor packaging, in particular to a manufacturing method of a chip packaging structure and the chip packaging structure.
Background
Fan-out package (Fan-out) technology is a common chip packaging technology in the manufacturing process of chip packaging structures. Among them, face-down (face-down) packages and face-up (face-up) packages are two commonly used types in fan-out type packaging technology. Whether a face-up fan-out type packaging process or a face-down fan-out type packaging process is adopted, the problems of chip alignment deviation or complex process steps and the like may exist.
Disclosure of Invention
In view of the above, in order to at least partially solve the above problems, the present application provides a method for manufacturing a chip package structure and a chip package structure.
First, in a first aspect, an embodiment of the present application provides a method for manufacturing a chip package structure, where the method includes:
manufacturing and forming a stopping barrier layer on a chip to be packaged, wherein the chip with the stopping barrier layer is positioned on a substrate;
packaging the chip with the stop barrier layer to form a packaging layer;
grinding the packaging layer to expose the stop barrier layer from the packaging layer;
removing the stop barrier layer exposed from the encapsulation layer.
According to a possible implementation manner of the first aspect, a stop barrier layer is formed on a chip to be packaged, and the stop barrier layer includes:
manufacturing a complete stop barrier layer on a wafer comprising a plurality of chips;
carrying out wafer cutting on the wafer with the stop barrier layer to obtain a plurality of independent chips with the stop barrier layer;
each individual chip with a stop barrier layer is transferred to the substrate by bulk transfer.
According to a possible implementation manner of the first aspect, a stop barrier layer is formed on a chip to be packaged, and the stop barrier layer includes:
carrying out wafer cutting on a wafer with a plurality of chips to obtain a plurality of independent chips and transferring each independent chip to a substrate through mass transfer;
manufacturing a whole stopping barrier layer covering each chip on the substrate;
and patterning the whole stop barrier layer to obtain independent chips with the stop barrier layers.
Based on a possible implementation manner of the first aspect, after the stop barrier layer is removed, a step difference is formed between one side of the encapsulation layer, which is far away from the substrate, and one side of the chip, which is far away from the substrate, so that the height of the encapsulation layer is greater than that of the chip, and a cavity is formed at the position of the chip.
In a possible implementation manner of the first aspect, the method further includes:
forming a dielectric layer on one side of the chip far away from the substrate through the cavity;
and forming a rewiring structure based on the dielectric layer, and enabling the rewiring structure to penetrate through the dielectric layer to be connected with the chip.
In a possible implementation manner of the first aspect, the method further includes:
and forming a solder ball on the rewiring structure by a ball mounting process.
In a possible implementation manner of the first aspect, the dielectric layer is located in the cavity; or
The dielectric layer is located in the cavity and extends from the cavity to above the encapsulation layer around the cavity.
In a second aspect, an embodiment of the present application further provides a chip package structure, which is manufactured by the above method, wherein the chip package structure includes a substrate, a chip located on the substrate, and a package layer surrounding four sides of the chip, wherein one side of the package layer, which is far away from the substrate, is higher than one side of the chip, which is far away from the substrate, so that a step difference is formed between the package layer and the chip, and the package layer surrounds the chip and forms a cavity above the chip.
Based on a possible implementation manner of the second aspect, the chip package structure further includes a dielectric layer located in the cavity, and a redistribution structure penetrating through the dielectric layer and connected to the chip.
According to a possible implementation manner of the second aspect, the chip packaging structure further includes solder balls located on the redistribution structure, and the dielectric layer extends from the cavity to above the packaging layer around the cavity.
Compared with the prior art, the manufacturing method of the chip packaging structure and the chip packaging structure provided by the embodiment of the application protect the chip by introducing the stop barrier layer above the chip in the chip packaging process, so that the problem that the quality of a chip connecting part is affected due to damage of the chip in the grinding process of the packaging layer can be avoided, for example, the problem that alignment is difficult in the subsequent process due to breakage and the like caused by grinding of chip pins can be avoided. In addition, compared with a face-down packaging mode, the process of substrate bonding twice is not needed, the complexity degree of the chip packaging process can be reduced, and the chip packaging cost is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a schematic process flow diagram of a common face-up chip packaging method according to an embodiment of the present disclosure.
Fig. 2 is a schematic process flow diagram of a common face-down chip packaging method according to an embodiment of the present disclosure.
Fig. 3 is a schematic flowchart of a manufacturing method of a chip package structure according to an embodiment of the present disclosure.
Fig. 4 is a schematic diagram of forming a stop barrier layer on a chip according to an embodiment of the present disclosure.
Fig. 5 is a second schematic diagram of forming a stop barrier layer on a chip according to an embodiment of the present disclosure.
Fig. 6 is a schematic plan view of individual chips after packaging with stop barriers.
Fig. 7 is a schematic cross-sectional view of a packaged single chip.
Fig. 8 is a schematic plan view of the encapsulation layer after polishing.
Fig. 9 is a schematic partial cross-sectional view of the encapsulation layer after polishing.
Fig. 10 is a schematic plan view of the removal of the stop barrier.
Fig. 11 is a partial cross-sectional schematic view after removal of the stop barrier.
Fig. 12 is a schematic plan view after forming the dielectric layer.
Fig. 13 is a schematic partial cross-sectional view after formation of the dielectric layer.
Fig. 14 is a schematic view of a chip package structure obtained by the manufacturing method according to the embodiment of the present application.
Fig. 15 is a schematic diagram of a chip package structure obtained by a conventional face-up-based packaging method.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined or explained in subsequent figures.
In the description of the present application, it is to be understood that the terms "upper", "lower", "inner", "outer", "left", "right", and the like, refer to orientations or positional relationships that are based on the orientations or positional relationships shown in the drawings, or the orientations or positional relationships that the products of the application conventionally position when in use, or the orientations or positional relationships that are conventionally understood by those skilled in the art, and are used for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated, and therefore, should not be construed as limiting the present application.
Furthermore, the terms "first," "second," and the like are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is also to be noted that, unless otherwise explicitly stated or limited, the terms "disposed" and "connected" are to be interpreted broadly, for example, "connected" may be a fixed connection, a detachable connection, or an integral connection; can be mechanically or electrically connected; the connection may be direct or indirect through an intermediate medium, and the connection may be internal to the two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as the case may be.
The following detailed description of embodiments of the present application will be made with reference to the accompanying drawings.
As for the technical problems described in the background art, the inventor of the present application has conducted research and analysis on the conventional full flow of the face-up packaging and face-down packaging operations, which are commonly used. Generally, for example, as shown in fig. 1, in the face-up packaging method, steps such as "coating temporary bonding glue on the substrate" - > chip transfer to substrate (PNP) - > EMC package (Mold) - > grinding (Grind) are required. In the Grind step, an etching (etch) step is required after grinding the EMC material, so that the connection portions (e.g., pins) of the chip are exposed from the EMC material, and a subsequent process (e.g., manufacturing a redistribution layer (RDL)) is performed. However, the inventors have found that this method easily causes quality problems of the copper pillar (Cu pilar) of the chip connection portion (e.g., cracks or ridges of the copper pillar due to over-etching or over-grinding), and further causes alignment difficulties of the chip connection portion in subsequent processes (e.g., alignment difficulties of the RDL structure and the Cu pilar).
For another example, as shown in fig. 2, the face-down packaging method needs to go through the steps of "coating a temporary bonding paste on a substrate" - > transferring a chip to a substrate (PNP) - > EMC package (Mold) - > carrier (carrier) bonding (Bond) - > substrate de-bonding (Debond), and the like. In this way, the production process needs to perform two times of substrate bonding processes, which results in complicated production process steps and increased production cost.
In order to at least partially solve the foregoing technical problem, an embodiment of the present application innovatively provides a method for manufacturing a chip package structure, which is shown in fig. 3 and is a schematic flow chart of the manufacturing method, and the manufacturing method is exemplarily described below with reference to the accompanying drawings.
Step S100, forming a stopping barrier layer 100 (stopping layer) on the chip to be packaged, wherein the chip on which the stopping barrier layer 100 is formed is located on the substrate 200.
In a possible implementation manner of the embodiment of the present application, as shown in fig. 4, for step S100, a complete stop barrier layer 100 may be first fabricated on a wafer (wafer) including a plurality of (a large number of) chips, then the wafer with the stop barrier layer 100 is subjected to wafer dicing (wafer dicing) to obtain a plurality of independent chips with the stop barrier layer 100, and finally, each independent chip with the stop barrier layer 100 is transferred onto the substrate 200 through bulk transfer.
In another possible implementation manner of the embodiment of the present application, as shown in fig. 5, in step S100, a wafer having a plurality of (a large number of) chips 400 may be first wafer diced (wafer dicing) to obtain a plurality of independent chips 400, and each independent chip 400 is transferred onto a substrate 200 by bulk transfer, then an entire stop barrier layer 100 covering each chip 400 is fabricated on the substrate 200, and finally the entire stop barrier layer 100 is patterned to obtain each independent chip 400 having the stop barrier layer 100. The patterning may be implemented by various commonly used patterning methods such as photolithography and development, laser etching, and the like, which are not described in detail in this embodiment.
The substrate 200 may be a bonding substrate provided with a temporary bonding paste.
Step S200 is performed to package the chip 400 having the stop barrier layer 100, so as to form the package layer 300.
In one possible implementation manner of the embodiment of the present application, for example, as shown in fig. 6 and 7, fig. 6 is a schematic plan view of each chip 400 having the stop barrier layer 100 after being packaged, and fig. 7 is a schematic cross-sectional view of a single packaged chip 400. The application can use an EMC material (Epoxy Molding Compound) to implement the above-mentioned packaging process. For example, an original chip packaging substrate (e.g., EMC substrate) may be placed on a molding machine, and the chip may be molded by a molding machine.
Step S300, the encapsulation layer 300 is polished to expose the stop barrier layer 100 from the encapsulation layer 300.
In a possible implementation manner of the embodiment of the present application, for example, as shown in fig. 8 and fig. 9, fig. 8 is a schematic plan view of the encapsulation layer 300 after being ground, and fig. 9 is a schematic partial cross-sectional view of the encapsulation layer 300 after being ground. By grinding the encapsulation layer 300, the encapsulation material above the stop barrier layer 100 can be removed, exposing the stop barrier layer 100 from the encapsulation layer 300. In this embodiment, the stop block layer 100 may be made of a metal material having a mask removal rate lower than that of the encapsulation layer 300, so that the chip 400 is prevented from being affected by the grinding process after the stop block layer 100 is ground and removed in the process of grinding and removing a portion of the encapsulation layer 300.
Step S400, removing the stop barrier layer 100 exposed from the encapsulation layer 300.
In a possible implementation manner of the embodiment of the present application, for example, as shown in fig. 10 and fig. 11, fig. 10 is a schematic plan view of removing the stop barrier layer 100, and fig. 11 is a schematic partial cross-sectional view of removing the stop barrier layer 100, after removing the stop barrier layer 100, the chip 400 may be exposed, and since the stop barrier layer 100 is removed, a step h is formed between a side of the encapsulation layer 300 away from the substrate 200 and a side of the chip 400 away from the substrate 200. Thus, the height of the package layer 300 is greater than that of the chip 400, and a cavity 410 is formed at the chip. In addition, the stop barrier layer 100 may be removed by etching, for example, a layer of photoresist may be coated on the stop barrier layer 100, a patterned window is formed on the photoresist through a patterned mask to expose the stop barrier layer 100, and finally the exposed stop barrier layer 100 is etched (e.g., wet etching) to remove the stop barrier layer 100.
In summary, in the embodiment of the present application, in the packaging process of the chip 400, the stop barrier layer 100 is introduced above the chip 400 to protect the chip 400, so that the chip 400 is prevented from being damaged in the grinding process of the packaging layer 300 to affect the quality of the connection portion of the chip 400, for example, the problem of alignment difficulty in the subsequent process due to cracking of the chip pins caused by grinding can be avoided. In addition, compared with a face-down packaging mode, the process of substrate bonding twice is not needed, the complexity degree of the chip packaging process can be reduced, and the chip packaging cost is reduced.
On the basis of the process flows of the above steps S100 to S400, the embodiment of the present application may further include a subsequent packaging process flow of the chip 400. For example, the process steps of steps S500 and S600 described below may also be included, as an example.
Step S500, a dielectric layer 500 is formed on one side of the chip 400 away from the substrate 200 through the cavity 410.
In this embodiment, for example, as shown in fig. 12 and fig. 13, fig. 12 is a schematic plan view after the dielectric layer 500 is formed, and fig. 13 is a schematic partial sectional view after the dielectric layer 500 is formed. The dielectric layer 500 may be only located at a position corresponding to the cavity 410. In other embodiments, for convenience of manufacturing, the dielectric layer 500 may be located in the cavity 410 and extend to the upper side of the encapsulation layer 300 around the cavity 410, so that the dielectric layer 500 may be manufactured by a full-layer coating manner, which facilitates the implementation of the process.
Step S600, forming a redistribution structure 600 based on the dielectric layer 500, and connecting the redistribution structure to the chip 400 through the dielectric layer 500, for example, to a connection portion (e.g., a chip pin) of the chip 400.
For example, as an example, a connection via penetrating through the dielectric layer 500 may be formed on the basis of the dielectric layer 500 through a photolithography process, and then the rewiring structure 600 may be grown on the dielectric layer 500 so as to be connected to the chip pin of the chip 400 through the connection via. The redistribution layer structure 600 may include a redistribution layer formed by multiple growth, which is not specifically limited in this embodiment.
Based on the above, in the embodiment of the present application, a solder ball 700 may be formed on the redistribution structure 600 through a ball-mounting process, for example, as shown in fig. 14, so as to facilitate electrical connection between the chip 400 and other electronic devices through the solder ball 700, thereby obtaining the chip package structure provided in the embodiment of the present application.
In summary, the chip package structure manufactured by the method provided by the embodiment of the present application is structurally different from the chip package structure manufactured by the conventional method (e.g., based on a face-up packaging method). For example, referring to fig. 14 and 15, fig. 15 is a chip package structure obtained by a conventional face-up based package method, in the chip package structure of fig. 15, five surfaces of the chip 400, i.e., four front, back, left, and right sides, and a side away from the substrate 200, are surrounded by a packaging material (e.g., an EMC material). In the present embodiment, as shown in fig. 14, since the stop barrier layer 100 is introduced during the manufacturing process, the surface of the chip 400 away from the substrate 200 is not surrounded by the encapsulation material, and only four sides of the chip 400 are surrounded by the encapsulation material.
On the basis of the above, the embodiment of the present application further provides a chip package structure manufactured based on the above manufacturing method. For example, in one possible implementation manner of the present embodiment, as shown in fig. 14, the chip package structure includes a substrate 200, a chip 400 located on the substrate 200, and a package layer 300 surrounding four sides of the chip 400. One side of the package layer 300 away from the substrate 200 is higher than one side of the chip 400 away from the substrate 200, so that a step is formed between the package layer 300 and the chip 400, and the package layer 300 surrounds the chip 400 and forms a cavity above the chip 400.
In addition, the chip packaging structure further includes a dielectric layer 500 located in the cavity, and a rewiring structure 600 penetrating through the dielectric layer 500 and connected to the chip 400. Meanwhile, the chip package structure may further include solder balls 700 located on the redistribution structure 600, so that the chip 400 is electrically connected to other electronic devices through the solder balls 700, and signal transmission of the chip 400 is achieved.
The dielectric layer 500 may be located only in the cavity, or may extend from the cavity to above the encapsulation layer 300.
In summary, according to the manufacturing method of the chip package structure and the chip package structure provided by the embodiment of the application, in the process of the package process of the chip 400, the stop barrier layer 100 is introduced above the chip 400 to protect the chip 400, so that the problem that the quality of the connection portion of the chip 400 is affected by damage to the chip 400 in the grinding process of the package layer 300 can be avoided, for example, the problem that the alignment is difficult in the subsequent process due to the breakage of the chip pins caused by grinding can be avoided. In addition, compared with the face-down packaging mode, the process of substrate bonding twice is not needed, the complexity of the chip packaging process can be reduced, and the chip packaging cost is reduced.
The foregoing description, for purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the application to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and its practical application, to thereby enable others skilled in the art to best utilize the application and various embodiments with various modifications as are suited to the particular use contemplated. The foregoing description, for purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the application to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and its practical application, to thereby enable others skilled in the art to best utilize the application and various embodiments with various modifications as are suited to the particular use contemplated.

Claims (10)

1. A method for manufacturing a chip packaging structure is characterized by comprising the following steps:
manufacturing and forming a stopping barrier layer on a chip to be packaged, wherein the chip with the stopping barrier layer is positioned on a substrate;
packaging the chip with the stop barrier layer to form a packaging layer;
grinding the encapsulation layer to expose the stop barrier layer from the encapsulation layer;
removing the stop barrier layer exposed from the encapsulation layer.
2. The method of claim 1, wherein forming a stop barrier layer on the die to be packaged comprises:
manufacturing a complete stop barrier layer on a wafer comprising a plurality of chips;
carrying out wafer cutting on the wafer with the stop barrier layer to obtain a plurality of independent chips with the stop barrier layer;
each individual chip with a stop barrier layer is transferred to the substrate by bulk transfer.
3. The method of claim 1, wherein forming a stop barrier layer on the die to be packaged comprises:
carrying out wafer cutting on a wafer with a plurality of chips to obtain a plurality of independent chips and transferring each independent chip to a substrate through mass transfer;
manufacturing a whole stop barrier layer covering each chip on the substrate;
and patterning the whole stop barrier layer to obtain independent chips with the stop barrier layers.
4. The method according to any one of claims 1 to 3, wherein after removing the stop barrier layer, a step is formed between a side of the encapsulation layer away from the substrate and a side of the chip away from the substrate, so that the height of the encapsulation layer is greater than that of the chip, thereby forming a cavity at the position of the chip.
5. The method of claim 4, further comprising:
forming a dielectric layer on one side of the chip far away from the substrate through the cavity;
and forming a rewiring structure based on the dielectric layer, and enabling the rewiring structure to penetrate through the dielectric layer to be connected with the chip.
6. The method of claim 5, further comprising:
and forming a solder ball on the rewiring structure by a ball mounting process.
7. The method of claim 5, wherein the dielectric layer is located within the cavity; or alternatively
The dielectric layer is located in the cavity and extends from the cavity to above the encapsulation layer around the cavity.
8. A chip package structure manufactured by the method of any one of claims 1 to 7, wherein the chip package structure comprises:
the packaging structure comprises a substrate, a chip positioned on the substrate and a packaging layer surrounding four sides of the chip, wherein one side, far away from the substrate, of the packaging layer is higher than one side, far away from the substrate, of the chip, so that a section difference is formed between the packaging layer and the chip, and then the packaging layer surrounds the chip and a cavity is formed above the chip.
9. The chip package structure according to claim 8, further comprising a dielectric layer located in the cavity, and a redistribution structure connected to the chip through the dielectric layer.
10. The chip package structure according to claim 9, further comprising solder balls on the redistribution structure, wherein the dielectric layer extends from the cavity to above the encapsulation layer around the cavity.
CN202211029413.3A 2022-08-26 2022-08-26 Manufacturing method of chip packaging structure and chip packaging structure Pending CN115101427A (en)

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Application publication date: 20220923